Signal transmission circuit for high frequency transmission

Abstract

A signal transmission circuit for high frequency transmission is provided. The signal transmission circuit includes an equalizer, a resonator and an adder. The equalizer receives an input signal and gains the input signal to generate a gain signal. The resonator receives the input signal and performs a high-frequency resonance operation on the input signal to generate a high-frequency resonance signal. The adder receives the gain signal and the high-frequency resonance signal, and adds the gain signal and the high-frequency resonance signal to generate an output signal.

Description

Technical Field

[0001] This invention relates to a signal transmission circuit, and more particularly to a signal transmission circuit for high-frequency transmission. Prior Technology

[0002] Signal transmission circuits can be used for wired communication transmission. However, when used for high-frequency transmission, the signal transmission circuit itself suffers from high-frequency losses. Therefore, how to provide a signal transmission circuit that can compensate for high-frequency signals is one of the key research focuses for those skilled in the art. Summary of the Invention

[0003] This invention provides a signal transmission circuit for high-frequency transmission, which can compensate for high-frequency signals.

[0004] In one embodiment of the present invention, the signal transmission circuit includes an equalizer, a resonator, and an adder. The equalizer receives an input signal and amplifies the input signal to generate a gain signal. The resonator receives the input signal and performs a high-frequency resonance operation on the input signal to generate a high-frequency resonant signal. The adder is coupled to the equalizer and the resonator. The adder receives the gain signal and the high-frequency resonant signal, and sums the gain signal and the high-frequency resonant signal to generate an output signal.

[0005] Based on the above, the resonator performs high-frequency resonance operation on the input signal to generate a high-frequency resonant signal. The adder uses the high-frequency resonant signal to compensate for the gain signal to generate the output signal. In this way, the high-frequency component of the output signal can be compensated. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 2 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 5 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 6 is a damping response diagram of a resonator according to an embodiment of the present invention. Figure 7 is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. Figure 8 is a schematic diagram of a resonator according to an embodiment of the present invention. Figure 9 is a schematic diagram of an amplifier according to an embodiment of the present invention. Implementation

[0007] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0008] Please refer to Figure 1, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 100 includes an equalizer 110, a resonator 120, and an adder 130. The equalizer 110 receives the input signal SIN and amplifies the input signal SIN to generate a gain signal SA. The resonator 120 receives the input signal SIN and performs a high-frequency resonance operation on the input signal SIN to generate a high-frequency resonant signal SR. The adder 130 is coupled to the equalizer 110 and the resonator 120. The adder 130 receives the gain signal SA and the high-frequency resonant signal SR. The adder 130 sums the gain signal SA and the high-frequency resonant signal SR to generate an output signal SOUT.

[0009] It is worth mentioning that resonator 120 performs high-frequency resonance operation on the input signal SIN to generate a high-frequency resonant signal SR. Adder 130 uses the high-frequency resonant signal SR to compensate the gain signal SA to generate the output signal SOUT. In this way, the high-frequency component of the output signal SOUT can be compensated by the high-frequency resonant signal SR.

[0010] Please refer to Figure 2, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 200 includes an equalizer 210, a resonator 220, an adder 230, a delay circuit 240, and a delay buffer 250. The equalizer 210 receives the input signal SIN and amplifies the input signal SIN to generate a gain signal SA. The delay circuit 240 is coupled between the equalizer 210 and the adder 230. The delay circuit 240 delays the timing of the gain signal SA. The resonator 220 receives the input signal SIN and performs a high-frequency resonance operation on the input signal SIN to generate a high-frequency resonant signal SR. The delay buffer 250 is coupled between the resonator 220 and the adder 230. The delay buffer 250 delays the timing of the high-frequency resonant signal SR.

[0011] In this embodiment, equalizer 210 and delay circuit 240 can be considered as the first signal path of signal transmission circuit 200. Furthermore, resonator 220 and delay buffer 250 can be considered as the second signal path of signal transmission circuit 200.

[0012] Generally, the high-frequency resonant signal SR has a timing delay compared to the input signal SIN. Therefore, the delay circuit 240 and the delay buffer 250 are designed to match the timing of the high-frequency resonant signal SR with the timing of the gain signal SA.

[0013] Please refer to Figure 3, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 300 includes an equalizer 210, a resonator 220, an adder 230, a delay circuit 240, a delay buffer 250, and a high-pass filter 360. In this embodiment, the cooperative operation of the equalizer 210, resonator 220, adder 230, delay circuit 240, and delay buffer 250 has been clearly described in the embodiment of Figure 2, and therefore will not be repeated here.

[0014] In this embodiment, a high-pass filter 360 is coupled to a resonator 220. The high-pass filter 360 receives the input signal SIN and filters out its low-frequency components. The high-pass filter 360 can output the high-frequency components of the input signal SIN. Therefore, the resonator 220 performs a high-frequency resonance operation on the high-frequency components of the input signal SIN to generate a high-frequency resonant signal SR.

[0015] In this embodiment, equalizer 210 and delay circuit 240 can be considered as the first signal path of signal transmission circuit 300. In addition, resonator 220, delay buffer 250 and high-pass filter 360 can be considered as the second signal path of signal transmission circuit 300.

[0016] Please refer to Figure 4, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 400 includes an equalizer 410, a resonator 420, an adder 230, a delay circuit 440, a delay buffer 450, and a high-pass filter 360. The equalizer 410 may be implemented by amplifiers A1(1) and A1(2). The delay circuit 440 may be implemented by amplifiers A1(3) to A1(M). The delay buffer 450 may be implemented by amplifiers A2(1) to A2(N). In this embodiment, amplifiers A1(1) to A1(M) are connected in series with each other. Amplifiers A2(1) to A2(N) are connected in series with each other.

[0017] When resonator 420 generates a high-frequency resonant signal SR, the high-frequency resonant signal SR will have a timing delay compared to the input signal SIN. Therefore, signal transmission circuit 400 uses amplifiers A1(1)~A1(M) to delay the timing of the gain signal SA for the first time, and uses amplifiers A2(1)~A2(N) to delay the timing of the high-frequency resonant signal SR for the second time, thereby matching the timing of the high-frequency resonant signal SR and the timing of the gain signal SA. The first delay is greater than the second delay. The number of amplifiers A1(1)~A1(M) in series is greater than the number of amplifiers A2(1)~A2(N) in series. Assuming that amplifiers A1(1)~A1(M) and A2(1)~A2(N) have the same delay, then (M) is designed to be greater than (N) or greater than (N+1). In this embodiment, amplifiers A1(1)~A1(M) and A2(1)~A2(N) are implemented by variable gain amplifiers or buffers, respectively.

[0018] In this embodiment, the resonator 420 includes a resonant buffer 421, a resonant inductor LR, and a resonant capacitor CR. The input terminal of the resonant buffer 421 receives the input signal SIN. The output terminal of the resonant buffer 421 outputs a high-frequency resonant signal SR. The resonant inductor LR is coupled between the output terminal of the resonant buffer 421 and the reference bias voltage VB. The resonant capacitor CR is coupled between the output terminal of the resonant buffer 421 and the reference bias voltage VB. In some embodiments, the resonant capacitor CR may be a variable capacitor.

[0019] In this embodiment, the resonant buffer 421 receives the input signal SIN via the high-pass filter 360. Therefore, the resonant buffer 421 receives the high-frequency components of the input signal SIN. The resonant inductor LR provides the resonant inductance value. The parasitic resistance of the resonant inductor LR provides the resonant resistance value. The resonant capacitor CR provides the resonant capacitance value. The resonant inductor LR and the resonant capacitor CR can form a resonance tank to perform high-frequency resonant operation on the high-frequency components of the input signal SIN.

[0020] In some embodiments, the high-pass filter 360 may be omitted.

[0021] Please refer to Figure 5, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 500 includes an equalizer 510, a resonator 520, an adder 530, a delay circuit 540, a delay buffer 550, and a high-pass filter 560. The equalizer 510 includes equalizing transistors M1-M4, current sources IB1-IB4, resistors R1-R4, and parameter circuits 511 and 512. The first terminal of equalizing transistor M1 is coupled to a reference bias voltage VB. The first terminal of equalizing transistor M1 is coupled to the reference bias voltage VB via resistor R1. The control terminal of equalizing transistor M1 receives a first differential input signal SINp from the input signal SIN. The first terminal of equalizing transistor M2 is coupled to the reference bias voltage VB. The first terminal of equalizing transistor M2 is coupled to the reference bias voltage VB via resistor R2. The control terminal of equalizing transistor M2 receives a second differential input signal SINn from the input signal SIN. Current source IB1 is coupled between the second terminal of equalizing transistor M1 and a reference low voltage (e.g., ground). Current source IB2 is coupled between the second terminal of equalizing transistor M2 and a reference low voltage (e.g., ground). Current sources IB1 and IB2 are used to provide bias current for equalizer 510.

[0022] In this embodiment, parameter circuit 511 is coupled between the second terminal of equalizing transistor M1 and the second terminal of equalizing transistor M2. Parameter circuit 511 can be used to adjust at least one of the gain and bandwidth of equalizer 510. Parameter circuit 511 includes resistor RP1 and capacitor CP1. Resistor RP1 is coupled between the second terminal of equalizing transistor M1 and the second terminal of equalizing transistor M2. Capacitor CP1 is coupled between the second terminal of equalizing transistor M1 and the second terminal of equalizing transistor M2. Resistor RP1 can be a variable resistor. Resistor RP1 can provide a variable resistance value. Changes in the variable resistance value can be used to adjust the gain of equalizer 510. For example, the higher the variable resistance value, the lower the gain of equalizer 510. The lower the variable resistance value, the higher the gain of equalizer 510.

[0023] In some embodiments, capacitor CP1 may be a variable capacitor. Capacitor CP1 can provide a variable capacitance value. Changes in the variable capacitance value can be used to adjust the bandwidth of equalizer 510. For example, a higher variable capacitance value results in a narrower bandwidth for equalizer 510, while a lower variable capacitance value results in a wider bandwidth for equalizer 510.

[0024] In this embodiment, the first terminal of equalizing transistor M3 is coupled to the reference bias voltage VB. The first terminal of equalizing transistor M3 is coupled to the reference bias voltage VB via resistor R3. The control terminal of equalizing transistor M3 is coupled to the first terminal of equalizing transistor M2. The first terminal of equalizing transistor M4 is coupled to the reference bias voltage VB. The first terminal of equalizing transistor M4 is coupled to the reference bias voltage VB via resistor R4. The control terminal of equalizing transistor M4 is coupled to the first terminal of equalizing transistor M1. Current source IB3 is coupled between the second terminal of equalizing transistor M3 and a reference low voltage (e.g., ground). Current source IB4 is coupled between the second terminal of equalizing transistor M4 and a reference low voltage (e.g., ground). Current sources IB3 and IB4 are used to provide bias current for equalizer 510.

[0025] In this embodiment, the parameter circuit 512 is coupled between the second terminal of the equalizing transistor M3 and the second terminal of the equalizing transistor M4. The first terminal of the equalizing transistor M3 outputs a first differential gain signal SA1 of the gain signal SA. The first terminal of the equalizing transistor M4 outputs a second differential gain signal SA2 of the gain signal SA.

[0026] In this embodiment, the parameter circuit 512 includes resistors RP2 and RP3 and capacitor CP2. Resistor RP2 is coupled between the second terminal of transistor M3 and the second terminal of transistor M4. Resistor RP2 and capacitor CP2 are connected in series between the second terminals of transistors M3 and M4. Resistors RP2 and RP3 each have a fixed resistance value. Capacitor CP2 has a fixed capacitance value.

[0027] In some embodiments, parameter circuit 512 can also be used to adjust at least one of the gain and bandwidth of equalizer 510. For example, at least one of resistors RP2 and RP3 can be a variable resistor. For example, capacitor CP2 can be a variable capacitor.

[0028] In some embodiments, the circuit implementation of parameter circuit 512 may be similar to the circuit implementation of parameter circuit 511.

[0029] In this embodiment, equalizing transistors M1 and M2, current sources IB1 and IB2, resistors R1 and R2, and parameter circuit 511 can be the first-stage circuit of equalizer 510. Equalizing transistors M3 and M4, current sources IB3 and IB4, resistors R3 and R4, and parameter circuit 512 can be the second-stage circuit of equalizer 510.

[0030] In some embodiments, the second-stage circuitry of equalizer 510 may be omitted. Therefore, the first terminal of equalizer M1 outputs a first differential gain signal SA1 of the gain signal SA. The first terminal of equalizer M2 outputs a second differential gain signal SA2 of the gain signal SA.

[0031] In this embodiment, the delay circuit 540 includes transistors M5-M8, current sources IB5 and IB6, and resistors R5 and R6. The first terminal of transistor M5 is coupled to the reference bias voltage VB. The first terminal of transistor M5 is coupled to the reference bias voltage VB via resistor R5. The control terminal of transistor M5 receives a first differential gain signal SA1. The first terminal of transistor M6 is coupled to the reference bias voltage VB. The first terminal of transistor M6 is coupled to the reference bias voltage VB via resistor R6. The control terminal of transistor M6 receives a second differential gain signal SA2. Current source IB5 is coupled to the second terminals of transistors M5 and M6 and a reference low voltage. The first terminal of transistor M7 is coupled to adder 530. The control terminal of transistor M7 is coupled to the first terminal of transistor M6. The first terminal of transistor M8 is coupled to adder 530. The control terminal of transistor M8 is coupled to the first terminal of transistor M5. Current source IB6 is coupled to the second terminals of transistors M7 and M8 and to the reference low voltage. Current sources IB5 and IB6 are used to provide bias current for delay circuit 540.

[0032] In this embodiment, the first terminal of transistor M8 outputs a delayed first differential gain signal SA1'. The first terminal of transistor M7 outputs a delayed second differential gain signal SA2'.

[0033] In this embodiment, resistors R5 and R6, transistors M5 and M6, and current source IB5 can be the first stage circuit of delay circuit 540. Transistors M7 and M8, and current source IB6 can be the second stage circuit of delay circuit 540.

[0034] In this embodiment, the high-pass filter 560 includes inductors LF1 and LF2. A first terminal of inductor LF1 is coupled to a reference bias voltage VB. A second terminal of inductor LF1 is coupled to a resonator 520. The second terminal of inductor LF1 receives a first differential input signal SINp from the input signal SIN via resistor R9. A first terminal of inductor LF2 is coupled to the reference bias voltage VB. The second terminal of inductor LF2 is coupled to the resonator 520. The second terminal of inductor LF2 receives a second differential input signal SINn from the input signal SIN via resistor R10. The high-pass filter 560 filters out the low-frequency components of both the first differential input signal SINp and the second differential input signal SINn.

[0035] In this embodiment, the resonator 520 includes a resonant buffer 521 and a resonant circuit 522. The resonant buffer 521 includes resistors R7 and R8, resonant transistors MN1 and MN2, and a resonant current source IB7. The first terminal of resonant transistor MN1 is coupled to a reference bias voltage VB. The first terminal of resonant transistor MN1 is coupled to the reference bias voltage VB via resistor R7. The control terminal of resonant transistor MN1 receives a first differential input signal SINp. It should be noted that the high-pass filter 560 filters out the low-frequency components of the first differential input signal SINp of the input signal SIN. Therefore, the control terminal of resonant transistor MN1 receives the high-frequency components of the first differential input signal SINp. The first terminal of resonant transistor MN2 is coupled to the reference bias voltage VB. The first terminal of resonant transistor MN2 is coupled to the reference bias voltage VB via resistor R8. The control terminal of resonant transistor MN2 receives a second differential input signal SINn. It should be noted that the high-pass filter 560 filters out the low-frequency components of the second differential input signal SINn of the input signal SIN. Therefore, the control terminal of the resonant transistor MN2 receives the high-frequency component of the second differential input signal SINn.

[0036] The resonant current source IB7 is coupled to the resonant transistors MN1 and MN2 and the reference low voltage. The resonant current source IB7 is used to provide the bias current for the resonator 520.

[0037] The resonant circuit 522 includes a resonant capacitor CR and a resonant inductor LR. The resonant capacitor CR is coupled between the first terminal of the resonant transistor MN1 and the first terminal of the resonant transistor MN2. The resonant inductor LR and the resonant capacitor CR can form a resonant slot to perform high-frequency resonance operation on the high-frequency components of the first differential input signal SINp and the second differential input signal SINn to generate a first differential resonant signal SR1 and a second differential resonant signal SR2.

[0038] In this embodiment, the delay buffer 550 includes transistors M9 and M10 and a current source IB8. The first terminal of transistor M9 is coupled to adder 530. The control terminal of transistor M9 is coupled to the first terminal of resonant transistor MN2 to receive the second differential resonant signal SR2. The first terminal of transistor M10 is coupled to adder 530. The control terminal of transistor M10 is coupled to the first terminal of transistor M7 to receive the first differential resonant signal SR1. The current source IB8 is coupled to the second terminals of transistors M9 and M10 and a reference low voltage.

[0039] In this embodiment, the first terminal output of transistor M10 outputs a delayed first differential resonant signal SR1'. The first terminal output of transistor M9 outputs a delayed second differential resonant signal SR2'. Current source IB8 is used to provide bias current for delay buffer 550.

[0040] In this embodiment, adder 530 includes resistors RA1 and RA2. A first terminal of resistor RA1 is coupled to a reference bias voltage VB. A second terminal of resistor RA1 receives a delayed first differential resonant signal SR1' and a delayed first differential gain signal SA1'. Therefore, adder 530 can sum the delayed first differential resonant signal SR1' and the delayed first differential gain signal SA1' to generate a first differential output signal SOp for output signal SOUT.

[0041] The first terminal of resistor RA2 is coupled to the reference bias voltage VB. The second terminal of resistor RA2 receives the delayed second differential resonant signal SR2' and the delayed second differential gain signal SA2'. Therefore, adder 530 can sum the delayed second differential resonant signal SR2' and the delayed second differential gain signal SA2' to generate a second differential output signal SOn for output signal SOUT.

[0042] In some embodiments, resistors R1 to R10 may be omitted. Resistors R1 to R10 may be replaced by the parasitic resistance of the circuit itself.

[0043] In this embodiment, the equalizing transistors M1~M4, transistors M5~M10, and resonant transistors MN1 and MN2 are all implemented using N-type transistors. This invention is not limited to the type of N-type transistor.

[0044] Please refer to Figures 5 and 6. Figure 6 is a damping response diagram of a resonator according to an embodiment of the present invention. In this embodiment, Figure 6 shows curves CV1 to CV6. The horizontal axis represents time. The vertical axis represents the intensity of the signal (e.g., the first differential resonant signal SR1 and the second differential resonant signal SR2). Curves CV1 to CV6 respectively represent different damping responses provided by the resonant circuit 522 of the resonator 520. The resonant capacitor CR provides the resonant capacitance value. The resonant inductor LR provides the resonant inductance value and the resonant resistance value. The resonant capacitance value, resonant inductance value, and resonant resistance value determine the damping coefficient. Curve CV1 corresponds to a damping response with a damping coefficient equal to "0". Curve CV2 corresponds to a damping response with a damping coefficient equal to "0.1". Curve CV3 corresponds to a damping response with a damping coefficient equal to "0.2". Curve CV4 corresponds to a damping response with a damping coefficient equal to "0.3". Curve CV5 corresponds to a damping response with a damping coefficient equal to "0.5". Curve CV6 corresponds to the damped response when the damping coefficient is equal to "1". As shown in Figure 6, curves CV1~CV4 exhibit resonant responses. Therefore, the damping coefficient can be designed to be less than 0.5, thereby enabling the resonant circuit 522 to achieve resonant functionality.

[0045] Please refer to Figure 7, which is a schematic diagram of a signal transmission circuit according to an embodiment of the present invention. In this embodiment, the signal transmission circuit 600 includes an equalizer 610, a resonator 620, an adder 630, a delay circuit 640, a delay buffer 650, and a high-pass filter 660. The equalizer 610 includes equalizing transistors M1-M4, current sources IB1-IB4, resistors R1-R4, and parameter circuits 611 and 612. The implementation of equalizing transistors M1 and M2, current sources IB1 and IB2, resistors R1 and R2, and parameter circuit 611 is similar to the implementation of equalizing transistors M1 and M2, current sources IB1 and IB2, resistors R1 and R2, and parameter circuit 611 shown in Figure 5, and therefore will not be repeated here.

[0046] In this embodiment, the first terminal of the equalizing transistor M3 is coupled to the reference bias voltage VB. The first terminal of the equalizing transistor M3 is coupled to the reference bias voltage VB via resistor R3. The control terminal of the equalizing transistor M3 is coupled to the first terminal of the equalizing transistor M2. The first terminal of the equalizing transistor M4 is coupled to the reference bias voltage VB. The first terminal of the equalizing transistor M4 is coupled to the reference bias voltage VB via resistor R4. The control terminal of the equalizing transistor M4 is coupled to the first terminal of the equalizing transistor M1. Current source IB3 is coupled between the second terminal of the equalizing transistor M3 and a reference low voltage (e.g., ground). Current source IB4 is coupled between the second terminal of the equalizing transistor M4 and a reference low voltage (e.g., ground). Parameter circuit 612 is coupled between the second terminals of the equalizing transistors M3 and M4.

[0047] In this embodiment, the first terminal of the equalization transistor M3 outputs a first differential gain signal SA1, which is a gain signal SA. The first terminal of the equalization transistor M4 outputs a second differential gain signal SA2, which is a gain signal SA.

[0048] In this embodiment, the parameter circuit 612 includes a resistor RP2 and a capacitor CP2. Resistor RP2 is coupled between the second terminal of the equalizing transistor M3 and the second terminal of the equalizing transistor M4. Resistor RP2 and capacitor CP2 are connected in series between the second terminals of the equalizing transistors M3 and M4. Resistor RP2 has a fixed resistance value. Capacitor CP2 has a fixed capacitance value.

[0049] In some embodiments, resistor RP2 may be a variable resistor. Capacitor CP2 may be a variable capacitor.

[0050] In this embodiment, the equalizing transistors M1 and M2, current sources IB1 and IB2, resistors R1 and R2, and parameter circuit 611 can be the first-stage circuit of equalizer 610. The equalizing transistors M3 and M4, current sources IB3 and IB4, resistors R3 and R4, and parameter circuit 612 can be the second-stage circuit of equalizer 610.

[0051] In some embodiments, the second-stage circuitry of the equalizer 610 may be omitted. Therefore, the first terminal of the equalizer M1 outputs a first differential gain signal SA1 of the gain signal SA. The first terminal of the equalizer M2 outputs a second differential gain signal SA2 of the gain signal SA.

[0052] In this embodiment, the delay circuit 540 includes transistors M5, M6, MN7, MN8, MP7, MP8, current sources IB5 and IB6, and resistors R5, R6, and RM. The first terminal of transistor M5 is coupled to the reference bias voltage VB. The first terminal of transistor M5 is coupled to the reference bias voltage VB via resistor R5. The control terminal of transistor M5 receives a first differential gain signal SA1. The first terminal of transistor M6 is coupled to the reference bias voltage VB. The first terminal of transistor M6 is coupled to the reference bias voltage VB via resistor R6. The control terminal of transistor M6 receives a second differential gain signal SA2. Current source IB5 is coupled to the second terminal of transistor M5 and a reference low voltage. Current source IB6 is coupled to the second terminal of transistor M6 and a reference low voltage. Resistor RM is coupled between the second terminals of transistors M5 and M6.

[0053] Transistor MP7's first terminal is coupled to the reference bias voltage VB. Transistor MP7's second terminal is coupled to adder 530. Transistor MP7's control terminal is coupled to the first terminal of transistor M6. Transistor MP8's first terminal is coupled to the reference bias voltage VB. Transistor MP8's control terminal is coupled to the first terminal of transistor M5. Transistor MP8's second terminal is coupled to adder 530. Transistor MN7's first terminal is coupled to the second terminal of transistor MP7. Transistor MN7's second terminal is coupled to the reference low voltage. Transistor MN7's control terminal is coupled to the first terminal of transistor M6. Transistor MN8's first terminal is coupled to the second terminal of transistor MP8. Transistor MN8's second terminal is coupled to the reference low voltage. Transistor MN8's control terminal is coupled to the first terminal of transistor M5.

[0054] In this embodiment, the first terminal of transistor MN8 outputs a delayed first differential gain signal SA1'. The first terminal of transistor MN7 outputs a delayed second differential gain signal SA2'.

[0055] In this embodiment, transistors M5 and M6, current sources IB5 and IB6, and resistor RM can be the first stage circuit of delay circuit 640. Transistors MN7, MN8, MP7, and MP8 can be the second stage circuit of delay circuit 640.

[0056] In this embodiment, the high-pass filter 660 includes capacitors CF1 and CF2. The first terminal of capacitor CF1 receives the first differential input signal SINp of the input signal SIN. The first terminal of capacitor CF1 is coupled to the reference bias voltage VB via resistor R9. The second terminal of capacitor CF1 is coupled to resonator 620. The first terminal of capacitor CF2 receives the second differential input signal SINn of the input signal SIN. The first terminal of capacitor CF2 is coupled to the reference bias voltage VB via resistor R10. The second terminal of capacitor CF2 is coupled to resonator 620. The high-pass filter 660 filters out the low-frequency components of the first differential input signal SINp of the input signal SIN, and also filters out the low-frequency components of the second differential input signal SINn of the input signal SIN.

[0057] In this embodiment, the resonator 620 includes a resonant buffer 621 and a resonant circuit 622. The resonant buffer 621 includes resonant transistors MN1, MN2, MP1, and MP2. The first terminal of transistor MP1 is coupled to a reference bias voltage VB. The control terminal of transistor MP1 receives a first differential input signal SINp from the input signal SIN. The first terminal of resonant transistor MN1 is coupled to a second terminal of transistor MP1. The second terminal of resonant transistor MN1 is coupled to a reference low voltage. The control terminal of transistor MN1 receives the first differential input signal SINp from the input signal SIN. It should be noted that the high-pass filter 660 filters out the low-frequency components of the first differential input signal SINp from the input signal SIN. Therefore, the control terminals of resonant transistors MP1 and MN1 jointly receive the high-frequency components of the first differential input signal SINp. The first terminal of transistor MP2 is coupled to the reference bias voltage VB. The control terminal of transistor MP2 receives a second differential input signal SINn from the input signal SIN. The first terminal of resonant transistor MN2 is coupled to the second terminal of transistor MP2. The second terminal of resonant transistor MN2 is coupled to a reference low voltage. The control terminal of transistor MN2 receives the second differential input signal SINn from the input signal SIN. It should be noted that the high-pass filter 660 filters out the low-frequency components of the second differential input signal SINn from the input signal SIN. Therefore, the control terminals of resonant transistors MP2 and MN2 jointly receive the high-frequency components of the second differential input signal SINn.

[0058] The resonant circuit 622 includes a resonant resistor RR, a resonant capacitor CR, and a resonant inductor LR. The resonant capacitor CR is coupled between the first terminals of resonant transistor MN1 and MN2. The resonant resistor RR is coupled between the first terminals of resonant transistor MN1 and MN2. The resonant inductor LR is coupled between the first terminals of resonant transistor MN1 and MN2. The resonant inductor LR and the resonant capacitor CR can form a resonant slot to perform high-frequency resonance operation on the high-frequency components of the first differential input signal SINp and the second differential input signal SINn to generate a first differential resonant signal SR1 and a second differential resonant signal SR2.

[0059] In some embodiments, the resonant capacitor CR can be a variable capacitor. In some embodiments, the resonant resistor RR can be a variable resistor.

[0060] In some embodiments, the resonant resistor RR can be omitted. The resonant resistor RR can be replaced by the parasitic resistance of the resonant inductor LR.

[0061] In this embodiment, the delay buffer 650 includes transistors MN9, MN10, MP9, and MP10. The first terminal of transistor MP9 is coupled to a reference bias voltage VB. The control terminal of transistor MP9 is coupled to the first terminal of resonant transistor MN2 to receive the second differential resonant signal SR2. The first terminal of transistor MN9 is coupled to the second terminal of transistor MP9. The second terminal of transistor MN9 is coupled to a reference low voltage. The control terminal of transistor MN9 is coupled to the first terminal of resonant transistor MN2 to receive the second differential resonant signal SR2.

[0062] The first terminal of transistor MP10 is coupled to the reference bias voltage VB. The control terminal of transistor MP10 is coupled to the first terminal of resonant transistor MN1 to receive the first differential resonant signal SR1. The first terminal of transistor MN10 is coupled to the second terminal of transistor MP10. The second terminal of transistor MN10 is coupled to the reference low voltage. The control terminal of transistor MN10 is coupled to the first terminal of resonant transistor MN1 to receive the first differential resonant signal SR1.

[0063] In this embodiment, the first terminal of transistor MN10 outputs a delayed first differential resonant signal SR1'. The first terminal of transistor MN9 outputs a delayed second differential resonant signal SR2'.

[0064] In this embodiment, adder 630 includes resistor RA. A first terminal of resistor RA receives a delayed first differential resonant signal SR1' and a delayed first differential gain signal SA1'. Therefore, the first terminal of resistor RA can sum the delayed first differential resonant signal SR1' and the delayed first differential gain signal SA1' to generate a first differential output signal SOp for output signal SOUT. A second terminal of resistor RA receives a delayed second differential resonant signal SR2' and a delayed second differential gain signal SA2'. Therefore, the second terminal of resistor RA can sum the delayed second differential resonant signal SR2' and the delayed second differential gain signal SA2' to generate a second differential output signal SOn for output signal SOUT.

[0065] In this embodiment, the equalizing transistors M1-M4, transistors M5, M6, MN7-MN10, and resonant transistors MN1 and MN2 are all implemented using N-type transistors. This invention is not limited to the type of N-type transistor. Transistors MP7-MP10 and resonant transistors MP1 and MP2 are all implemented using P-type transistors. This invention is not limited to the type of P-type transistor.

[0066] Please refer to Figure 8, which is a schematic diagram of a resonator according to an embodiment of the present invention. In this embodiment, the resonator 720 includes a resonant buffer 721 and a resonant circuit 722. The resonant circuit 722 includes a resonant capacitor CR and resonant inductors LR1 and LR2. The resonant inductor LR1 is coupled between a reference bias voltage VB and a first terminal of the resonant capacitor CR. The resonant inductor LR2 is coupled between the reference bias voltage VB and a second terminal of the resonant capacitor CR. In this embodiment, the resonant inductors LR1 and LR2 each have parasitic resistance to generate a resonant resistance value. In some embodiments, the resonant capacitor CR may be a variable capacitor.

[0067] In this embodiment, the resonant buffer 721 includes resonant transistors MN1 and MN2 and a current source IB7. The first terminal of resonant transistor MN1 is coupled to the first terminal of resonant capacitor CR. The control terminal of resonant transistor MN1 receives a first differential input signal SINp. The first terminal of resonant transistor MN2 is coupled to the second terminal of resonant capacitor CR. The control terminal of resonant transistor MN2 receives a second differential input signal SINn. The resonant current source IB7 is coupled to the second terminals of resonant transistors MN1 and MN2. In this embodiment, the first terminal of resonant transistor MN1 is used to provide a first differential resonant signal SR1. The first terminal of resonant transistor MN2 is used to provide a second differential resonant signal SR2.

[0068] In this embodiment, the resonant transistors MN1 and MN2 are implemented by N-type transistors.

[0069] Please refer to Figures 5, 7, and 8. The resonator 520 in Figure 5 can be replaced by one of the resonators 620 in Figure 7 and 720 in Figure 8. The resonator 620 in Figure 7 can be replaced by one of the resonators 520 in Figure 5 and 720 in Figure 8.

[0070] Please refer to Figures 4 and 9. Figure 9 is a schematic diagram of an amplifier according to an embodiment of the present invention. In this embodiment, amplifiers A1(1)~A1(M) and A2(1)~A2(N) can be implemented by amplifier AX. Amplifier AX includes a current source IB9, transistors M11 and M12, and resistors R11 and R12. The first terminal of current source IB9 is coupled to a reference bias voltage VB. The first terminal of transistor M11 is coupled to the second terminal of current source IB9. The first terminal of transistor M12 is coupled to the second terminal of current source IB9. Resistor R11 is coupled between the second terminal of transistor M11 and a reference low voltage. Resistor R12 is coupled between the second terminal of transistor M12 and a reference low voltage. In this embodiment, the control terminals of transistors M11 and M12 receive an input signal SIN with a differential signal format or a differential signal from the previous stage amplifier. The second terminals of transistors M11 and M12 output differential signals in differential signal format to the next stage amplifier or adder 230.

[0071] In some embodiments, amplifiers A1(1)~A1(M) and A2(1)~A2(N) can be implemented by one of the following: the first stage circuit of the delay circuit 540 as shown in Figure 5 (i.e., the circuit combination of resistors R5, R6, transistors M5, M6 and current source IB5), the second stage circuit of the delay circuit 540 as shown in Figure 5 (i.e., the circuit combination of transistors M7, M8 and current source IB6), the second stage circuit of the delay circuit 640 as shown in Figure 6 (i.e., the circuit combination of transistors MN7, MN8, MP7, MP8), and amplifier AX as shown in Figure 9.

[0072] In summary, the resonator performs high-frequency resonance on the input signal to generate a high-frequency resonant signal. The adder uses this high-frequency resonant signal to compensate for the gain signal SA to generate the output signal. In this way, the high-frequency component of the output signal can be compensated by the high-frequency resonant signal.

[0073] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0074] 100, 200, 300, 400, 500, 600: Signal transmission circuit 110, 210, 410, 510, 610: equalizers 120, 220, 420, 520, 620, 720: Resonators 130, 230, 530, 630: Adders 240, 440, 540, 640: Delay circuits 250, 450, 550, 650: Delay buffers 360, 560, 660: High-pass filters 421, 521, 621, 721: Resonant Buffer 511, 512, 611, 612: Parameter Circuits 522, 622, 722: Resonant circuits A1(1)~A1(M), A2(1)~A2(N): Amplifier CF1, CF2, CP1, CP2: Capacitors CR: Resonant capacitor CV1~CV6: Curves IB1~IB6, IB8, IB9: Current Sources IB7: Resonant Current Source LF1, LF2: Inductors LR, LR1, LR2: Resonant inductors M1~M4: Isoelectric transistors M5~M12, MN7~MN10, MP7~MP10: Transistors MN1, MN2, MP1, MP2: Resonant transistors R1~R12, RA, RA1, RA2, RM, RP1, RP2, RP3: Resistors RR: Resonant resistor SA: Gain signal SA1: First differential gain signal SA1': Delayed first differential gain signal SA2: Second differential gain signal SA2': Delayed second differential gain signal SIN: Input signal SINn: Second differential input signal SINp: First differential input signal SOn: Second differential output signal SOp: First differential output signal SOUT: Output signal SR: High-frequency resonant signal SR1: First differential resonance signal SR1': Delayed first differential resonant signal SR2: Second differential resonance signal SR2': Delayed second differential resonant signal VB: Reference Bias

Claims

1. A signal transmission circuit for high-frequency transmission, comprising: An equalizer is configured to receive an input signal and amplify the input signal to generate a gained signal; A resonator is configured to receive the input signal and perform a high-frequency resonant operation on the input signal to generate a high-frequency resonant signal; An adder, coupled to the equalizer and the resonator, is configured to receive the gain signal and the high-frequency resonant signal, and sum the gain signal and the high-frequency resonant signal to generate an output signal.

2. The signal transmission circuit as claimed in claim 1, wherein the equalizer comprises: A first equalizing transistor, wherein a first terminal of the first equalizing transistor is coupled to a reference bias voltage, and a control terminal of the first equalizing transistor receives a first differential input signal of the input signal; A second equalizing transistor, the first terminal of which is coupled to a reference bias voltage, and the control terminal of which receives a second differential input signal of the input signal; a first current source coupled between the second terminal of the first equalizing transistor and a reference low voltage; a second current source coupled between the second terminal of the second equalizing transistor and the reference low voltage; and a first parameter circuit coupled between the second terminal of the first equalizing transistor and the second terminal of the second equalizing transistor.

3. The signal transmission circuit as claimed in claim 2, wherein the first parameter circuit comprises: A first variable resistor, coupled between the second terminal of the first equalizing transistor and the second terminal of the second equalizing transistor, is configured to provide a first variable resistance value.

4. The signal transmission circuit as claimed in claim 2, wherein the first parameter circuit comprises: A first variable capacitor, coupled between the second terminal of the first equalizing transistor and the second terminal of the second equalizing transistor, is configured to provide a second variable capacitance value.

5. The signal transmission circuit as claimed in claim 2, wherein the equalizer further comprises: The third equalization transistor has a first terminal coupled to a reference bias voltage and a control terminal coupled to the first terminal of the second equalization transistor. A fourth equalizing transistor, the first terminal of which is coupled to a reference bias voltage, and the control terminal of which is coupled to the first terminal of the first equalizing transistor; a third current source coupled between the second terminal of the third equalizing transistor and a reference low voltage; a fourth current source coupled between the second terminal of the fourth equalizing transistor and the reference low voltage; and a second parameter circuit coupled between the second terminal of the third equalizing transistor and the second terminal of the fourth equalizing transistor, wherein the first terminal of the fourth equalizing transistor outputs a first differential gain signal of the gain signal, and wherein the first terminal of the third equalizing transistor outputs a second differential gain signal of the gain signal.

6. The signal transmission circuit as claimed in claim 5, wherein the second parameter circuit comprises: A second variable resistor, coupled between the second terminal of the third equalizing transistor and the second terminal of the fourth equalizing transistor, is configured to provide a second variable resistance value.

7. The signal transmission circuit as claimed in claim 5, wherein the second parameter circuit comprises: A second variable capacitor, coupled between the second terminal of the third equalizing transistor and the second terminal of the fourth equalizing transistor, is configured to provide a second variable capacitance value.

8. The signal transmission circuit as described in claim 1, further comprising: A delay circuit, coupled between the equalizer and the adder, is configured to delay the timing of the gain signal.

9. The signal transmission circuit as described in claim 8, further comprising: A delay buffer, coupled between the resonator and the adder, is configured to delay the timing of the high-frequency resonant signal.

10. The signal transmission circuit as described in claim 9, wherein: The equalizer and the delay circuit together include a plurality of first amplifiers, the delay buffer includes a plurality of second amplifiers, and the number of the plurality of first amplifiers connected in series is greater than the number of the plurality of second amplifiers connected in series.

11. The signal transmission circuit as claimed in claim 1, wherein the resonator comprises: A resonant buffer, wherein the input terminal of the resonant buffer receives the input signal, and the output terminal of the resonant buffer outputs the high-frequency resonant signal; A resonant inductor is coupled between the output of the resonant buffer and the reference bias voltage; And a resonant capacitor, coupled between the output of the resonant buffer and the reference bias voltage.

12. The signal transmission circuit as described in claim 1, further comprising: A high-pass filter, coupled to the resonator, is configured to receive the input signal and filter out the low-frequency components of the input signal, thereby enabling the resonator to perform high-frequency resonance operation on the high-frequency components of the input signal to generate the high-frequency resonant signal.

13. The signal transmission circuit of claim 12, wherein the high-pass filter filters out the low-frequency components of the first differential input signal of the input signal and filters out the low-frequency components of the second differential input signal of the input signal.

14. The signal transmission circuit as claimed in claim 13, wherein the resonator comprises: A resonant buffer includes: a first resonant transistor, a first terminal of which is coupled to a reference bias voltage, and a control terminal of which receives a first differential input signal; a second resonant transistor, a first terminal of which is coupled to a reference bias voltage, and a control terminal of which receives a second differential input signal; a resonant current source coupled to a second terminal of the first resonant transistor, a second terminal of the second resonant transistor, and a reference low voltage; and a resonant circuit including: a resonant capacitor coupled between a first terminal of the first resonant transistor and a first terminal of the second resonant transistor; and a resonant inductor coupled between a first terminal of the first resonant transistor and a first terminal of the second resonant transistor.

15. The signal transmission circuit as described in claim 14, further comprising: A delay buffer, coupled to the second terminals of the first resonant transistor and the second resonant transistor, is configured to delay the timing of the first resonant signal and the timing of the second resonant signal of the high-frequency resonant signal, and to provide the first resonant signal and the second resonant signal to the adder.

16. The signal transmission circuit as claimed in claim 13, wherein the resonator comprises: A resonant buffer includes: a first P-type resonant transistor, a first terminal of which is coupled to a reference bias voltage, and a control terminal of which receives a first differential input signal; a second P-type resonant transistor, a first terminal of which is coupled to a reference bias voltage, and a control terminal of which receives a second differential input signal; a first N-type resonant transistor, a first terminal of which is coupled to a second terminal of which is coupled to a reference low voltage, and a control terminal of which receives the first differential input signal; and a second N-type resonant transistor, a first terminal of which is coupled to a second terminal of which is coupled to a second P-type resonant transistor, and a second terminal of which is coupled to a reference low voltage, and a control terminal of which receives the second differential input signal; and a resonant circuit including: A resonant capacitor is coupled between the first terminal of the first N-type resonant transistor and the first terminal of the second N-type resonant transistor; and a resonant inductor is coupled between the first terminal of the first N-type resonant transistor and the first terminal of the second N-type resonant transistor.

17. The signal transmission circuit as claimed in claim 13, wherein the resonator comprises: A resonant circuit includes: a resonant capacitor; a first resonant inductor coupled between a reference bias voltage and a first terminal of the resonant capacitor; and a second resonant inductor coupled between a reference bias voltage and a second terminal of the resonant capacitor; and a resonant buffer including: a first resonant transistor, a first terminal of which is coupled to the first terminal of the resonant capacitor, and a control terminal of which receives a first differential input signal; a second resonant transistor, a first terminal of which is coupled to the second terminal of the resonant capacitor, and a control terminal of which receives a second differential input signal; and a resonant current source coupled to the second terminals of the first and second resonant transistors.

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