Semiconductor memory devices and their control methods

Abstract

This invention provides a preferred semiconductor memory device and its control method. A semiconductor memory device includes: a plurality of semiconductor layers deposited in a stacking direction and extending along a first direction; a plurality of via electrodes arranged along two sides of the plurality of semiconductor layers in a second direction in the first direction; a plurality of charge storage layers disposed between the plurality of semiconductor layers and the plurality of via electrodes; and via wiring connected to the ends of the plurality of semiconductor layers in the first direction. Furthermore, when performing a readout operation, at a first timing, a first voltage is supplied to a via electrode disposed on the via wiring side relative to a first via electrode. At a second timing, a readout voltage greater than the first voltage is supplied to the first via electrode. Additionally, the voltages of a plurality of second via electrodes are maintained at the first voltage, the plurality of second via electrodes being disposed relative to the semiconductor layers on the side opposite to the first via electrode in the second direction, and within a predetermined distance from the first via electrode. Furthermore, a readout through voltage greater than the readout voltage is supplied to a plurality of third via electrodes.

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