Semiconductor devices

Abstract

An embodiment provides a semiconductor device that suppresses parasitic capacitance. The semiconductor device of this embodiment includes a first diffusion layer region and a second diffusion layer region disposed on a semiconductor substrate, separated along the surface direction of the semiconductor substrate. It has a gate insulating film disposed on the semiconductor substrate, at least a portion of which is located between the first and second diffusion layer regions. It has a gate electrode located on the side opposite to the gate insulating film and the semiconductor substrate. It has a first base conductive region disposed along the surface direction of the semiconductor substrate on the side opposite to the first diffusion layer region and the semiconductor substrate, and a first connection conductive region connected to the first base conductive region. It includes a second base conductive region disposed along the surface direction of the semiconductor substrate on the side opposite to the second diffusion layer region and the semiconductor substrate, and a second connection conductive region connected to the second base conductive region. The height of at least one of the first and second base conductive regions is equal to or lower than the height of the gate electrode.

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