Trench power device

Abstract

A trench power device includes a substrate, an epitaxial layer, a trench gate structure, a drain layer, and source regions. The epitaxial layer having a trench is formed on the first surface of the substrate. The trench gate structure is in the trench of the epitaxial layer. The drain layer is on the second surface of the substrate. The source regions are formed in the epitaxial layer on both sides of the trench gate structure. The trench gate structure includes a gate formed in the trench, a gate oxide layer and a bottom dielectric layer. The gate oxide layer is formed on sidewalls of the gate. The bottom dielectric layer is formed between the gate and a bottom surface of the trench. The thickness of the bottom dielectric layer is greater than that of the gate oxide layer, and a top of the bottom dielectric layer includes a convex curved surface.

Description

Technical Field

[0001] This invention relates to a power transistor technology, and more particularly to a trench power device. Prior Technology

[0002] In the field of power devices, reducing on-resistance to increase power density is a key area of ​​development for both industry and academia. Therefore, compared to existing planar transistors, trench power devices with lower on-resistance have become a focus of power device research and development.

[0003] However, power components in trench architecture must withstand high voltage at the bottom and corner areas of the trench. Without proper design and protection, this can lead to leakage or even direct damage to the components. Summary of the Invention

[0004] This invention provides a trench-type power element that can avoid excessively high electric fields at the bottom and corners of the trench, thereby preventing leakage and premature failure of the element.

[0005] A trench power device according to the present invention includes a substrate, an epitaxial layer, a trench gate structure, a drain layer, and a source region. The substrate has a first surface and a second surface opposite to each other. The epitaxial layer is formed on the first surface of the substrate and has a trench. The trench gate structure is formed within the trench of the epitaxial layer. The drain layer is formed on the second surface of the substrate. The source region is formed within the epitaxial layer on both sides of the trench gate structure. The trench gate structure includes a gate, a gate oxide layer, and a bottom dielectric layer. The gate is formed within the trench, and the gate oxide layer is formed between the gate and the sidewall of the trench. The bottom dielectric layer is formed between the gate and the bottom surface of the trench, wherein the thickness of the bottom dielectric layer is greater than the thickness of the gate oxide layer, and the top of the bottom dielectric layer includes a convex curved surface.

[0006] Another trench power device of the present invention includes a substrate, an epitaxial layer, a trench gate structure, a drain layer, and a source region. The substrate has opposing first and second surfaces. The epitaxial layer is formed on the first surface of the substrate and has trenches. The trench gate structure is formed within the trenches of the epitaxial layer. The drain layer is formed on the second surface of the substrate. The source regions are formed within the epitaxial layers on both sides of the trench gate structure. The trench gate structure includes a gate, a gate oxide layer, and a bottom dielectric layer. The gate is formed within the trench, wherein the bottom of the gate has a concave curved surface. The gate oxide layer is formed between the gate and the sidewalls of the trench, and the bottom dielectric layer is formed between the gate and the bottom surface of the trench.

[0007] Based on the above, the trench power element of the present invention has a bottom dielectric layer with a specific structure, which is disposed in the trench gate structure, and can avoid the phenomenon of excessively high electric field at the bottom of the trench and the corner.

[0008] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0009] Figure 1 is a cross-sectional schematic diagram of a trench power element according to an embodiment of the present invention. Figure 2 is a cross-sectional schematic diagram of an example of the gate structure in a trench power element according to an embodiment of the present invention. Figure 3A is a cross-sectional schematic diagram of another example of the gate structure in a trench power element according to an embodiment of the present invention. Figure 3B is a three-dimensional view of the bottom dielectric layer in the gate structure of Figure 3A. Figure 4 is a cross-sectional schematic diagram of yet another example of the gate structure in a trench power element according to an embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of another example of the gate structure in a trench power element according to an embodiment of the present invention. Implementation

[0010] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, for ease of explanation, the dimensions of regions or films shown in the drawings are not to scale.

[0011] Figure 1 is a cross-sectional schematic diagram of a trench power element according to an embodiment of the present invention.

[0012] Referring to Figure 1, the trench power device of this embodiment includes a substrate 100, an epitaxial layer 102, a trench gate structure 104, a drain layer 106, and a source region 108. In some embodiments, the substrate 100 may be a semiconductor substrate, the material of which is, for example, Si, SiC, GaN, or GaAs. In other embodiments, the substrate 100 may be an insulating substrate, such as a glass substrate or a sapphire substrate. The substrate 100 has opposing first surfaces 100a and second surfaces 100b. The epitaxial layer 102 is formed on the first surface 100a of the substrate 100 and has trenches 112. In some embodiments, the epitaxial layer 102 is, for example, a silicon carbide layer. The trench gate structure 104 is formed within the trenches 112 of the epitaxial layer 102, that is, the trench gate structure 104 is located within the space formed by the sidewalls 112s and the bottom surface 112b of the trench 112. The drain layer 106 is formed on the second surface 100b of the substrate 100. Source regions 108 are formed within epitaxial layers 102 on both sides of the trench gate structure 104. In some embodiments, heavily doped regions 110 are also present on both sides of the source regions 108, wherein the conductivity of the heavily doped regions 110 is different from that of the source regions 108, and can be used to stabilize the potential. In this embodiment, the source region 108 is, for example, an N+ region, and the heavily doped region 110 is, for example, a P+ region. The trench gate structure 104 includes a gate 114, a gate oxide layer 116, and a bottom dielectric layer 118. The gate 114 is formed within the trench 112, and the gate oxide layer 116 is formed between the gate 114 and the sidewalls 112s of the trench 112. The bottom dielectric layer 118 is formed between the gate 114 and the bottom surface 112b of the trench 112. In some embodiments, the material of the bottom dielectric layer 118 includes silicon oxide, silicon nitride, or a metal oxide. The top 118t of the bottom dielectric layer 118 includes a convex curved surface CC. That is, the top 118t of the bottom dielectric layer 118 has an upwardly convex geometry, and this convex surface is curved. Therefore, such a structure can significantly reduce the electric field accumulation effect caused by the large voltage at the bottom and corners of the trench 112 due to the large voltage at the drain, thereby improving the voltage withstand capability of the device.

[0013] Please refer to Figure 1. In this embodiment, the thickness t2 of the bottom dielectric layer 118 is greater than the thickness t1 of the gate oxide layer 116. The term "thickness of the bottom dielectric layer" in this text refers to the maximum thickness of the bottom dielectric layer 118, and even without specific indication, the minimum thickness of the bottom dielectric layer 118 will be greater than the thickness t1 of the gate oxide layer 116. Therefore, the bottom dielectric layer 118 can also be called a "thick" dielectric layer, which can prevent excessively high electric fields at the bottom and corners of the trench 112 in trench-type power devices, thus avoiding device leakage and premature failure. Furthermore, the top 118t of the bottom dielectric layer 118 in Figure 1 has a triangular profile, which can significantly reduce the gate void phenomenon caused by insufficient gate material filling gaps during the deposition of the gate 114. The method for forming the bottom dielectric layer 118 includes, but is not limited to, depositing a dielectric material with a faster etching rate (such as oxide) on the sidewalls 112s and bottom surface 112b of the trench 112, then depositing a dielectric material with a slower etching rate (such as oxide) and performing a planarization process, followed by an etching process. Due to the process, the convex curved surface CC of the top 118t is approximately located between the sidewalls 112s. Therefore, if the trench 112 extends vertically into the plane, the convex curved surface CC will also extend within the trench 112. This triangular-profile bottom dielectric layer 118 structure also reduces the gate-to-drain Miller capacitance effect, thereby accelerating the switching speed of the device. On the other hand, from the structure of the gate 114, the gate 114 is also different from the gate with a general rectangular cross-section. The gate 114 in this embodiment has a contour that is complementary to the top 118t of the bottom dielectric layer 118. Therefore, the bottom 114b of the gate 114 has a concave curved surface, and the cross-section of the bottom 114b has a dovetail-shaped contour. In Figure 1, if the epitaxial layer 102 is an N-type epitaxial layer 102, a shallow base region 120 and a thick base region 122 can also be formed on both sides of the trench 112, wherein the shallow base region 120 and the thick base region 122 are P-type doped regions. The thick base region 122 is below the source region 108 and the heavily doped region 110, but is not connected to the trench gate structure 104. The shallow base region 120 surrounds the above doped regions (such as the source region 108 and the heavily doped region 110) and is connected to the trench gate structure 104. However, the present invention is not limited thereto; other doped regions may also be present in the epitaxial layer 102 to prevent leakage current, improve breakdown voltage, etc.

[0014] In some embodiments, the thickness of the epitaxial layer 102 is, for example, 5 μm to 100 μm; the doping concentration of the epitaxial layer 102 is, for example, 1E15 cm⁻³ to 6E16 cm⁻³. In some embodiments, the thickness of the source region 108 is, for example, 0.3 μm to 0.6 μm; the doping concentration of the source region 108 is, for example, 1E19 cm⁻³ to 1E21 cm⁻³. In some embodiments, the thickness of the heavily doped region 110 is, for example, 0.3 μm to 0.6 μm; the doping concentration of the heavily doped region 110 is, for example, 1E19 cm⁻³ to 1E21 cm⁻³. In some embodiments, the thickness of the shallow base region 120 is, for example, 0.7 μm to 1 μm; the doping concentration of the shallow base region 120 is, for example, 5E16 cm⁻³ to 5E17 cm⁻³, and the thickness of the thick base region 122 is, for example, 1 μm to 1.5 μm; the doping concentration of the thick base region 122 is, for example, 5E17 cm⁻³ to 1E19 cm⁻³. In some embodiments, the thickness t2 of the bottom dielectric layer 118 is, for example, 0.2 μm to 0.4 μm. In some embodiments, the thickness t1 of the gate oxide layer 116 is, for example, 0.02 μm to 0.1 μm.

[0015] The above numerical ranges are those used in some embodiments, but the present invention is not limited to the above ranges.

[0016] Figure 2 is a cross-sectional schematic diagram of an example of the gate structure in a trench power element according to an embodiment of the present invention. Referring to Figure 2, the gate structure in the trench power element of the above embodiment can also be changed to a trench gate structure 200, and the rest is the same as or similar to that in Figure 1, so it is not shown for the sake of simplicity. The trench gate structure 200 includes a bottom dielectric layer 202, a gate 204, and a gate oxide layer 116. The relative positions between the gate 204 and the bottom dielectric layer 202 and the gate oxide layer 116 are the same as in the previous embodiment. The difference is that the cross-section of the top 202t of the bottom dielectric layer 202 has a wavy profile, and the top 202t has a convex curved surface CC as shown in Figure 1. Therefore, the trench gate structure 200 in Figure 2 also avoids the phenomenon of excessive electric field at the bottom and corners of the trench 112. The method for forming the bottom dielectric layer 202 includes, but is not limited to, performing the method for forming the bottom dielectric layer 118 of FIG1, then conformally depositing an oxide layer thereon, and then performing an oxide etching process until the bottom dielectric layer 202 has a wavy profile. The gate 204 in FIG2 has a profile complementary to the top 202t of the bottom dielectric layer 202, so the bottom 204b of the gate 204 has a concave curved surface, and the cross-section of the bottom 204b also has a wavy profile.

[0017] Figure 3A is a cross-sectional schematic diagram of another example of the gate structure in a trench power device according to an embodiment of the present invention. Referring to Figure 3A, the gate structure in the trench power device of the above embodiment can also be changed to a trench gate structure 300, and the rest is the same as or similar to that in Figure 1, so it is not shown for the sake of simplicity. The trench gate structure 300 includes a bottom dielectric layer 302, a gate 304, and a gate oxide layer 116. The relative positions between the gate 304 and the bottom dielectric layer 302 and the gate oxide layer 116 are the same as in the above embodiment, the difference being that the top 302t of the bottom dielectric layer 302 is a ridge bar, and the cross-section of the ridge bar has a triangular outline. Since the trench 112 is actually a long strip extending vertically into the drawing, the perspective view of the bottom dielectric layer 302 formed therein is shown in Figure 3B.

[0018] In Figure 3B, the top 302t of the bottom dielectric layer 302 has a convex curved surface CC, similar to that in Figure 1. Therefore, the trench gate structure 300 in Figure 3A also has the effect of avoiding excessively high electric fields at the bottom and corners of the trench 112, and can significantly reduce gate voids and the Miller capacitance effect between the gate and the drain. The bottom dielectric layer 302 in Figure 3A also includes a necked portion 306 located between the ridge and the bottom surface 112b of the trench 112. The method of forming the bottom dielectric layer 302 is, for example, but not limited to, performing the method of forming the bottom dielectric layer 118 in Figure 1 first, and then continuing to etch the oxide to obtain the top 302t, such as the ridge. The gate 304 in Figure 3A has a profile complementary to the top 302t of the bottom dielectric layer 302. Therefore, the bottom 304b of the gate 304 has a concave curved surface, and the cross-section of the bottom 204b has an arrow-shaped profile.

[0019] Figure 4 is a cross-sectional schematic diagram of another example of the gate structure in a trench power element according to an embodiment of the present invention. Referring to Figure 4, the gate structure in the trench power element of the above embodiment can also be changed to a trench gate structure 400, and the rest is the same as or similar to that in Figure 1, so it is not shown for the sake of simplicity. The trench gate structure 400 includes a bottom dielectric layer 402, a gate 404, and a gate oxide layer 116. The relative positions between the gate 404, the bottom dielectric layer 402, and the gate oxide layer 116 are the same as in the above embodiment, the difference being that the cross-section of the top 402t of the bottom dielectric layer 402 is a semi-circular outline. And the top 402t has a convex curved surface CC as in Figure 1, so the trench gate structure 400 of Figure 2 also has the effect of avoiding the phenomenon of excessive electric field at the bottom and corners of the trench 112, and can reduce the phenomenon of gate voids. In some embodiments, the bottom dielectric layer 402 may have a hole 406. The method for forming the bottom dielectric layer 402 includes, but is not limited to, performing the method for forming the bottom dielectric layer 118 of FIG1 first, followed by high-temperature annealing, during which voids 406 are generated in the bottom dielectric layer 402. The gate 404 in FIG4 has a profile complementary to the top 402t of the bottom dielectric layer 402, so the bottom 404b of the gate 404 has a concave curved surface, and the cross-section of the bottom 404b is also a semi-circular profile.

[0020] Figure 5 is a cross-sectional schematic diagram of another example of the gate structure in a trench power element according to an embodiment of the present invention. Referring to Figure 5, the gate structure in the trench power element of the above embodiment can also be changed to a trench gate structure 500, while the rest is the same as or similar to that in Figure 1, so it is not shown for simplicity. The trench gate structure 500 includes a gate oxide layer 116, a bottom dielectric layer 118, a split gate 502, a split gate 504, and an isolation layer 506. The difference between the trench gate structure 500 and the trench gate structure 104 in Figure 1 is that the gate is changed to a split gate 502 and a split gate 504. The split gate 502 and the split gate 504 can reduce Miller capacitance, thereby increasing the device switching speed. The method for forming the split gate 502 and split gate 504 includes, but is not limited to, forming the gate oxide layer 116 and the bottom dielectric layer 118, and then conformally depositing the gate material on top of the bottom dielectric layer 118. That is, the shape of the gate inside the trench 112 will also be triangular. The gate material can be heavily doped polycrystalline silicon or a metallic conductive material. After depositing the gate material, anisotropic etching is performed to form the split gate structure, and then an isolation layer 506 is formed between the split gates on both sides of the trench 112. The split gate 502 and split gate 504 in Figure 5 can also be used in the structures in Figures 2, 3A and 4, so they will not be described in detail here.

[0021] The trench power element of the present invention can withstand high voltage at the bottom and corners of the trench, and is therefore suitable as a key component of electric vehicles or for use in other high-power devices.

[0022] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0023] 100:Substrate 100a: First surface 100b: Second surface 102: Epitaxial layer 104, 200, 300, 400, 500: Trench gate structure 106: Drain Layer 108: Source Region 110: Heavily doped region 112: Trench 112s: Sidewall 112b: Bottom surface 114, 204, 304, 404: Gate 114b, 204b, 304b, 404b: Bottom 116: Gate oxide layer 118, 202, 302, 402: Bottom dielectric layer 118t, 202t, 302t, 402t: Top 120: Shallow-base polar region 122: Thick-based polar region 124: Dielectric layer 126: Source Contact Window 306: Neck retraction 406: Empty hole 502, 504: Separate gate 506: Isolation Layer CC: Convex surface t1, t2: thickness

Claims

1. A trench-type power device, comprising: A substrate having a first surface and a second surface opposite to each other; An epitaxial layer is formed on the first surface of the substrate and has trenches; A trench gate structure is formed in the trench of the epitaxial layer; a drain layer is formed on the second surface of the substrate; The trench gate structure includes a source region formed within the epitaxial layer on both sides of the trench gate structure. The trench gate structure comprises: a gate formed within the trench; a gate oxide layer formed between the gate and the sidewall of the trench; and a bottom dielectric layer formed between the gate and the bottom surface of the trench, wherein the thickness of the bottom dielectric layer is greater than the thickness of the gate oxide layer, and the top of the bottom dielectric layer includes a convex curved surface, wherein the top of the bottom dielectric layer is a ridge bar, and the cross-section of the ridge bar has a triangular profile.

2. The trench power element as claimed in claim 1, wherein the bottom dielectric layer further includes a necking portion located between the ridge and the bottom surface of the trench.

3. The trench power device as claimed in claim 1, wherein the material of the bottom dielectric layer includes silicon oxide, silicon nitride, or metal oxide.

4. The trench power device as claimed in claim 1, wherein the substrate material includes Si, SiC, GaN, or GaAs.

5. The trench power device as claimed in claim 1, wherein the substrate comprises a glass substrate or a sapphire substrate.

6. A trench-type power element, comprising: A substrate having a first surface and a second surface opposite to each other; An epitaxial layer is formed on the first surface of the substrate and has trenches; A trench gate structure is formed in the trench of the epitaxial layer; a drain layer is formed on the second surface of the substrate; The trench gate structure includes a source region formed within the epitaxial layer on both sides of the trench gate structure. The trench gate structure comprises: a gate formed within the trench, wherein the bottom of the gate has a concave curved surface, and the cross-section of the bottom of the gate has a dovetail or arrowhead profile; and a gate oxide layer formed between the gate and the sidewall of the trench. And a bottom dielectric layer is formed between the gate and the bottom surface of the trench.

7. The trench power element as claimed in claim 6, wherein the gate is a single gate or a split gate.

8. The trench power element as claimed in claim 7, wherein an isolation layer is provided between the discrete gates.

9. The trench power device as claimed in claim 6, wherein the material of the bottom dielectric layer includes silicon oxide, silicon nitride, or metal oxide.

10. The trench power device as claimed in claim 6, wherein the substrate material includes Si, SiC, GaN, or GaAs.

11. The trench power device as claimed in claim 6, wherein the substrate material includes a glass substrate or a sapphire substrate.

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