Integrated circuit device and method of manufacturing the same

Abstract

In some embodiments, the present disclosure relates to an IC device including an array of cells. A semiconductor channel overlays the back gate, isolated from a back gate by a first dielectric layer. A lower portion of a top gate overlays and is in contact with the back gate. The top gate is isolated from the semiconductor channel by a first sidewall spacer; an upper portion overlays the semiconductor channel, isolated by a second dielectric layer, and isolated laterally from adjoining structures by a second sidewall spacer. A cascading portion connects the upper portion and the lower portion and overlays the first sidewall spacer. A first electrode is on a first side of the upper portion and in contact with the semiconductor channel. A second electrode is on the opposite side of the upper portion and in contact with the semiconductor channel.

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