Methods for forming source / drain regions of cfets

Abstract

A method includes forming a multilayer stack comprising a first semiconductor nanostructure and a second semiconductor nanostructure over the first semiconductor nanostructure, forming a dummy gate stack over the multilayer stack, etching the multilayer stack to form a source / drain recess, forming a sacrificial region at a bottom of the source / drain recess, and performing a selective deposition process to form a dielectric liner. The dielectric liner is selectively deposited on a sidewall of the multilayer stack, and a top surface of the sacrificial region is exposed to the source / drain recess. The method further includes removing the sacrificial region, forming a lower source / drain region in the source / drain recess and electrically connected to the first semiconductor nanostructure, removing the dielectric liner to reveal the second semiconductor nanostructure, and forming an upper source / drain region to electrically connect to the second semiconductor nanostructure.

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