Semiconductor device manufacturing methods and plasma processing methods
TW202638776APending Publication Date: 2026-09-16HITACHI HIGH TECH CORP
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Patent Information
- Application Number
- TW115104804
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-10
- Filing Date
- 2026-02-06
- Publication Date
- 2026-09-16
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Abstract
This disclosure aims to provide a technique that, during the etching of spacers in the formation process of transistor gate sidewall spacers, utilizes a first protective film and a second protective film to protect the upper part and sidewall of the dummy gate, respectively. The technique includes the following process: a first process, in which a first protective film is formed to cover a semiconductor layer that is formed linearly and forms a channel, and a spacer layer is formed to cover the dummy gate, which is formed linearly orthogonally to the semiconductor layer; a second process, after the first process, in which a second protective film, different from the first protective film, is formed to cover the first protective film; a third process, after the second process, in which the second protective film formed on the sidewall of the dummy gate, and the second protective film formed on the sidewall and above the semiconductor layer, are removed by selective isotropic etching relative to the second protective film formed on the above the dummy gate; and a fourth process, after the third process, in which the first protective film formed on the sidewall of the semiconductor layer is removed by anisotropic etching.
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