Fully self-aligned contact between backside power and interconnect using replacement metal contact integration

TW202638780APending Publication Date: 2026-09-16TOKYO ELECTRON LTD
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Patent Information

Application Number
TW114122706
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-26
Filing Date
2025-06-17
Publication Date
2026-09-16

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Abstract

Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a source-and-drain (S / D) contact and a metal backside contact via vertically aligned with the S / D contact. For example, the method can include providing a substrate, with an oxide layer formed on the substrate, forming over the oxide layer a fin structure that includes a stack of alternating semiconductor layers and dielectric layers, etching a portion of the oxide layer beneath the fin structure to form a backside contact via opening, forming at least one S / D contact to cover the semiconductor layers of the fin structure, and metalizing the backside contact via opening to form a metal backside contact via.
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