Integrated circuit device and method of manufacturing the same

Abstract

In some embodiments, the present disclosure relates to an IC device including an array of cells, each including a stacked field-effect transistor (FET) that includes a gate stack, a channel layer, source and drain terminals, and dielectric layers. The gate stack includes top and bottom gate boards and a gate pillar conductively connecting them. The channel layer includes a first channel band disposed between the bottom gate board and the top gate board and connecting the source terminal to the drain terminal. The source terminal is located on a first side of the gate stack and the drain terminal is located on a second side of the gate stack.A bottom-gate dielectric layer separates the bottom gate board from the channel layer and a top-gate dielectric layer separates the top gate board from the channel layer. The gate stack is configured to control the conductivity of the first channel band.

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