Semiconductor device and method of forming the same

Abstract

A semiconductor device includes: a semiconductor on insulator (SOI) substrate; and a vertical active element disposed in a first region. The semiconductor on insulator substrate includes: a base plate, and an insulating layer disposed on a frontside of the base plate. The vertical active element includes: a pair of source regions disposed in the semiconductor on insulator substrate; a pair of gate electrodes disposed at opposite sides of the pair of source regions, respectively; and a drain electrode disposed on a backside of the base plate. A portion of the drain electrode is disposed through the base plate and the insulating layer. The semiconductor device further includes: a horizontal active element disposed in a second region; and an isolation structure separating the vertical active element from the horizontal active element.

Description

Semiconductor devices and methods for forming the same This disclosure relates to semiconductor devices and methods of forming them, and in particular to the design of integrating vertical active elements and horizontal active elements. The integrated circuit (IC) industry has experienced rapid growth. Technological evolution in IC materials and design has resulted in various generations of ICs, each with smaller and more complex circuitry than the previous generation. In this evolution, functional density (e.g., the number of interconnects per die area) has generally increased, while geometry (e.g., the smallest components (or traces) that can be created using a process) has shrunk. This shrinking of size generally benefits production efficiency and reduces associated costs. However, this shrinkage also introduces new challenges. However, these advancements have increased the complexity of manufacturing integrated circuits. As component sizes continue to shrink, manufacturing processes become increasingly difficult to execute. Therefore, forming reliable semiconductor devices in smaller sizes remains a significant challenge. A semiconductor device includes: a semiconductor-on-insulator (SOI) substrate; and a vertical active element disposed in a first region. The SOI substrate includes: a substrate; and an insulating layer disposed on the front side of the substrate. The vertical active element includes: a pair of source regions disposed in the SOI substrate; a pair of gate electrodes disposed on opposite sides of the source regions; and a drain electrode disposed on the back side of the substrate. A portion of the drain electrode extends through the substrate and the insulating layer. The semiconductor device further includes: a horizontal active element disposed in a second region; and an isolation structure separating the vertical active element from the horizontal active element. A method of forming a semiconductor device includes: providing a semiconductor substrate on an insulating layer; and forming a vertical active element in a first region. The semiconductor substrate on the insulating layer includes: providing a substrate and forming an insulating layer on the front side of the substrate. Forming the vertical active element includes: forming a pair of source regions in the semiconductor substrate on the insulating layer; forming a pair of gate electrodes on opposite sides of the source regions; and depositing a drain electrode on the back side of the substrate. The method of forming the semiconductor device further includes: etching the semiconductor substrate on the insulating layer to form an opening through the substrate and the insulating layer from the back side of the substrate, wherein a portion of the drain electrode extends into the opening; forming a horizontal active element in a second region; and forming an isolation structure to separate the vertical active element from the horizontal active element. The following disclosure provides numerous different embodiments or examples for implementing various components of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the description mentioning that a first component is formed on top of a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed. Furthermore, in some embodiments disclosed herein, terms such as “connection” and “interconnection” may, unless specifically defined, refer to two structures being in direct contact, or to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, spatially related terms such as "below," "below," "lower than," "above," "above," and similar terms may be used here to describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations shown in the figure. When the device is rotated to other orientations (rotated 90° or other orientations), the spatial relative descriptions used here may also be interpreted according to the orientation after rotation. The terms "about," "approximately," and "roughly" as used herein generally mean within ±20%, preferably ±10%, and even more preferably within ±5%, ±3%, ±2%, ±1%, or 0.5% of a given value. The values ​​given herein are approximate; that is, unless specifically stated otherwise, the given values ​​may imply the meaning of "about," "approximately," or "roughly." The following describes some embodiments of this disclosure in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Additional components may be added to the semiconductor device. Some of the components described may be replaced or omitted in different embodiments. Although some embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure. In existing technologies, the doping concentration and structural profile of each semiconductor region of a horizontally active device (such as a laterally diffused metal-oxide semiconductor, LDMOS) are typically adjusted during the manufacturing process to generate a sufficiently high breakdown voltage and a sufficiently low on-state resistance, thereby further optimizing overall performance. However, in the design of more complex horizontally active devices (such as integrated bipolar complementary metal-oxide semiconductor-double diffused metal-oxide semiconductor, BCD) transistors, achieving effective isolation becomes extremely difficult. In addition, existing vertical active devices may include metal-oxide-semiconductor field-effect transistors (MOSFETs), such as split-gate transistors (SGTs) to maintain breakdown voltage and reduce on-resistance. The configuration of the "split-gate" structure can drive the electric field from the front side of the substrate to the drain end on the back side of the substrate, thereby increasing the breakdown voltage and reducing the on-resistance. It should be understood that the channels of horizontal active elements extend in the horizontal direction, while the channels of vertical active elements extend in the vertical direction. Therefore, existing technologies require the horizontal and vertical active elements to be formed in different fabrication processes to be placed on the same wafer. Furthermore, achieving effective isolation within horizontal active elements is already difficult; integrating horizontal and vertical active elements makes isolation even more challenging. The inventors have discovered that complete isolation can be achieved by combining a semiconductor on insulator (SOI) substrate with a deep trench isolation (DTI) structure. Moreover, to accommodate the use of SOI substrates, back-side processes (including grinding, etching, deposition, or other similar methods) can be used to design the drain electrode formed on the back side of the substrate of the SOI substrate to extend through the substrate and the insulating layer, thus forming an innovative drain electrode. Figures 1-9 are schematic cross-sectional views illustrating intermediate stages of forming a semiconductor device 10 according to some embodiments of this disclosure. In this embodiment, only a portion of the horizontal active elements and a portion of the vertical active elements are shown in the semiconductor device 10. In some embodiments, the semiconductor device may include any number of active and passive components. Active components include metal-oxide-semiconductor (MOS) transistors, complementary metal-oxide-semiconductor (CMOS) transistors, laterally diffused MOS transistors, bicarrier-complementary MOS-double-diffused MOS transistors, planar transistors, fin field-effect transistors (FINFETs), gate-all-around field-effect transistors (GAAFETs), split-gate transistors, other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, pads, or other similar structures. For simplicity, Figure 9 only shows illustrative bicarrier-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistors and split-gate transistors. Referring to Figure 1, the semiconductor device 10 can be divided into a first region 10A and a second region 10B. The initial structure of the semiconductor device 10 may include a semiconductor-on-insulator substrate 100 and a buried layer 200. In some embodiments, the semiconductor-on-insulator substrate 100 may include a substrate 120, an insulating layer 140, an epitaxial layer 160, and an epitaxial layer 180. In other embodiments, the semiconductor-on-insulator substrate 100 may only include a substrate 120, an insulating layer 140, and an epitaxial layer 160, while the epitaxial layer 180 is an additional semiconductor film layer. In some embodiments, the substrate 120 of the semiconductor substrate 100 on the insulating layer may be, for example, a wafer or a die, but the embodiments disclosed herein are not limited thereto. In some embodiments, the substrate 120 may be a semiconductor substrate, such as a silicon (Si) substrate. Furthermore, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, and gallium indium arsenide (GaInAs) alloy. GaInAs alloys, gallium indium phosphide (GaInP) alloys, and / or gallium indium arsenide phosphide (GaInAsP) alloys, or combinations thereof. Furthermore, the substrate 120 may be of a first conductivity type or a second conductivity type different from the first conductivity type. In the embodiments described below, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be individually doped with suitable dopants (or impurities). P-type dopants may include boron (B), indium (In), aluminum (Al), or gallium (Ga), while N-type dopants may include phosphorus (P) or arsenic (As). In a particular embodiment of this disclosure, the substrate 120 may be of the second conductivity type (N-type) with a doping concentration between 3 × 10⁻⁶. 19 cm -3 and 8×10 19 cm -3 between. Referring again to Figure 1, an insulating layer 140 may be disposed on a substrate 120. In some embodiments, the insulating layer 140 may encapsulate the substrate 120 and may extend continuously across the first region 10A and the second region 10B. According to some embodiments of this disclosure, the insulating layer 140 may provide insulation between the overlying structure and the underlying substrate 120. The insulating layer 140 may be a buried oxide (BOX). The thickness of the insulating layer 140 may be between 0.5 μm and 5 μm. Referring to Figure 1, an epitaxial layer 160 may be disposed on the insulating layer 140. In some embodiments, the epitaxial layer 160 may have a second conductivity type (N-type), and its doping concentration may be between 6 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3 In a specific embodiment of this disclosure, the substrate 120 may have the same conductivity type as the epitaxial layer 160, but the doping concentration of the substrate 120 is greater than that of the epitaxial layer 160. The material of the epitaxial layer 160 may include silicon, silicon germanium, silicon carbide, other similar materials, or combinations thereof. The thickness of the epitaxial layer 160 may be between 1 μm and 7 μm. The epitaxial layer 160 may be formed by an epitaxial process, which may include metal-organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), hydride vapor phase epitaxy (HVPE), selective epitaxial growth (SEG), molecular beam epitaxy (MBE), other suitable methods, or combinations thereof. Referring again to Figure 1, an epitaxial layer 180 can be disposed on the epitaxial layer 160. In some embodiments, the epitaxial layer 180 may have a second conductivity type (N-type), and its doping concentration may be between 6 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3 In a specific embodiment disclosed herein, the substrate 120, epitaxial layer 160, and epitaxial layer 180 may all have the same conductivity type, but the doping concentration of epitaxial layer 160 is greater than that of epitaxial layer 180. Epitaxial layer 160 may be located between insulating layer 140 and epitaxial layer 180. The thickness of epitaxial layer 180 may be between 1 μm and 7 μm. The material and formation method of epitaxial layer 180 may be similar to those of epitaxial layer 160, and the details will not be repeated here. It should be understood that, since the subsequently formed discrete device is of the second conductivity type (N-type), the substrate 120, epitaxial layer 160, and epitaxial layer 180 must all be of the second conductivity type (N-type) to facilitate current conduction in the vertical channel. If epitaxial layers 160 and 180 are both configured of the first conductivity type (P-type), additional second conductivity type (N-type) well regions can be formed around the discrete device (e.g., a split-gate transistor), allowing the discrete device to maintain normal operation. Furthermore, epitaxial layer 160 can be configured to have a relatively high doping concentration to reduce the overall on-resistance of the discrete device, and epitaxial layer 180 can be configured to have a relatively low doping concentration to maintain the overall breakdown voltage of the discrete device. Referring to Figure 1, the semiconductor device 10 may include a buried layer 200 located in the first region 10A and disposed within the epitaxial layer 160 and the epitaxial layer 180. In some embodiments, the buried layer 200 may have a second conductivity type (N-type). According to some embodiments of this disclosure, the buried layer 200 may reduce the overall on-resistance of discrete components. The configuration of the buried layer 200 is optional. In other words, when a semiconductor-on-insulator substrate 100 is used, the buried layer 200 may be omitted. Alternatively, if the backside bias significantly affects the breakdown voltage of the horizontal active components in the second region 10B, the buried layer 200 may be provided in the second region 10B to reduce the backside effect. The vertical dimension of the buried layer 200 may be between 0.5 μm and 2 μm. The lateral dimension of the buried layer 200 may extend across the first region 10A. The method for forming the buried layer 200 may include ion-implanting an N-type dopant (e.g., phosphorus or arsenic) within the epitaxial layer 160 before forming the epitaxial layer 180, performing heat treatment to drive the implanted ions into the epitaxial layer 160, and then forming the epitaxial layer 180 on the epitaxial layer 160. In some embodiments, since the epitaxial layer 180 is formed under high-temperature conditions, the implanted ions diffuse into the epitaxial layer 180. As shown in Figure 1, the buried layer 200 is located near the interface between the epitaxial layers 160 and 180, and has a portion within the epitaxial layer 160 and another portion within the epitaxial layer 180. In other words, the buried layer 200 may extend upward from the interface between the epitaxial layers 160 and 180. In some embodiments, the doping concentration of the buried layer 200 may be between 5 × 10⁻⁶. 17 cm -3 and 1×10 20 cm -3 According to some embodiments disclosed herein, the doping concentration of the substrate 120 may be greater than the doping concentration of the buried layer 200, the doping concentration of the buried layer 200 may be greater than the doping concentration of the epitaxial layer 160, and the doping concentration of the epitaxial layer 160 may be greater than the doping concentration of the epitaxial layer 180. Configuring a relatively high doping concentration epitaxial layer 160 below the buried layer 200 and a relatively low doping concentration epitaxial layer 180 above the buried layer 200 is an ideal design for further reducing on-resistance. Referring to Figure 2, a vertical active element, which may be a discrete element, can be disposed in the first region 10A of the semiconductor substrate 100 on the insulating layer. Although the semiconductor device 10 illustrates a split-gate transistor as an example of a discrete element, the embodiments disclosed herein are not limited thereto. For example, the discrete element may include a switching trench-type metal-oxide-semiconductor transistor or a vertically diffused metal-oxide-semiconductor transistor. In conventional split-gate transistors, the source and gate terminals may be configured on the front side of the substrate, while the drain terminal may be configured on the back side of the substrate. Thus, a channel in the vertical direction can be formed extending from the front side of the substrate to the back side of the substrate. It is worth noting that a semiconductor-on-insulator (SBI) substrate 100 is used to integrate the horizontal and vertical active components and achieve complete isolation. If the drain terminal of the split-gate transistor is still disposed on the back side of the substrate 120 of the SBI substrate 100, the insulating layer 140 will block the original channel path, making the drain terminal unable to conduct. According to some embodiments of this disclosure, the drain terminal of the split-gate transistor can be disposed through the substrate 120 and the insulating layer 140 to avoid the insulating layer 140 affecting the operation of the split-gate transistor. The split-gate transistor in the first region 10A still has a channel in the vertical direction. However, the current in the channel will conduct through the portion where the drain terminal is disposed through the substrate 120 and the insulating layer 140, thereby achieving effective operation of the split-gate transistor. First, a well region 420 may be formed within the epitaxial layer 180. The well region 420 extends vertically from the top surface of the epitaxial layer 180 into the epitaxial layer 180. In some embodiments, the well region 420 may include a subsequently formed heavily doped region 422, a source region 424-1, and a source region 424-2. According to some embodiments disclosed herein, the well region 420 may be of a first conductivity type (P-type), and its doping concentration may be between 1 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3 The thickness of well region 420 can be between 0.3 μm and 1.5 μm. Well region 420 can be formed by, for example, ion implantation and / or diffusion processes. Referring again to Figure 2, a heavily doped region 422, a source region 424-1, and a source region 424-2 can be disposed within the well region 420, extending downward from the top surface of the well region 420. According to some embodiments disclosed herein, the heavily doped region 422 can be of a first conductivity type (P-type), while the source regions 424-1 and 424-2 can be of a second conductivity type (N-type). The heavily doped region 422, source region 424-1, and source region 424-2 can be laterally adjacent to each other, and the heavily doped region 422 can be laterally sandwiched between source regions 424-1 and 424-2. The formation method of the heavily doped region 422, source region 424-1, and source region 424-2 can be similar to the formation method of the well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of the heavily doped region 422 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The heavily doped region 422 can be coupled simultaneously with source region 424-1 or source region 424-2 to the subsequently formed source contact 980S. The thickness of the heavily doped region 422 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, since well region 420 and heavily doped region 422 have the same conductivity type, the heavily doped region 422 can serve as the source end body connecting source region 424-1 and source region 424-2, and plays a key role in the electrical grounding of the source end. In some embodiments, the doping concentrations of source region 424-1 and source region 424-2 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The thicknesses of source regions 424-1 and 424-2 can be between 0.1 μm and 0.5 μm. According to some embodiments disclosed herein, source regions 424-1 and 424-2 can serve as the source terminals of a split-gate transistor. Referring to Figure 2, dielectric layers 520-1 and 520-2, electrode 680-1, and electrode 680-2 can be disposed in epitaxial layer 180. Dielectric layer 520-1 may include a first portion 520-1A and a second portion 520-1B. Dielectric layer 520-2 may include a first portion 520-2A and a second portion 520-2B. Electrode 680-1 may include a first structure 680-1A and a second structure 680-1B. Electrode 680-2 may include a first structure 680-2A and a second structure 680-2B. In some embodiments, the second portion 520-1B and the second structure 680-1B may constitute a gate structure laterally located on one side of well region 420 adjacent to source region 424-1, while the second portion 520-2B and the second structure 680-2B may constitute another gate structure laterally located on the other side of well region 420 adjacent to source region 424-2. Furthermore, the first part 520-1A and the first structure 680-1A can constitute a split gate structure below the gate structure (including the second part 520-1B and the second structure 680-1B), while the first part 520-2A and the first structure 680-2A can constitute another split gate structure below the gate structure (including the second part 520-2B and the second structure 680-2B). In some embodiments, the gate structure (including the second part 520-1B and the second structure 680-1B) and the gate structure (including the second part 520-2B and the second structure 680-2B) can be coupled to the subsequently formed gate contact 980G, respectively. The first structure 680-1A and the second structure 680-1B of the electrode 680-1 can be isolated from each other, and the first structure 680-2A and the second structure 680-2B of the electrode 680-2 can be isolated from each other. According to some embodiments of this disclosure, the gate structure (including the second part 520-1B and the second structure 680-1B), the gate structure (including the second part 520-2B and the second structure 680-2B), the split gate structure (including the first part 520-1A and the first structure 680-1A), and the split gate structure (including the first part 520-2A and the first structure 680-2A) can be connected to the same potential (not shown) as the source terminal of the split gate transistor. The materials of dielectric layers 520-1 and 520-2 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or multiple layers thereof. In other embodiments, dielectric layers 520-1 and 520-2 may include materials with a high dielectric constant, having a dielectric constant (or k-value) greater than about 7.0. Materials with high dielectric constants may include metal oxides, and may also include silicates of hafnium (Hf), aluminum, zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), other similar materials, or combinations thereof. Metal oxides may include hafnium oxide (HfO). 2) Hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), and lanthanum oxide (La). 2O 3) Aluminum oxide (Al) 2O 3) Aluminum silicon oxide (AlSiO) and zirconium oxide (ZrO) 2) Titanium oxide (TiO) and tantalum oxide (TaO) 2O 5) Yttrium oxide (Y 2O 3) or other similar materials. The thickness of the second portion 520-1B of dielectric layer 520-1 and the second portion 520-2B of dielectric layer 520-2 can be between 250 Å and 1500 Å. The thickness of the first portion 520-1A of dielectric layer 520-1 and the first portion 520-2A of dielectric layer 520-2 can be between 1000 Å and 6000 Å. According to some embodiments disclosed herein, the thickness of the first portion 520-1A and the first portion 520-2A is greater than the thickness of the second portion 520-1B and the second portion 520-2B. It should be understood that if the thickness of the second portion 520-1B and the second portion 520-2B is too large, an excessively high critical voltage may be generated. If the thickness of the first portion 520-1A and the first portion 520-2A is too small, the insulating function may be compromised. Dielectric layers 520-1 and 520-2 can be formed by chemical vapor deposition (CVD), molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), other similar methods, or combinations thereof. The materials of electrodes 680-1 and 680-2 may include amorphous silicon, polycrystalline silicon, poly-SiGe, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicates (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, or metals. Metals may include cobalt (Co), ruthenium (Ru), aluminum, palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium, tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium, other similar materials, combinations thereof, or multiple layers thereof. In some embodiments, the first part 520-1A and the first part 520-2A may be respectively disposed on opposite sides and the bottom of the first structure 680-1A and the first structure 680-2A, while the second part 520-1B and the second part 520-2B may be respectively disposed on opposite sides and the bottom of the second structure 680-1B and the second structure 680-2B. Furthermore, the portion of the second part 520-1B located at the bottom of the second structure 680-1B may be positioned between the first structure 680-1A and the second structure 680-1B, and the portion of the second part 520-2B located at the bottom of the second structure 680-2B may be positioned between the first structure 680-2A and the second structure 680-2B. In other words, the first structure 680-1A and the second structure 680-1B of electrode 680-1 can be "split" by a portion of dielectric layer 520-1, and the first structure 680-2A and the second structure 680-2B of electrode 680-2 can be "split" by a portion of dielectric layer 520-2, thereby exhibiting the "split gate" feature of this disclosed embodiment. The first structures 680-1A and 680-2A may have lateral dimensions between 0.18 μm and 2 μm, and vertical dimensions between 0.8 μm and 10 μm. The second structures 680-1B and 680-2B may have lateral dimensions between 0.18 μm and 2 μm, and vertical dimensions between 0.3 μm and 2 μm. According to some embodiments of this disclosure, the lateral dimensions of the second structures 680-1B and 680-2B may be larger than those of the first structures 680-1A and 680-2A. The vertical dimensions of the first structures 680-1A and 680-2A may be larger than those of the second structures 680-1B and 680-2B. Electrodes 680-1 and 680-2 can be formed by physical vapor deposition (PVD), atomic layer deposition, plating, sputtering, evaporating, other suitable processes, or combinations thereof. In some embodiments, a first opening (not shown) extending into the epitaxial layer 180 may first be formed on opposite sides of the well region 420. After the first opening is formed, a second opening may be formed from the bottom surface of the first opening. The second opening also extends into the epitaxial layer 180 and is perpendicularly spaced from the underlying buried layer 200. The lateral dimension of the first opening is substantially equal to the lateral dimension of the second opening, while the vertical dimension of the second opening is greater than the vertical dimension of the first opening. The subsequently formed dielectric layers 520-1, 520-2, electrode 680-1, and electrode 680-2 may adopt the contours of the first and second openings. The first and second openings may be patterned by a photolithography process followed by an etching process. The photolithography process may include photoresist coating, soft baking, exposure, post-exposure baking, development, other similar techniques, or combinations thereof. The etching process may include dry etching, wet etching, other similar methods, or combinations thereof. Wet etching processes can be isotropic and can be performed using wet etchants such as sulfuric acid (H2O). 2SO 4) Hydrochloric acid (HCl), hydrogen bromide (HBr), and ammonia (NH4+). 3) Diluted hydrofluoric acid (dHF), hydrofluoric acid (HF), potassium hydroxide (KOH), and nitric acid (HNO₃). 3) Acetic acid (CH 3COOH), succinic acid (C 4H 6O 4) Citric acid (C 6H 8O 7) Other similar chemicals or combinations thereof, but the embodiments disclosed herein are not limited thereto. Dry etching processes may include anisotropic plasma etching, such as reactive ion etching (RIE), inductively coupled plasma (ICP), capacitively coupled plasma (CCP), other similar methods, or combinations thereof, but the embodiments disclosed herein are not limited thereto. Dry etching processes can be performed in an environment of a selected process gas; exemplary process gases may include nitrogen (N). 2) Ammonia, Oxygen 2) Nitrous oxide (N) 2O), argon (Ar), helium (He), hydrogen (H) 2) Carbon tetrafluoromethane (CF) 4), sulfur hexafluoride (SF) 6) Difluoromethane (CH 2F 2), trifluoromethane (CHF) 3) Hexafluoroethane (C 2F 6) Chlorine (Cl) 2) Chloroform (trichloromethane, CHCl3) 3) Carbon tetrachloride (CCl) 4) Boron trichloride (BCl) 3) Hydrogen bromide, bromoform (CHBr) 3) or other similar gases, but the embodiments disclosed herein are not limited thereto. In some embodiments, any of the suitable deposition processes described above can be used to form a first portion 520-1A of dielectric layer 520-1 and a first portion 520-2A of dielectric layer 520-2 in the second opening, respectively. Then, any of the suitable deposition processes described above can be used to form a first structure 680-1A of electrode 680-1 and a first structure 680-2A of electrode 680-2 in the remaining portion of the second opening, respectively. Specifically, dielectric material and electrode material can be sequentially filled into the second opening after an etching process is performed to form the second opening and before the photolithography pattern is removed. After filling the second opening, a planarization process (such as chemical mechanical polishing (CMP) or etch-back) can be performed to remove the photolithography pattern and excess dielectric and electrode material. The remaining dielectric and electrode materials become the first part 520-1A of dielectric layer 520-1 and the first part 520-2A of dielectric layer 520-2, as well as the first structure 680-1A of electrode 680-1 and the first structure 680-2A of electrode 680-2, respectively. In some embodiments, a second portion 520-1B of dielectric layer 520-1 and a second portion 520-2B of dielectric layer 520-2 can be formed in the first opening using any of the suitable deposition processes described above. Then, a second structure 680-1B of electrode 680-1 and a second structure 680-2B of electrode 680-2 can be formed in the remaining portion of the first opening using any of the suitable deposition processes described above. Specifically, the same dielectric material can be compliantly formed on the sidewalls of the first opening, on the top surfaces of the first portion 520-1A and the first structure 680-1A, and on the top surfaces of the first portion 520-2A and the first structure 680-2A. Afterward, the first opening can be completely filled with the same electrode material. The same planarization process can be performed to remove excess dielectric and electrode material outside the first opening. After the planarization process, the top surfaces of the epitaxial layer 180, the dielectric material, and the electrode material are flush with each other. The remaining dielectric and electrode materials become the second part 520-1B of dielectric layer 520-1 and the second part 520-2B of dielectric layer 520-2, as well as the second structure 680-1B of electrode 680-1 and the second structure 680-2B of electrode 680-2. Referring to Figure 3, a horizontal active element may be disposed in the second region 10B of the semiconductor substrate 100 on the insulating layer, which may include a first transistor 10B-1, a second transistor 10B-2, and a third transistor 10B-3. The first transistor 10B-1 may be a metal-oxide-semiconductor transistor having a second conductivity type (N-type). The second transistor 10B-2 may be a metal-oxide-semiconductor transistor having a first conductivity type (P-type). The third transistor 10B-3 may be a laterally diffused metal-oxide-semiconductor transistor having a second conductivity type (N-type). In some embodiments, the first transistor 10B-1 may be adjacent to the second transistor 10B-2, while the second transistor 10B-2 may be spaced apart from the third transistor 10B-3. Unlike the vertical active element in the first region 10A, the first transistor 10B-1, the second transistor 10B-2, and the third transistor 10B-3 may have channels in the horizontal direction. According to a specific embodiment of this disclosure, the first transistor 10B-1, the second transistor 10B-2, and the third transistor 10B-3 may constitute a horizontal active element (e.g., a bicarrier-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistor). First, a well region 320 for a first transistor 10B-1, a well region 340 for a second transistor 10B-2, and a high-voltage well region 360 for a third transistor 10B-3 can be formed within the epitaxial layer 180. Well regions 320, 340, and 360 can extend vertically from the top surface of the epitaxial layer 180 into the epitaxial layer 180. According to some embodiments disclosed herein, well region 320 can be of a first conductivity type (P-type), while well region 340 and high-voltage well region 360 can be of a second conductivity type (N-type). Well regions 320 and 340 can be laterally adjacent to each other, while well region 340 and high-voltage well region 360 can be laterally separated from each other. The method of forming well regions 320, 340, and 360 can be similar to the method of forming well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of well region 320 may be between 1 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3 The thickness of well region 320 can be between 0.3 μm and 1.5 μm. Well region 320 may include subsequently formed host region 322, source region 324, and drain region 326. Furthermore, a gate structure 620 may be subsequently formed on the surface of well region 320 of epitaxial layer 180. Gate structure 620 may be laterally located between source region 324 and drain region 326. In some embodiments, the doping concentration of well region 340 may be between 1 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3 The thickness of well region 340 can be between 0.3 μm and 1.5 μm. Well region 340 may include subsequently formed host region 342, source region 344, and drain region 346. Furthermore, a gate structure 640 may be subsequently formed on the surface of well region 340 of epitaxial layer 180. Gate structure 640 may be laterally located between source region 344 and drain region 346. In some embodiments, the doping concentration of the high-pressure well region 360 may be between 1 × 10⁻⁶. 15 cm -3 and 2×10 17 cm -3The thickness of the high-pressure well region 360 can be between 0.3 μm and 1.5 μm. The high-pressure well region 360 may include subsequently formed well region 440, drain region 446-1, drain region 446-2, isolation structure 560-1, and isolation structure 560-2. Well region 440 may further include heavily doped region 442, source region 444-1, and source region 444-2. Furthermore, gate structure 660-1 and gate structure 660-2 may be subsequently formed on the surface of the high-pressure well region 360 of the epitaxial layer 180. Gate structure 660-1 may be laterally located between source region 444-1 and drain region 446-1, while gate structure 660-2 may be laterally located between source region 444-2 and drain region 446-2. The isolation structure 560-1 can laterally isolate the drain region 446-1 from the gate structure 660-1, while the isolation structure 560-2 can laterally isolate the drain region 446-2 from the gate structure 660-2. Referring again to Figure 3, a main body region 322, a source region 324, and a drain region 326 can be disposed within the well region 320, extending downward from the top surface of the well region 320. According to some embodiments disclosed herein, the main body region 322 can be of a first conductivity type (P-type), while the source region 324 and drain region 326 can be of a second conductivity type (N-type). The main body region 322, source region 324, and drain region 326 can be laterally separated. The method of forming the main body region 322, source region 324, and drain region 326 can be similar to the method of forming the well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of the main region 322 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 Between. The main body region 322 can be coupled to the subsequently formed main body contact 920B. The thickness of the main body region 322 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, since the well region 320 and the main body region 322 have the same conductivity type, the main body region 322 can serve as the main end of the first transistor 10B-1. In some embodiments, the doping concentration of the source region 324 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3The source region 324 can be coupled to the subsequently formed source contact 920S. The thickness of the source region 324 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, the source region 324 can serve as the source terminal of the first transistor 10B-1. In some embodiments, the doping concentration of the drain region 326 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The drain region 326 can be coupled to the subsequently formed drain contact 920D. The thickness of the drain region 326 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, the drain region 326 can serve as the drain end of the first transistor 10B-1. Referring to Figure 3, a main body region 342, a source region 344, and a drain region 346 can be disposed within the well region 340, extending downward from the top surface of the well region 340. According to some embodiments disclosed herein, the main body region 342 can be of a second conductivity type (N-type), while the source region 344 and drain region 346 can be of a first conductivity type (P-type). The main body region 342, source region 344, and drain region 346 can be laterally separated. The method of forming the main body region 342, source region 344, and drain region 346 can be similar to the method of forming the well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of the main region 342 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 Between. The main body region 342 can be coupled to the subsequently formed main body contact 940B. The thickness of the main body region 342 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, since the well region 340 and the main body region 342 have the same conductivity type, the main body region 342 can serve as the main end of the second transistor 10B-2. In some embodiments, the doping concentration of the source region 344 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3The source region 344 can be coupled to the subsequently formed source contact 940S. The thickness of the source region 344 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, the source region 344 can serve as the source terminal of the second transistor 10B-2. In some embodiments, the doping concentration of the drain region 346 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The drain region 346 can be coupled to the subsequently formed drain contact 940D. The thickness of the drain region 346 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, the drain region 346 can serve as the drain end of the second transistor 10B-2. Referring again to Figure 3, a well region 440, a drain region 446-1, a drain region 446-2, an isolation structure 560-1, and an isolation structure 560-2 can be provided within the high-pressure well region 360, extending downwards from the top surface of the high-pressure well region 360. According to some embodiments disclosed herein, the well region 440 can be of a first conductivity type (P-type), while the drain regions 446-1 and 446-2 can be of a second conductivity type (N-type). The well region 440, drain region 446-1, and drain region 446-2 can be laterally separated. The isolation structures 560-1 and 560-2 can be adjacent to the drain regions 446-1 and 446-2, respectively. The method of forming the well region 440, drain region 446-1, and drain region 446-2 can be similar to the method of forming the well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of well region 440 may be between 1 × 10⁻⁶. 15 cm -3 and 2×10 18 cm -3 The thickness of well region 440 can be between 0.3 μm and 1.5 μm. Well region 440 may include subsequently formed heavily doped region 442, source region 444-1, and source region 444-2. Furthermore, gate structure 660-1 and gate structure 660-2 may partially contact well region 440. In some embodiments, the doping concentrations of drain regions 446-1 and 446-2 may be between 1 × 10⁻⁶. 18 cm -3and 1×10 22 cm -3 Between. Drain regions 446-1 and 446-2 can be coupled to subsequently formed drain contact 960D, respectively. The thickness of drain regions 446-1 and 446-2 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, drain regions 446-1 and 446-2 can serve as drain terminals of the third transistor 10B-3. In some embodiments, isolation structures 560-1 and 560-2 may be shallow trench isolation (STI) structures or local oxidation of silicon (LOCOS) structures. As previously mentioned, isolation structure 560-1 laterally isolates drain region 446-1 from gate structure 660-1, while isolation structure 560-2 laterally isolates drain region 446-2 from gate structure 660-2. According to some embodiments of this disclosure, isolation structures 560-1 and 560-2 can avoid high electric fields caused by junction collapse. The depths of isolation structures 560-1 and 560-2 may be between 0.2 μm and 0.6 μm. It is worth noting that the depth of isolation structures 560-1 and 560-2 should be greater than the thickness of drain regions 446-1 and 446-2 in order to effectively block the high electric field from drain regions 446-1 and 446-2. In some embodiments, the formation of isolation structures 560-1 and 560-2 may include, for example, forming an insulating layer on an insulating-on-insulator substrate 100, selectively etching the insulating layer and the insulating-on-insulator substrate 100 to form trenches extending from the top surface of the insulating-on-insulator substrate 100 to a location within the insulating-on-insulator substrate 100, wherein the trenches are located between adjacent active regions. Next, a nitrogen-rich substrate (such as silicon oxynitride or other similar materials) may be grown along the trenches, and then an insulating material (such as silicon dioxide, SiO2) may be deposited using a deposition process. 2) Silicon nitride, silicon oxynitride, or other similar materials are filled into the trench. Then, the insulating material in the trench is annealed, and the semiconductor substrate 100 on the insulating layer is planarized (such as chemical mechanical polishing or similar methods) to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the semiconductor substrate 100 on the insulating layer. Referring to Figure 3, a heavily doped region 442, a source region 444-1, and a source region 444-2 can be disposed within the well region 440, extending downward from the top surface of the well region 440. According to some embodiments disclosed herein, the heavily doped region 442 can be of a first conductivity type (P-type), while the source regions 444-1 and 444-2 can be of a second conductivity type (N-type). The heavily doped region 442, source region 444-1, and source region 444-2 can be laterally adjacent to each other, and the heavily doped region 442 can be laterally sandwiched between source regions 444-1 and 444-2. The formation method of the heavily doped region 442, source region 444-1, and source region 444-2 can be similar to the formation method of the well region 420, and its details will not be repeated here. In some embodiments, the doping concentration of the heavily doped region 442 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The heavily doped region 442 can be coupled simultaneously with source region 444-1 or source region 444-2 to the subsequently formed source contact 960S. The thickness of the heavily doped region 442 can be between 0.1 μm and 0.5 μm. According to some embodiments of this disclosure, since well region 440 and heavily doped region 442 have the same conductivity type, the heavily doped region 442 can serve as the source end body connecting source region 444-1 and source region 444-2, and plays a key role in the electrical grounding of the source end. In some embodiments, the doping concentrations of source region 444-1 and source region 444-2 may be between 1 × 10⁻⁶. 18 cm -3 and 1×10 22 cm -3 The thicknesses of source regions 444-1 and 444-2 can be between 0.1 μm and 0.5 μm. According to some embodiments disclosed herein, source regions 444-1 and 444-2 can serve as source terminals of the third transistor 10B-3. Referring again to Figure 3, gate structures 620 for a first transistor 10B-1, 640 for a second transistor 10B-2, and 660-1 and 660-2 for a third transistor 10B-3 can be formed on the epitaxial layer 180. The portion of the well region 320 contacted by gate structure 620 can be considered as the channel region of the first transistor 10B-1, and gate structure 620 can serve as the gate terminal of the first transistor 10B-1. Gate structure 620 can be coupled to the subsequently formed gate contact 920G. The portion of the well region 340 contacted by gate structure 640 can be considered as the channel region of the second transistor 10B-2, and gate structure 640 can serve as the gate terminal of the second transistor 10B-2. Gate structure 640 can be coupled to the subsequently formed gate contact 940G. Gate structures 660-1 and 660-2 can extend horizontally from the high-pressure well region 360 to the well region 440. The portion of the high-pressure well region 360 or the portion of the well region 440 contacted by gate structures 660-1 and 660-2 can be considered as the channel region of the third transistor 10B-3, and gate structures 660-1 and 660-2 can serve as the gate terminals of the third transistor 10B-3. Gate structures 660-1 and 660-2 can be coupled to the subsequently formed gate contact 960G. In the third transistor 10B-3, the source region 444-1, drain region 446-1, and gate structure 660-1 can form a transistor of a second conductivity type (N-type) (hereinafter referred to as the first transistor), while the source region 444-2, drain region 446-2, and gate structure 660-2 can form another transistor of a second conductivity type (N-type) (hereinafter referred to as the second transistor). According to some embodiments of this disclosure, the first transistor and the second transistor in the third transistor 10B-3 can be connected in series. Therefore, the third transistor 10B-3 can exhibit an array-type structure, such as a laterally "double" diffused metal-oxide-semiconductor transistor. The thickness of gate structures 620, 640, 660-1, and 660-2 may be between 20 Å and 1000 Å. In some embodiments, each of gate structures 620, 640, 660-1, and 660-2 may include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. The material and formation method of the gate dielectric layer may be similar to those of dielectric layers 520-1 and 520-2, and the details will not be repeated here. The material and formation method of the gate electrode may be similar to those of electrode 680-1 and electrode 680-2, and the details will not be repeated here. Referring to Figure 4, an isolation structure 580 may be provided in the semiconductor substrate 100 on the insulating layer. In some embodiments, the isolation structure 580 may be a deep trench isolation structure. The isolation structure 580 may extend through the epitaxial layers 180 and 160 and reach the insulating layer 140. According to some embodiments of this disclosure, the isolation structure 580 may laterally surround and define an active region and electrically isolate active region components within or above the semiconductor substrate 100 on the insulating layer. The materials and formation methods of the isolation structure 580 may be similar to those of the isolation structures 560-1 and 560-2, and the details will not be repeated here. It should be noted that the isolation structure 580 may extend into the insulating layer 140, but not through it. Typical bicarrier-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistors utilize junction designs to achieve isolation. However, such isolation is not complete. According to some embodiments disclosed herein, complete isolation can be achieved by combining the isolation structure 580 with the semiconductor-on-insulator substrate 100 (e.g., insulating layer 140). From another perspective, the isolation structure 580 and the semiconductor-on-insulator substrate 100 (e.g., insulating layer 140) can be considered together as a "container" for individual active components, isolating adjacent active components to suppress potential leakage currents and unwanted interference. The isolation structure 580 can laterally surround the vertical active element (e.g., a split-gate transistor) in the first region 10A and the horizontal active element (e.g., a bi-carrier complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistor) in the second region 10B to achieve complete isolation between the horizontal and vertical active elements, as shown in Figure 4. Furthermore, the isolation structure 580 can further isolate the first transistor 10B-1 and the second transistor 10B-2 from the third transistor 10B-3. In other words, the isolation structure 580 completely isolates the "bi-carrier complementary metal-oxide-semiconductor" portion from the "double-diffused metal-oxide-semiconductor" portion of the horizontal active element. Referring again to Figure 4, an interlayer dielectric (ILD) layer 800 can be disposed on the semiconductor substrate 100 above the insulating layer. In some embodiments, the ILD layer 800 may cover gate structure 620, gate structure 640, gate structure 660-1, and gate structure 660-2. Besides providing mechanical protection and insulation for underlying components, the ILD layer 800 can also isolate conductive materials at different levels. The material of the ILD layer 800 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon oxynitrocarbide (SiO2). x N y C 1-x-y (where x and y are in the range of 0 to 1), tetraethyl ortho silicate (TEOS), undoped silica glass, doped silica (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials. The thickness of the interlayer dielectric layer 800 can be between 5000 Å and 20000 Å. The interlayer dielectric layer 800 can be formed by spin-on coating, chemical vapor deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or combinations thereof. Subsequently, a planarization process (such as chemical mechanical polishing) can be performed on the interlayer dielectric layer 800 to give it a flat top surface. Referring to Figure 4, the following components can be configured: main contact 920B, source contact 920S, drain contact 920D, gate contact 920G, main contact 940B, source contact 940S, drain contact 940D, gate contact 940G, source contact 960S, drain contact 960D, gate contact 960G, source contact 980S, and gate contact 980G, all passing through the interlayer dielectric layer 800. In the first transistor 10B-1, the main contact 920B, source contact 920S, drain contact 920D, and gate contact 920G can respectively physically contact the main region 322, source region 324, drain region 326, and gate structure 620. In the second transistor 10B-2, the main contact 940B, source contact 940S, drain contact 940D, and gate contact 940G can physically contact the main region 342, source region 344, drain region 346, and gate structure 640, respectively. In the third transistor 10B-3, the source contact 960S, drain contact 960D, and gate contact 960G can physically contact the heavily doped region 442 and source regions 444-1 / 444-2, drain regions 446-1 and 446-2, and gate structures 660-1 and 660-2, respectively. In the split gate transistor of the first region 10A, the source contact 980S and the gate contact 980G can physically contact the heavily doped region 422 and the source region 424-1 / 424-2, as well as the electrodes 680-1 and 680-2, respectively. The main contact 920B, source contact 920S, drain contact 920D, gate contact 920G, main contact 940B, source contact 940S, drain contact 940D, gate contact 940G, source contact 960S, drain contact 960D, gate contact 960G, source contact 980S, and gate contact 980G can be formed simultaneously and therefore include the same material, which can be similar to the material of electrodes 680-1 and 680-2, the details of which will not be repeated here. First, a plurality of openings can be formed in the interlayer dielectric layer 800, corresponding to the host region 322, source region 324, drain region 326, gate structure 620, host region 342, source region 344, drain region 346, gate structure 640, heavily doped region 442 and source region 444-1 / 444-2, drain region 446-1 and 446-2, gate structure 660-1 and 660-2, heavily doped region 422 and source region 424-1 / 424-2, and electrode 680-1 and 680-2. Next, the aforementioned material can be deposited on the interlayer dielectric layer 800 through a suitable deposition process. The aforementioned materials can be filled into all the openings to form body contact 920B, source contact 920S, drain contact 920D, gate contact 920G, body contact 940B, source contact 940S, drain contact 940D, gate contact 940G, source contact 960S, drain contact 960D, gate contact 960G, source contact 980S, and gate contact 980G. In some embodiments, although this embodiment refers only to the processes of body contact 920B, source contact 920S, drain contact 920D, gate contact 920G, body contact 940B, source contact 940S, drain contact 940D, gate contact 940G, source contact 960S, drain contact 960D, gate contact 960G, source contact 980S, and gate contact 980G, this disclosure is not limited thereto. Any subsequent processes can be performed based on the structure shown in Figure 4, according to industry needs. For example, suitable back-end of line (BEOL) processes can be further performed above the semiconductor device 10, which are not shown for simplicity. Referring to Figure 5, the substrate 120 of the semiconductor substrate 100 over the insulating layer can be thinned. Depending on the application and design requirements, the substrate 120 can be ground to the desired thickness from the back side. For example, the substrate 120 can be thinned to 19 mil or 23 mil. It should be understood that 1 mil is equal to approximately 25.4 μm. According to some embodiments of this disclosure, thinning the substrate 120 facilitates the subsequent formation of openings, allowing the drain terminals of the split-gate transistor to extend through the substrate 120 and the insulating layer 140, thereby achieving efficient operation of the split-gate transistor. The substrate 120 can be thinned by a taiko grinding process, a non-taiko grinding process, or other similar methods. Referring to Figure 6, after thinning the substrate 120, a plurality of vias 100H1 may be formed in the substrate 120. In some embodiments, the plurality of vias 100H1 may be distributed across the first region 10A and may be laterally spaced from each other. According to some embodiments of this disclosure, the plurality of vias 100H1 may extend through the substrate 120 and use the insulating layer 140 as an etch stop layer (ESL). Since the material of the substrate 120 (e.g., silicon) and the material of the insulating layer 140 (e.g., oxide) have different etch rates, two etch processes are used to etch the substrate 120 and the insulating layer 140 separately to achieve a better etch selectivity. Although Figure 6 illustrates three vias 100H1, the embodiments disclosed herein are not limited thereto. For example, any number of vias 100H1 may be configured, depending on application and design requirements. First, a patterned back-side photoresist can be formed on the back-side surface of the substrate 120. Then, the substrate 120 is etched using the aforementioned suitable etching technique to form a plurality of vias 100H1 on the back side of the substrate 120. Referring to Figure 7, the plurality of vias 100H1 can be further extended through the insulating layer 140. In some embodiments, the plurality of vias 100H1 can extend into the epitaxial layer 160, becoming a plurality of vias 100H2. According to some embodiments of this disclosure, the plurality of vias 100H2 can allow the subsequently formed drain electrode 740 to conduct without being affected by the insulating layer 140. The lateral dimension of each via 100H2 can be between 1 μm and 50 μm. The insulating layer 140 can be etched by a second etching process using the suitable etching technique described above. For example, dry oxide etching with a time-mode can be used to control the extent of extension of the plurality of vias 100H2. Referring to Figure 8, a drain region 720 may be formed in the substrate 120 before the drain electrode 740 is fabricated. In some embodiments, the drain region 720 may extend across the first region 10A and the second region 10B, and may be close to the back surface of the substrate 120 and the bottom surface of the plurality of vias 100H2. According to some embodiments of this disclosure, the drain region 720 may reduce the on-resistance of the split-gate transistor in the first region 10A. If a further reduction in the on-resistance of the split-gate transistor in the first region 10A is required, the portion of the drain region 720 near the bottom surface of the plurality of vias 100H2 may be configured to contact the buried layer 200. The drain region 720 may be of a second conductivity type (N-type). The configuration of the drain region 720 is optional. In other words, the drain region 720 may be omitted, and the drain electrode 740 may be formed directly on the back surface of the substrate 120 and in the plurality of vias 100H2. It is worth noting that, generally speaking, the epitaxial concentration in the high-voltage region needs to be lower than that in the low-voltage region. Therefore, if the vertical active element in the first region 10A is for a high-voltage application, then there is no need to configure the buried layer 200 and the drain region 720. In some embodiments, the doping concentration of the drain region 720 may be between 5 × 10⁻⁶. 17 cm -3 and 1×10 20 cm -3 In some embodiments disclosed herein, the doping concentration of the drain region 720 may be greater than that of the substrate 120. Suitable dopants can be implanted into the substrate 120 through a suitable implantation process. Subsequently, the dopants can be driven into the substrate 120 by an annealing process. Suitable annealing processes may include rapid thermal annealing (RTA), spike annealing, soap annealing, laser annealing, furnace annealing, or other similar methods. Since no mask is used, the drain region 720 may be formed near the back surface of the substrate 120 and near the bottom surface of the plurality of vias 100H2. Referring to Figure 9, a drain electrode 740 may be disposed on the back surface of the substrate 120 and in a plurality of vias 100H2. In some embodiments, the drain electrode 740 may extend across the first region 10A and the second region 10B, and compliantly extend into each via 100H2. According to some embodiments of this disclosure, portions of the drain electrode 740 in the plurality of vias 100H2 may serve as effective drain terminals of the split-gate transistor in the first region 10A. The thickness of the drain electrode 740 may be between 0.1 μm and 10 μm. The material and formation method of the drain electrode 740 may be similar to those of electrodes 680-1 and 680-2, and the details will not be repeated here. It should be understood that when the plurality of vias 100H2 have a high aspect ratio, the drain electrode 740 may not be able to extend compliantly into the plurality of vias 100H2. When the plurality of vias 100H2 have relatively narrow openings (e.g., very small linewidths), the plurality of vias 100H2 can be filled with a metallic material (e.g., tungsten). Furthermore, a titanium / titanium nitride liner can be deposited on the sidewalls and bottom surfaces of the plurality of vias 100H2 before filling with the metallic material. The metallic material filling the plurality of vias 100H2 can serve as a conductive block. Subsequently, the drain electrode 740 can be deposited on the back surface of the substrate 120 and on the top surface of the metallic material. It is noteworthy that although the drain electrode 740 also extends into the second region 10B, the drain electrode 740 can be electrically insulated from the horizontal active element of the second region 10B by the insulating layer 140 of the semiconductor substrate 100 on the insulating layer. Therefore, the drain electrode 740 will not cause any unwanted impact on the horizontal active element of the second region 10B. In the split-gate transistor of the first region 10A, the source region 424-1, the drain electrode 740, the dielectric layer 520-1, and the electrode 680-1 can form a first transistor, while the source region 424-2, the drain electrode 740, the dielectric layer 520-2, and the electrode 680-2 can form a second transistor. According to some embodiments of this disclosure, the first and second transistors in the split-gate transistor can be connected in parallel with each other. Therefore, the split-gate transistor can exhibit an array-type metal-oxide-semiconductor field-effect transistor. Figures 10-13 are schematic cross-sectional views illustrating an intermediate stage in the formation of a semiconductor device 20 according to other embodiments of the present disclosure. The semiconductor device 20 can be divided into a first region 20A and a second region 20B. Horizontal active elements in the second region 20B may include a first transistor 20B-1, a second transistor 20B-2, and a third transistor 20B-3. Compared to the semiconductor device 10, the semiconductor device 20 may form relatively large openings in the substrate 120 of the semiconductor substrate 100 on the insulating layer. For simplicity, the features shown in the first region 20A and the second region 20B (including the first transistor 20B-1, the second transistor 20B-2, and the third transistor 20B-3) are similar to those shown in the first region 10A and the second region 10B (including the first transistor 10B-1, the second transistor 10B-2, and the third transistor 10B-3), and their details will not be repeated here. Referring to Figure 10, compared to Figure 6, a single trench 100T1 can be formed in the substrate 120. In some embodiments, the trench 100T1 may overlap with the heavily doped region 422 and source region 424-1 / 424-2, dielectric layer 520-1 and electrode 680-1, and dielectric layer 520-2 and electrode 680-2. According to some embodiments of this disclosure, the trench 100T1 may extend through the substrate 120 and use the insulating layer 140 as an etch stop layer. As previously mentioned, since the material of the substrate 120 (e.g., silicon) and the material of the insulating layer 140 (e.g., oxide) have different etch rates, two etch processes are used to etch the substrate 120 and the insulating layer 140 separately to achieve a better etch selectivity. The method of forming the trench 100T1 may be similar to the method of forming a plurality of vias 100H1, and the details will not be repeated here. Referring to Figure 11, trench 100T1 can be further extended through insulating layer 140. In some embodiments, trench 100T1 can extend into epitaxial layer 160, becoming trench 100T2. According to some embodiments of this disclosure, trench 100T2 can allow subsequently formed drain electrode 740 to conduct without being affected by insulating layer 140. The lateral dimension of trench 100T2 can be between 50 μm and 200 μm. The method of forming trench 100T2 can be similar to the method of forming a plurality of vias 100H2, the details of which will not be repeated here. Referring to Figure 12, a drain region 720 may be provided in the substrate 120. In some embodiments, the drain region 720 may extend across the first region 20A and the second region 20B, and may be close to the back surface of the substrate 120 and the bottom surface of the trench 100T2. According to some embodiments of this disclosure, the drain region 720 may reduce the on-resistance of the split-gate transistor in the first region 20A. If a further reduction in the on-resistance of the split-gate transistor in the first region 20A is required, the portion of the drain region 720 near the bottom surface of the trench 100T2 may be configured to contact the buried layer 200. The drain region 720 may be of a second conductivity type (N-type). As previously mentioned, the configuration of the drain region 720 is optional. In other words, the drain region 720 may be omitted, and the drain electrode 740 may be formed directly on the back surface of the substrate 120 and in the trench 100T2. The characteristics of the 720-pole region are similar to those shown in Figure 8, and the details will not be repeated here. Referring to Figure 13, a drain electrode 740 may be disposed on the back surface of the substrate 120 and in the trench 100T2. In some embodiments, the drain electrode 740 may extend across the first region 20A and the second region 20B and compliantly extend into the trench 100T2. According to some embodiments of this disclosure, the portion of the drain electrode 740 in the trench 100T2 may serve as an effective drain terminal of the split gate transistor of the first region 20A. As previously mentioned, the portion of the drain electrode 740 in the second region 20B may be electrically insulated from the horizontal active element of the second region 20B by the insulating layer 140 of the semiconductor substrate 100 on the insulating layer, so that the drain electrode 740 will not cause any unwanted impact on the horizontal active element of the second region 20B. The features of the drain electrode 740 may be similar to those shown in Figure 9, and the details will not be repeated here. In existing technologies, the channels of horizontal active components extend horizontally, while the channels of vertical active components extend vertically. Therefore, to place horizontal and vertical active components on the same wafer, they must be formed in different fabrication processes. Furthermore, achieving effective isolation within horizontal active components is already difficult; integrating horizontal and vertical active components makes isolation even more challenging. According to some embodiments disclosed herein, complete isolation can be achieved by combining a semiconductor-on-insulator (SBI) substrate with a deep trench isolation structure. The deep trench isolation structure and the SBI substrate can be considered together as a "container" for individual active components, isolating adjacent active components to suppress potential leakage current and unwanted interference. Moreover, to accommodate the use of an SBI substrate, a back-side process can be used to design the drain electrode formed on the back side of the substrate of the SBI substrate to extend through the substrate and the insulating layer, thus forming an innovative drain electrode. This design effectively avoids the situation where the insulating layer of the semiconductor substrate on the insulating layer is electrically insulated from the drain terminals on the back side of the substrate and the source and gate terminals on the front side of the substrate, which could cause device malfunction. Therefore, it can effectively integrate horizontal and vertical active components and achieve complete isolation. The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the disclosed embodiments. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the disclosed embodiments to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. 10: Semiconductor device 10A: First region 10B: Second region 10B-1: First transistor 10B-2: Second transistor 10B-3: Third transistor 20: Semiconductor device 20A: First region 20B: Second region 20B-1: First transistor 20B-2: Second transistor 20B-3: Third transistor 100: Semiconductor substrate on insulating layer 100H1: Through hole 100H2: Through hole 100T1: Trench 100T2: Trench 120: Substrate 140: Insulation Layer 160: Epitaxial Layer 180: Epitaxial Layer 200: Buried Layer 320: Well Region 322: Main Region 324: Source Region 326: Drain Region 340: Well Region 342: Main Region 344: Source Region 346: Drain Region 360: High-Voltage Well Region 420: Well Region 422: Heavily Doped Region 424-1: Source Region 424-2: Source Region 440: Well Region 442: Heavily Doped Region 444-1: Source Region 444-2: Source Region 446-1: Drain Region 446-2: Drain Region 52 0-1: Dielectric layer 520-1A: First part 520-1B: Second part 520-2: Dielectric layer 520-2A: First part 520-2B: Second part 560-1: Isolation structure 560-2: Isolation structure 580: Isolation structure 620: Gate structure 640: Gate structure 660-1: Gate structure 660-2: Gate structure 680-1: Electrode 680-1A: First structure 680-1B: Second structure 680-2: Electrode 680-2A: First Structure 680-2B: Second Structure; 720: Drain Region; 740: Drain Electrode; 800: Interlayer Dielectric Layer; 920B: Body Contact; 920D: Drain Contact; 920G: Gate Contact; 920S: Source Contact; 940B: Body Contact; 940D: Drain Contact; 940G: Gate Contact; 940S: Source Contact; 960D: Drain Contact; 960G: Gate Contact; 960S: Source Contact; 980G: Gate Contact; 980S: Source Contact The various aspects of the embodiments disclosed herein will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments disclosed herein. Figures 1-9 are schematic cross-sectional views illustrating intermediate stages of forming a semiconductor device according to some embodiments of the present disclosure. Figures 10-13 are schematic cross-sectional views illustrating intermediate stages of forming a semiconductor device according to other embodiments of the present disclosure. 10: Semiconductor devices 10A: Zone 1 10B: Second Zone 10B-1: First transistor 10B-2: Second transistor 10B-3: Third transistor 100: Semiconductor substrate on insulating layer 120: Base 140: Insulation layer 160: Epitaxial layer 180: Epitaxial layer 200: Buried layer 320: Well Area 322: Main Area 324: Source Region 326: Drainage Zone 340: Well Area 342: Main Area 344: Source Region 346: Drainage Zone 360: High-pressure well area 420: Well Area 422: Heavily doped region 424-1: Source Region 424-2: Source Region 440: Well Area 442: Heavily doped region 444-1: Source Region 444-2: Source Region 446-1: Drainage Zone 446-2: Drainage Zone 520-1: Dielectric layer 520-1A: Part One 520-1B: Part Two 520-2: Dielectric layer 520-2A: Part 1 520-2B: Part Two 560-1: Isolation Structure 560-2: Isolation Structure 580: Isolation Structure 620: Gate structure 640: Gate structure 660-1: Gate structure 660-2: Gate structure 680-1: Electrode 680-1A: First Structure 680-1B: Second Structure 680-2: Electrode 680-2A: First Structure 680-2B: Second Structure 720: Dublin Zone 740: Drain electrode 800: Interlayer dielectric layer 920B: Main body contact element 920D: Drain Contact 920G: Gate Contact 920S: Source contact 940B: Main body contact element 940D: Drain Contact 940G: Gate Contact 940S: Source contact 960D: Drain Contact 960G: Gate Contact 960S: Source contact 980G: Gate Contact 980S: Source contact

Claims

1. A semiconductor device, comprising: A semiconductor-on-insulator (SOI) substrate includes: a substrate; and an insulating layer disposed on the front side of the substrate; a vertical active element disposed in a first region, including: a pair of source regions disposed in the SOI substrate; a pair of gate electrodes disposed on opposite sides of the pair of source regions; and a drain electrode disposed on the back side of the substrate, wherein a portion of the drain electrode passes through the substrate and the insulating layer; a horizontal active element disposed in a second region; and an isolation structure separating the vertical active element from the horizontal active element. The semiconductor device of claim 1, wherein the vertical active element is a discrete device and the horizontal active element is a bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistor. The semiconductor device of claim 2, wherein the discrete element includes a split-gate transistor (SGT). The semiconductor device of claim 1, wherein the insulating layer extends continuously across the first region and the second region. The semiconductor device of claim 1 further includes a heavily doped region sandwiched between the pair of source regions, wherein the heavily doped region has a first conductivity type and the pair of source regions have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. The semiconductor device of claim 5, wherein the heavily doped region is laterally adjacent to the pair of source regions. The semiconductor device of claim 5, wherein the heavily doped region and the pair of source regions are disposed in a well region, wherein the well region has the first conductivity type. The semiconductor device of claim 5, wherein the semiconductor substrate on the insulating layer further includes a first epitaxial layer disposed on the insulating layer and having the second conductivity type, wherein the pair of source regions and the pair of gate electrodes are located in the first epitaxial layer. The semiconductor device of claim 8, wherein the semiconductor substrate on the insulating layer further includes a second epitaxial layer disposed between the insulating layer and the first epitaxial layer, and has the second conductivity type, wherein the portion of the drain electrode is located in the second epitaxial layer. The semiconductor device of claim 9, wherein the isolation structure is a deep trench isolation (DTI) structure that extends through the first epitaxial layer and the second epitaxial layer and touches the insulating layer. The semiconductor device of claim 1, wherein the pair of gate electrodes further comprises: A first structure having a first dimension; And a second structure on top of the first structure, wherein the second structure has a second dimension that is larger than the first dimension. The semiconductor device of claim 11 further includes a gate dielectric layer, comprising: A first part is disposed on the opposite sides and bottom of the first structure; And a second part, disposed between the first structure and the second structure, and on opposite sides of the second structure. The semiconductor device of claim 5, wherein the horizontal active element further includes: A first transistor having the second conductivity type; A second transistor adjacent to the first transistor and having the first conductivity type, wherein the first transistor and the second transistor are metal-oxide-semiconductor (MOS) transistors; and a third transistor separated from the second transistor by the isolation structure and having the second conductivity type, wherein the third transistor is a lateral-diffused metal-oxide-semiconductor (LDMOS) transistor. A method for forming a semiconductor device includes: A semiconductor-on-insulator substrate is provided, comprising: providing a substrate; and forming an insulating layer on a front side of the substrate; forming a vertical active element in a first region, comprising: forming a pair of source regions in the semiconductor-on-insulator substrate; forming a pair of gate electrodes on both sides of the pair of source regions; and depositing a drain electrode on a back side of the substrate; etching the semiconductor-on-insulator substrate to form an opening through the substrate and the insulating layer from the back side of the substrate, wherein a portion of the drain electrode extends into the opening; forming a horizontal active element in a second region; and forming an isolation structure to separate the vertical active element from the horizontal active element. The method of forming a semiconductor device as described in claim 14, wherein forming the opening includes: A first etching process is performed to extend the opening through the substrate; And a second etching process is performed to extend the opening through the insulating layer. The method of forming a semiconductor device as claimed in claim 15, wherein the opening is a plurality of through holes distributed across the first region and laterally separated from each other. The method of forming a semiconductor device as claimed in claim 15, wherein the opening is a trench that overlaps with the pair of source regions and the pair of gate electrodes. The method of forming a semiconductor device, as claimed in claim 14, further includes thinning the substrate of the semiconductor substrate on the insulating layer before forming the opening. The method for forming a semiconductor device, as claimed in claim 18, further includes performing an ion implantation process on the back surface of the substrate and the opening after thinning the substrate. The method of forming a semiconductor device as claimed in claim 14, wherein providing the semiconductor substrate on the insulating layer further includes: A first epitaxial layer is formed on the insulating layer, wherein the opening extends into the first epitaxial layer; And a second epitaxial layer is formed on the first epitaxial layer, wherein the pair of source regions and the pair of gate electrodes extend into the second epitaxial layer, wherein the isolation structure extends through the first epitaxial layer and the second epitaxial layer and physically contacts the insulating layer.

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