Interposers, semiconductor systems, and methods for producing the same

Abstract

Systems that include large area interposers and method for producing the interposers are provided. The interposers include an interconnection area that includes frontside metal layers, backside metal layers, and through silicon vias connecting the frontside metal layers and the backside metal layers in the interconnection area, a keep-out-zone area that surrounds a perimeter of the interconnection area, and a first seal ring area that surrounds a perimeter of the keep-out-zone area. The first seal ring area includes a first seal ring interconnect structure. The interconnection area is larger than a shot size of a lithography system used for production thereof. The interconnection area is segmented into two or more sub-regions that are each equal to or smaller than the shot size of the lithography system.

Description

[Technical Field]

[0001] This disclosure relates to an interposer, a semiconductor system, and a method of forming the same. [Previous Technology]

[0002] The semiconductor integrated circuit (IC) industry has experienced continuous and rapid growth in recent years. Advances in integrated circuit materials and design technologies have driven continuous improvements in integrated circuits generation after generation. Each generation of circuits is smaller and more complex than its predecessor, resulting in higher functional density (i.e., the number of interconnect components per wafer area) and smaller geometry (i.e., the smallest component or line that can be created using manufacturing processes). This scaling down of processes helps improve production efficiency and reduce associated costs. However, as feature sizes continue to shrink, manufacturing processes become more challenging, making it increasingly difficult to ensure the reliability of semiconductor components. Therefore, the industry faces the ongoing challenge of developing processes capable of producing smaller, more reliable integrated circuits. [Summary of the Invention]

[0003] Some embodiments described herein provide an interposer layer comprising: an interconnect region including one or more front metal layers, one or more back metal layers, and a plurality of silicon vias connecting one or more front metal layers in the interconnect region to one or more back metal layers, wherein the interconnect region is larger than the exposure area of ​​a lithography system for production, wherein the interconnect region is divided into two or more sub-regions, each of the two or more sub-regions being equal to or smaller than the exposure area of ​​the lithography system; an exclusion region, wherein the exclusion region surrounds the perimeter of the interconnect region; and a first sealing ring region including a first sealing ring interconnect structure, wherein the first sealing ring region surrounds the perimeter of the exclusion region.

[0004] Some embodiments described herein provide a semiconductor system comprising: two or more dies, each of the two or more dies having one or more functional components configured to perform a task; and an interposer functionally coupled to each of the two or more dies and configured to transmit a plurality of signals received from each of the two or more dies to another and / or another electronic element in the two or more dies, wherein the interposer comprises: an interconnect region including one or more front metal layers, one or more back metal layers and a plurality of silicon vias connecting one or more front metal layers in the interconnect region to one or more back metal layers, wherein the interconnect region is larger than the exposure area of ​​a lithography system for production; an exclusion region, wherein the exclusion region surrounds the perimeter of the interconnect region; a first sealing ring region including a first sealing ring interconnect structure, wherein the first sealing ring region surrounds the perimeter of the exclusion region; and one or more semiconductor elements functionally coupled to one or more exclusion region interconnect structures and / or the first sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structure and / or the first sealing ring interconnect structure coupled to the one or more semiconductor elements.

[0005] Some embodiments described herein provide a method for forming a semiconductor system, comprising: designating a plurality of portions of an interposer to be produced on a wafer, wherein the portions of the interposer include an interconnect region, an exclusion region, and a first sealing ring region of the interposer, wherein the exclusion region surrounds the interconnect region, and the first sealing ring region surrounds the exclusion region; forming one or more front metal layers, one or more back metal layers, and a plurality of silicon vias connecting the one or more front metal layers to the one or more back metal layers in the interconnect region using a lithography system, wherein the interconnect region is larger than the exposure area of ​​the lithography system, wherein the interconnect region is divided into at least a first sub-region and a second sub-region by first exposing a first sub-region with the lithography system and then exposing a second sub-region with the lithography system, each of the first sub-region and the second sub-region being equal to or smaller than the exposure area of ​​the lithography system, wherein a plurality of adjacent edges between the first sub-region and the second sub-region overlap; and forming a first sealing ring interconnect structure in the first sealing ring region.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another element or feature. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0008] As used herein, terms such as "first," "second," and "third," while describing various elements, components, regions, layers, and / or portions, should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. When terms such as "first," "second," and "third" are used herein, they do not imply a sequence or order unless the context clearly indicates otherwise.

[0009] For ease of description, conventional techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various operations and processes described herein can be incorporated into a more comprehensive process or a process with additional functions not detailed herein. Specifically, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon a full reading of this disclosure that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. Furthermore, it is worth noting that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0010] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another element or feature. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. When spatial relative terms (such as those listed above) are used to describe a first element relative to a second element, the first element may be directly on top of the other element, or there may be an intermediate element or layer. When an element or layer is said to be “above” another element or layer, it is directly on and in contact with the other element or layer.

[0011] It should be noted that the terms "an embodiment," "an exemplary embodiment," "example," and "exemplary" mentioned in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, these terms do not necessarily refer to the same embodiment. In other words, when a specific feature, structure, or characteristic is associated with an embodiment, those skilled in the art can influence that feature, structure, or characteristic in other embodiments, whether or not it is explicitly described.

[0012] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent, however, that the claimed subject matter may be practiced even without these specific details. In other instances, structures and elements are illustrated in block diagram form to facilitate the description of the claimed subject matter.

[0013] In these embodiments, other operations may be provided before, between, and / or after the described stages. Some described stages may be replaced or omitted in different embodiments. Other features may be added to the semiconductor element structure. Some features described below may be replaced or omitted in different embodiments. Although some embodiments perform operations in a specific order, these operations may also be performed in other logical orders.

[0014] The term “layer” as used herein refers to a region, such as an area containing arbitrary boundaries, which does not necessarily have a uniform thickness. For example, a layer can be a region where the thickness varies to some extent.

[0015] An interposer is a dedicated layer or substrate used to connect multiple components or integrated circuits (ICs) within a system. Interposers are typically placed between the IC and the main printed circuit board (PCB) to facilitate interconnection between them. Interposers are particularly useful in advanced packaging technologies such as three-dimensional (3D) ICs or system-in-package (SiP), where multiple ICs or wafers are stacked or placed close together.

[0016] Multiple interposers can be formed on a single wafer. Interposers can be formed through at least one or any combination of processes such as deposition, lithography, etching, chemical mechanical polishing (CMP), implantation, annealing, cleaning, and other known semiconductor processes. Once multiple interposers have been produced, the wafer can be diced to separate each interposer. Typically, each interposer is surrounded by an exclusion region and one or more sealing rings. Furthermore, dicing lines can be provided between the individual interposers. These exclusion regions, sealing rings, and dicing lines are designed to protect the interposers during the dicing process.

[0017] Generally, the size of each interposer is limited by the capabilities of semiconductor process equipment. For example, an interposer can be produced in part using a lithography process that includes forming a mask layer over the layer to be modified. In some embodiments, the mask layer may include multiple layers, such as a pad oxide layer (e.g., silicon oxide) and an overlying pad nitride layer (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, etc.), wherein the nitride layer is a photoresist material. The process may then include patterning the mask layer using a lithography technique that irradiates (exposes) and develops the mask layer to remove a portion thereof, thereby defining a patterned mask. Once the patterned mask is formed, an etching process can be used to etch the exposed portions of the layer to be modified, while the patterned mask protects the underlying material.

[0018] The lithography system used to produce the above-mentioned interposer may have a limited exposure area (e.g., exposure field size or field of view (FoV)) for irradiating (exposing) the mask layer. Existing processes for producing interposers may require an exposure area that covers at least the entire size of the desired interposer. However, with increasing process requirements, it may be necessary to produce interposers of larger sizes.

[0019] This document describes embodiments of semiconductor structures and methods for forming semiconductor structures with large surface areas, for example, exceeding the exposure area of ​​a lithography system used to produce semiconductor structures. For convenience, the semiconductor structures and methods will be described herein with reference to the production of interposers. However, the semiconductor structures and methods are not limited to this application. For example, semiconductor structures and methods may include ICs having mixed bonds therebetween.

[0020] Figure 1 is a cross-sectional view of a portion of an exemplary semiconductor system 100 according to an embodiment. In some examples, the semiconductor system 100 may include a system-in-package (SiP). SiP is an advanced packaging technology that integrates multiple functional components such as a microprocessor, memory, sensors, and power management units into a single package. In this example, the semiconductor system 100 includes a printed circuit board (PCB) 110, a substrate 114, an interposer 118, and a pair of dies 130 and dies 132.

[0021] The die 130 and die 132 (e.g., a chip or integrated circuit (IC)) can be various functional components, such as, but not limited to, processors, memory modules (e.g., DRAM, flash memory), power management ICs, sensors, or application-specific integrated circuits (ASICs). Each die 130 and die 132 can perform a specific task, such as computation, storage, or sensing.

[0022] The bare dies 130 and 132 are electrically connected through an interposer 118. The interposer 118 is a device configured to transmit electrical signals and power between the bare dies 130 and 132. In this example, the interposer 118 includes one or more back-side metal layers 120, an interposer substrate 122, one or more front-side or top-side metal layers 124, and a plurality of through-silicon vias (TSVs) 126 extending through the interposer substrate 122 and connecting the top-side metal layer 124 and the back-side metal layer 120. The top-side metal layer 124 may include a plurality of interconnect structures (not shown) electrically connected to corresponding interconnect structures (not shown) of the bare dies 130 and 132 through, for example, microbumps 128.

[0023] The back-side metal layer 120 can be connected to the substrate 114 via, for example, flip-chip bumps 116. The die 130, die 132, interposer 118, and substrate 114 can define a package or serve as components of a package, which can be connected to the PCB 110 via, for example, package bumps 112. The substrate 114 can also provide mechanical stability. Although not shown, the substrate 114 may include, for example, various metal layers and TSVs configured to electrically connect the interposer 118 and thus the die 130 and die 132 to the PCB 110. Similarly, the PCB 110 may include various metal layers, traces, pads, etc., configured to transmit and receive electrical signals between the die 130, die 132, and other components connected to the PCB 110.

[0024] Referring to Figure 2, an exemplary method 200 for forming an interposer 230 and / or a portion thereof (e.g., interposer 118 of Figure 1) is shown. In step 200A, method 200 includes providing a substrate 210 (e.g., interposer substrate 122 of Figure 1) and forming a trench 212 on its top side (e.g., through an etching process). In step 200B, method 200 includes forming a seed layer or barrier layer 214 on the surface of the trench 212 and on the top surface of the substrate 210. The barrier layer 214 may include, for example, an oxide material and may be formed using various techniques (e.g., certain deposition processes). In step 200C, method 200 includes forming a conductive layer 216 that fills the trench 212 and covers the barrier layer 214. The conductive layer 216 may be, for example, a metallic material (such as copper or an alloy thereof) and may be formed using various techniques (e.g., certain electroplating processes).

[0025] In step 200D, method 200 includes removing excess material from conductive layer 216 to form TSV 218 isolated by barrier layer 214. Various techniques, such as certain chemical mechanical polishing (CMP) processes, can be used to remove excess material. At step 200E, method 200 includes forming one or more front-side metal layers 220 (e.g., top-side metal layer 124 in Figure 1) over the exposed portions of TSV 218 and barrier layer 214. The front-side metal layer 220 may include a dielectric layer in which interconnect structures electrically connected to TSV 218 are formed. The interconnect structures may include multiple metal layers and vias. The interconnect structures can be formed by various materials and processes, including those known in the art. Non-limiting examples of processes forming interconnect structures may include one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes.

[0026] In step 200F, method 200 includes forming a support layer 222 over the front metal layer 220. The support layer 222 is configured to provide mechanical support during subsequent process steps. The support layer 222 can be formed using various techniques, such as certain deposition processes. In step 200G, method 200 includes removing a back-side portion of the substrate 210 to expose a back-side portion of the TSV 218. Various techniques, such as certain planarization processes, can be used to remove the back-side portion of the substrate 210.

[0027] In step 200H, method 200 includes forming one or more backside metal layers 224 (e.g., backside metal layer 120 of Figure 1) over the exposed backside portion of the TSV 218. The backside metal layer 224 may include a dielectric layer in which interconnect structures electrically connected to the TSV 218 are formed. The interconnect structures may include multiple metal layers and vias. The interconnect structures may be formed by various materials and processes, including those known in the art. Non-limiting examples of processes forming the interconnect structures may include one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes.

[0028] In step 200I, method 200 includes forming solder bumps 226 (e.g., flip-chip bumps 116 in Figure 1) on the back side of the back-side metal layer 224 in contact with its interconnect structure. In step 200J, method 200 includes removing the support layer 222 from the front-side metal layer 220 to produce an interposer layer 230. Various techniques (e.g., certain stripping processes) may be used to remove the support layer 222.

[0029] Figures 3 and 4 show a perspective view and a top view, respectively, of a large-area interposer 310 that can be produced, for example, by method 200. In some examples, the large-area interposer 310 may serve as an interposer 118 of a semiconductor system 100. The large-area interposer 310 may be formed on a wafer 302. The large-area interposer 310 includes interconnect regions 312, which are regions containing functional components of the large-area interposer 310, such as a front metal layer, a back metal layer, and a TSV. For example, the interconnect regions 312 may be formed using method 200 of Figure 2. The interconnect regions 312 are surrounded by exclusion regions 314, which in turn are surrounded by sealing ring regions 316.

[0030] Exclusion region 314 is an area within the large-area interposer 310 that does not contain any critical components (e.g., vias, traces, or solder bumps). Exclusion region 314 may be configured to reduce the likelihood of interference with other components of the large-area interposer 310, protect sensitive areas, promote proper mechanical and electrical integrity of the large-area interposer 310, maintain necessary cooling space, and / or allow alignment and bonding with other components during assembly. In some embodiments, exclusion region 314 may include one or more dummy fill structures (e.g., non-functional interconnect structures).

[0031] The sealing ring region 316 is a region that includes an interconnect structure referred to as a sealing ring, which is configured to act as a physical barrier along the periphery of the large-area interposer 310. The sealing ring interconnect structure may include various material layers for protecting the large-area interposer 310 from, for example, contamination and mechanical stress during manufacturing processes, such as when wafer 302 is cut in a wafer dicing process to remove the large-area interposer 310.

[0032] Unlike some existing methods for producing interposers, the large-area interposer 310 can cover a large portion of the wafer 302, exceeding the exposure area of ​​the lithography system used to produce the large-area interposer 310. In the example of Figure 4, the area of ​​the interconnect region 312 of the large-area interposer 310 is almost four times the exposure area of ​​the exemplary lithography system used to produce the interconnect region 312. For example, the maximum exposure area (exposure field size) of some existing lithography systems is approximately 22 mm x 22 mm or 26 mm x 33 mm. In some examples, the area of ​​the large-area interposer 310 can be greater than approximately 22 mm x 22 mm, for example equal to or greater than approximately 40 mm x 22 mm, for example equal to or greater than approximately 40 mm x 40 mm.

[0033] To overcome the limitations of the lithography system, the interconnecting region 312 can be formed by a combination of four sub-regions 318, 320, 322, and 324, each sub-region being formed by a single exposure from the lithography system. To ensure complete coverage during production, the four sub-regions 318, 320, 322, and 324 can overlap at their edges. For example, the first sub-region 318 and the second sub-region 320 can overlap with the third sub-region 322 and the fourth sub-region 324 to define a first double exposure region 326, and the first sub-region 318 and the third sub-region 322 can overlap with the second sub-region 320 and the fourth sub-region 324 to define a second double exposure region 328. Therefore, each of the four sub-regions 318, 320, 322, and 324 can have a surface area up to that of the exposure area of ​​the lithography system. Thus, the total surface area of ​​the interconnecting regions 312 can be up to four times the exposure area of ​​the lithography system minus the areas of the first double exposure region 326 and the second double exposure region 328. It is worth noting that the interconnecting regions 312 can include more or fewer overlapping sub-regions 318, 320, 322, and 324 (e.g., 2, 6, 8, 9, 10, etc.), and their dimensions can vary based on factors such as the required size of the exposure area and / or double exposure area of ​​the specific lithography system used (or other production-constrained system). The large-area interposer layer 310 includes only one exclusion region 314 and one sealing ring region 316. Each region surrounds all overlapping sub-regions 318, 320, 322, and 324. In other words, the large-area interposer layer 310 does not include separate exclusion and sealing ring regions, which surround each overlapping sub-region 318, 320, 322, and 324 and are separated by cut lines. In this manner, a large-area interposer layer 310 with a large interconnect area can be manufactured without being limited by certain manufacturing systems.

[0034] Figures 5 through 21 illustrate various non-limiting aspects of large-area interposers (e.g., interposer 118 in Figure 1, interposer 230 in Figure 2, and / or large-area interposer 310 in Figures 3 and 4) according to various paradigms. It should be noted that these paradigms are for illustrative purposes only, and large-area interposers formed according to the methods disclosed herein may have other configurations, including various combinations of the components shown in Figures 5 through 21. For convenience, consistent reference numerals are used in Figures 5 through 21 to identify identical or functionally related / equivalent elements, but numerical prefixes (1, 2, or 3, etc.) are added to distinguish a particular paradigm from other paradigms in the figures. Given the similarity between paradigms, the following discussion of Figures 5 through 21 will focus primarily on aspects in which the paradigm differs from other paradigms in some significant or important respects. Other aspects of the paradigms not discussed in detail may be substantially as described with respect to one or more other paradigms (including those in Figures 1 through 4) in terms of structure, function, materials, etc. It should be understood that the various areas and components of the large-area intermediary layer are shown for the convenience of the following description and are not drawn to scale.

[0035] Figures 5 and 6 represent a top view and a cross-sectional view along line AA, respectively, showing various aspects of the interposer layer 410 including interconnect regions 412. Interposer regions 412 have sub-regions 418, 420, 422, and 424 overlapping with double-exposure regions 426 and 428, an exclusion region 414, and a sealing ring region 416. Interposer regions 412 may include various components (e.g., lines, vias, etc.), not shown for clarity. At this stage of the manufacturing process, interposer layer 410 includes a mask layer for lithography. The mask layer includes a pad oxide layer 440 (e.g., silicon oxide) and an overlying pad nitride layer 442 (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, etc.), wherein the nitride layer is a photoresist material.

[0036] One or more exclusion region interconnect structures 430 may be formed in the exclusion region 414, and one or more sealing ring interconnect structures 432 may be formed in the sealing ring region 416, each interconnect structure being configured to serve as a protective barrier around the interconnect region 412. The exclusion region interconnect structure 430 and the sealing ring interconnect structure 432 may include multiple metal layers and vias. The exclusion region interconnect structure 430 and the sealing ring interconnect structure 432 may be formed from various materials and processes, including those known in the art. Non-limiting examples of processes for forming the exclusion region interconnect structure 430 and the sealing ring interconnect structure 432 may include one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes. In this example, the large area interposer 310 includes two exclusion region interconnect structures 430 and one sealing ring interconnect structure 432.

[0037] In some examples, one or more exclusion region interconnect structures 430 and / or sealing ring interconnect structures 432 may be electrically coupled to one or more semiconductor elements formed in wafer 402, such as certain transistors (e.g., CMOS, BJT, FET, etc.). The semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structures and / or the sealing ring interconnect structures coupled thereto. In the example of Figure 6, the sealing ring interconnect structure 432 is coupled to one or more complementary metal-oxide-semiconductor (CMOS) elements having an n-well 438 having a p-type diffusion region 436. The CMOS elements are formed in substrate 402. A polysilicon layer 441 may be formed between the CMOS elements and the upper layer of the interposer 410.

[0038] Figures 7 and 8 show a top view and a cross-sectional view along line BB, respectively, illustrating the orientation of the interposer layer 510 including interconnect regions 512. Interposer region 512 has sub-regions 518, 520, 522, and 524 overlapping with double-exposure regions 526 and 528, an exclusion region 514, and a first sealing ring region 516. Exclusion region 514 includes an exclusion region interconnect structure 530, and the first sealing ring region 516 includes a first sealing ring interconnect structure 532. At this stage of the manufacturing process, interposer layer 510 includes a mask layer having a pad oxide layer 540 and an overlying pad nitride layer 542. In this example, the exclusion region interconnect structure 530 and the sealing ring interconnect structure 532 are each electrically coupled to one or more silicon-germanium (SiGe) transistors 544 formed in substrate 502. A polycrystalline silicon layer 541 can be formed between the SiGe transistor 544 and the upper layer of the interposer 510.

[0039] Figures 9 and 10 show a top view and a cross-sectional view along line CC, respectively, illustrating the orientation of the interposer 610 containing interconnect regions 612. Interconnect regions 612 have sub-regions 618, 620, 622, and 624 overlapping with double-exposure regions 626 and 628, an exclusion region 614, and a first sealing ring region 616. Exclusion region 614 includes an exclusion region interconnect structure 630, and the first sealing ring region 616 includes a first sealing ring interconnect structure 632. At this stage of the manufacturing process, the interposer 610 includes a mask layer having a pad oxide layer 640 and an overlying pad nitride layer 642. In this example, each exclusion region interconnect structure 630 is electrically coupled to one or more silicon-germanium (SiGe) transistors 644 formed in the substrate 602, while the sealing ring interconnect structure 632 is not connected to a semiconductor element. A polycrystalline silicon layer 641 can be formed between the SiGe transistor 644 and the upper layer of the interposer 610.

[0040] Figures 11 and 12 show a top view and a cross-sectional view along line DD, respectively, illustrating the orientation of the interposer 710 containing interconnect regions 712. Interconnect regions 712 have sub-regions 718, 720, 722, and 724 overlapping with double-exposure regions 726 and 728, an exclusion region 714, and a first sealing ring region 716. Exclusion region 714 includes an exclusion region interconnect structure 730, and the first sealing ring region 716 includes a first sealing ring interconnect structure 732. At this stage of the manufacturing process, the interposer 710 includes a mask layer having a pad oxide layer 740 and an overlying pad nitride layer 742. In this example, the exclusion region interconnect structure 730 and the sealing ring interconnect structure 732 are electrically coupled to one or more CMOS elements having a p-well 746, wherein the p-well 746 has an n-type diffusion region 748. The CMOS elements are formed in a substrate 702. A polysilicon layer 741 can be formed between the CMOS element and the upper layer of the interposer 710.

[0041] Figure 13 shows a top view of an intermediate layer 810, which includes interconnecting regions 812 having overlapping sub-regions 818, 820, 822, and 824. These overlapping sub-regions 818, 820, 822, and 824 have double-exposure regions 826 and 828, respectively, as well as exclusion regions 814 and sealing ring regions 816. In some examples, the intermediate layer 810 may include one or more crack mitigation features located at its corners, configured to reduce the likelihood of crack propagation through the intermediate layer 810. For example, in Figure 13, the corner 850 of the sealing ring region 816 has a diagonal edge (instead of a 90-degree angle). This diagonal corner configuration reduces the propagation of cracks from the corner 850 to more central areas of the intermediate layer 810. It is worth noting that the diagonal corner 850 and / or other crack mitigation features may be included in any of the intermediate layers 118, 230, 310, 410, 510, 610 and 710 previously discussed in Figures 1 through 12.

[0042] Figures 14 and 15 show a top view and a cross-sectional view along line EE, respectively, illustrating the orientation of the interposer layer 910 containing interconnect regions 912. Interposer region 912 has sub-regions 918, 920, 922, and 924 overlapping with double-exposure regions 926 and 928, an exclusion region 914, a first sealing ring region 916, and a second sealing ring region 917. Exclusion region 914 includes an exclusion region interconnect structure 930. At this stage of the manufacturing process, interposer layer 910 includes a mask layer having a pad oxide layer 940 and an overlying pad nitride layer 942. In this example, interposer layer 910 includes a first sealing ring interconnect structure 932 (e.g., an inner sealing ring) in the first sealing ring region 916 and a second sealing ring interconnect structure 952 (e.g., an outer sealing ring) in the second sealing ring region 917 for protecting interconnect regions 912. The first sealing ring interconnect structure 932 and the second sealing ring interconnect structure 952 are each coupled to one or more CMOS elements, each CMOS element having an n-well 954 with a p-type diffusion region 956. The CMOS elements are formed in a substrate 902. A polysilicon layer 941 may be formed between the CMOS elements and the upper layer of the interposer 910.

[0043] Figures 16 and 17 represent a top view and a cross-sectional view along line FF, respectively, showing the orientation of the interposer layer 1010 including the interconnect region 1012. The interconnect region 1012 has sub-regions 1018, 1020, 1022, and 1024 overlapping with the double exposure regions 1026 and 1028, an exclusion region 1014, a first sealing ring region 1016, and a second sealing ring region 1017. The exclusion region 1014 includes an exclusion region interconnect structure 1030, the first sealing ring region 1016 includes a first sealing ring interconnect structure 1032, and the second sealing ring region 1017 includes a second sealing ring interconnect structure 1052. At this stage of the manufacturing process, the interposer layer 1010 includes a mask layer having a pad oxide layer 1040 and an overlying pad nitride layer 1042. In this example, the first sealing ring interconnect structure 1032 and the second sealing ring interconnect structure 1052 are each coupled to one or more silicon-germanium (SiGe) transistors 1058 and 1060 formed in the substrate 1002. A polycrystalline silicon layer 1041 may be formed between the SiGe transistors 1058 and 1060 and the upper layer of the interposer 1010.

[0044] Figures 18 and 19 represent a top view and a cross-sectional view along line GG, respectively, showing the orientation of the interposer layer 1110 including the interconnect region 1112. The interconnect region 1112 has sub-regions 1118, 1120, 1122, and 1124 overlapping with the double exposure regions 1126 and 1128, an exclusion region 1114, a first sealing ring region 1116, and a second sealing ring region 1117. The exclusion region 1114 includes an exclusion region interconnect structure 1130, the first sealing ring region 1116 includes a first sealing ring interconnect structure 1132, and the second sealing ring region 1117 includes a second sealing ring interconnect structure 1152. At this stage of the manufacturing process, the interposer layer 1110 includes a mask layer having a pad oxide layer 1140 and an overlying pad nitride layer 1142. In this example, the first sealing ring interconnect structure 1132 and the second sealing ring interconnect structure 1152 are each coupled to one or more CMOS elements having a p-well 1162 with an n-type diffusion region 1164. The CMOS elements are formed in a substrate 1102. A polysilicon layer 1141 may be formed between the CMOS elements and the upper layer of the interposer 1110.

[0045] Figure 20 shows a top view of an aspect of interposer 1210, which includes interconnecting regions 1212 having overlapping sub-regions 1218, 1220, 1222, and 1224. Sub-regions 1218, 1220, 1222, and 1224 have double-exposure regions 1226 and 1228, an exclusion region 1214, a first sealing ring region 1216, and a second sealing ring region 1217. In this example, a second corner 1266 of the second sealing ring region 1217 has one or more crack mitigation features, such as a diagonal edge (instead of a 90-degree angle), configured to reduce the propagation of cracks from corner 1266 to more central areas of interposer 1210. It is worth noting that diagonal corners and / or other crack mitigation features may be included in any one of the previously discussed first sealing ring regions 916, 1016, 1116 and / or second sealing ring regions 917, 1017 and 1117 of the intermediate layers 910, 1010 and 1110 in Figures 14 to 19.

[0046] Figure 21 shows a top view of the intermediate layer 1310 including the interconnect region 1312. The interconnect region 1312 has sub-regions 1318, 1320, 1322, and 1324 overlapping with the double exposure regions 1326 and 1328, an exclusion region 1314, a first sealing ring region 1316, and a second sealing ring region 1317. In this example, the first corner 1350 of the first sealing ring region 1316 and the second corner 1366 of the second sealing ring region 1317 have diagonal edges and may optionally include one or more other crack mitigation features. It is worth noting that the diagonal corners and / or other crack mitigation features may be included in any of the intermediate layers 910, 1010, and 1110 previously discussed in Figures 14 through 19.

[0047] The systems and methods disclosed herein (including semiconductor system 100 and interposers 118, 230, 310, 410, 510, 610, 710, 810, 910, 1010, 1110, 1210, and 1310) provide a method for producing large-area interposers. For example, Figure 22 is a flowchart showing an exemplary method 1400 for producing large-area interposers. As will be understood from this disclosure, the order of operations within method 1400 is not limited to the order shown in Figure 22, but may be performed in one or more different orders depending on the specific circumstances and in accordance with this disclosure. Method 1400 may begin with operation 1410.

[0048] In operation 1412, method 1400 may include specifying an interconnect region, an exclusion region, and a first sealing ring region for an interposer layer to be fabricated on a wafer, wherein the exclusion region surrounds the interconnect region and the first sealing ring region surrounds the exclusion region. In operation 1414, method 1400 may include forming one or more front metal layers and one or more back metal layers using a lithography system, and connecting the front metal layers and back metal layers in the interconnect region through silicon vias. Notably, the interconnect region is larger than the exposure area of ​​the lithography system. Therefore, the front metal layer, back metal layer, and silicon vias can be formed by exposing sub-regions of the interconnect region, wherein the area of ​​each sub-region is equal to or smaller than the exposure area of ​​the lithography system. For example, a photoresist layer on the interconnect layer can be patterned using a lithography system by first exposing a first sub-region, then exposing a second sub-region, wherein the first and second sub-regions overlap, that is, at least some of the first and second regions are exposed by the lithography system more than once (e.g., with adjacent, overlapping lenses). This process can be repeated for multiple sub-regions and can be performed multiple times during the intermediate layer fabrication because individual layers are formed to create a front-side metal layer, a back-side metal layer, and silicon vias. For example, a mask layer can be patterned using an overlay lens of a lithography system. Once the mask layer is fully patterned and developed, an etching system can be used to etch the exposed material, and a deposition system can be used to deposit material to form a layer. This series of steps can be repeated multiple times to fabricate the intermediate layer. In operation 1416, method 1400 may include forming a first sealing ring interconnect structure in the first sealing ring region.

[0049] Optionally, method 1400 may include specifying a second sealing ring region surrounding the first sealing ring region and forming a second sealing ring interconnect structure in the second sealing ring region. Optionally, method 1400 may include forming one or more semiconductor elements functionally coupled to one or more exclusion region interconnect structures, the first sealing ring interconnect structure, and / or the second sealing ring interconnect structure. The semiconductor elements may be configured to modify the conductivity of the exclusion region interconnect structure, the first sealing ring interconnect structure, and / or the second sealing ring interconnect structure coupled thereto. Optionally, method 1400 may include specifying that the first sealing ring region and / or the second sealing ring region have diagonal edges at their corners. In some embodiments, method 1400 may include forming one or more crack mitigation features at one or more corners of the first sealing ring region and / or the second sealing ring region. Method 1400 may terminate at operation 1418.

[0050] Therefore, this disclosure provides a system comprising an interposer layer and a method for forming such a system, which may have an interconnect region that is significantly larger than that produced using certain existing methods.

[0051] According to one embodiment, an interposer layer is provided, including an interconnect region comprising one or more front metal layers, one or more back metal layers, and one or more front metal layers in the interconnect region being connected to one or more back metal layers through silicon vias, wherein the interconnect region is larger than the exposure area of ​​a lithography system used for production. The interposer layer also includes an exclusion region surrounding the perimeter of the interconnect region. The interposer layer also includes a first sealing ring region of a first sealing ring interconnect structure surrounding the perimeter of the exclusion region. The interconnect region is divided into two or more sub-regions, each sub-region being equal to or smaller than the exposure area of ​​the lithography system.

[0052] In some embodiments, the intermediary layer further includes a second sealing ring region, the second sealing ring region including a second sealing ring interconnection structure, wherein the second sealing ring region surrounds the perimeter of the first sealing ring region.

[0053] In some embodiments, the interposer further includes one or more semiconductor elements functionally coupled to one or more exclusion region interconnect structures, a first sealing ring interconnect structure, and / or a second sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structure, the first sealing ring interconnect structure, and / or the second sealing ring interconnect structure coupled to the one or more semiconductor elements.

[0054] In some embodiments, one or more semiconductor elements comprise complementary metal-oxide-semiconductor transistors (CMOS transistors) or silicon-germanium transistors (SiGe transistors).

[0055] In some embodiments, the intermediary layer further includes one or more crack mitigation features located at one or more corners of the first sealing ring region and / or the second sealing ring region.

[0056] In some embodiments, the corners of the first sealing ring region and / or the second sealing ring region have diagonal edges.

[0057] According to another embodiment, a system is provided that includes two or more dies, each die including one or more functional components configured to perform a task. The system also includes an interposer functionally coupled to each of the two or more dies and configured to transmit signals received from each of the two or more dies to another of the two or more dies and / or another electronic device. The interposer includes an interconnect region including one or more front-side metal layers, one or more back-side metal layers, and silicon vias connecting the one or more front-side metal layers in the interconnect region to the one or more back-side metal layers, wherein the interconnect region is larger than the exposure area of ​​the lithography system used for production. The interposer includes an exclusion region surrounding the perimeter of the interconnect region. The interposer includes a first sealing ring region having a first sealing ring interconnect structure, wherein the first sealing ring region surrounds the perimeter of the exclusion region. The interposer includes one or more semiconductor elements functionally coupled to one or more exclusion region interconnect structures and / or the first sealing ring interconnect structure located within the exclusion region, wherein the one or more semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structure and / or the first sealing ring interconnect structure coupled thereto.

[0058] In some embodiments, the system further includes a second sealing ring region, the second sealing ring region including a second sealing ring interconnection structure, wherein the second sealing ring region surrounds the perimeter of the first sealing ring region.

[0059] In some embodiments, the corners of the first sealing ring region and / or the second sealing ring region have diagonal edges.

[0060] In some embodiments, the system further includes one or more crack mitigation features located at one or more corners of the first sealing ring region and / or the second sealing ring region.

[0061] In some embodiments, one or more semiconductor elements comprise complementary metal-oxide-semiconductor transistors (CMOS transistors) or silicon-germanium transistors (SiGe transistors).

[0062] In some embodiments, the system further includes a packaging substrate functionally coupled to an interposer and a circuit board functionally coupled to the packaging substrate, wherein the packaging substrate is configured to transmit signals received from the interposer to the circuit board, and the circuit board is configured to transmit signals received from the packaging substrate to one or more other electronic components functionally coupled to the circuit board.

[0063] According to another embodiment, a method for forming an interposer layer is provided. The method includes designating a portion of an interposer layer to be fabricated on a wafer, wherein the portion of the interposer layer includes an interconnect region, an exclusion region, and a first sealing ring region of the interposer layer, wherein the exclusion region surrounds the interconnect region, and the first sealing ring region surrounds the exclusion region. The method further includes forming one or more front-side metal layers, one or more back-side metal layers, and silicon vias connecting the one or more front-side metal layers to the one or more back-side metal layers in the interconnect region using a lithography system, wherein the interconnect region is larger than the exposure area of ​​the lithography system, wherein the interconnect region is divided into two or more sub-regions, each sub-region being equal to or smaller than the exposure area of ​​the lithography system, wherein adjacent edges between the two or more sub-regions overlap, and a first sealing ring interconnect structure is formed in the first sealing ring region.

[0064] In some embodiments, a portion of the interposer layer on the designated wafer includes a designated first sealing ring region having a diagonal edge at the corner.

[0065] In some embodiments, the method further includes forming one or more crack mitigation features at one or more corners of the first sealing ring region.

[0066] In some embodiments, the method further includes forming one or more semiconductor elements in a wafer, the one or more semiconductor elements being functionally coupled to one or more exclusion region interconnect structures and / or first sealing ring interconnect structures, wherein the one or more semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structures and / or the first sealing ring coupled to the one or more semiconductor elements.

[0067] In some embodiments, the method further includes: designating a second sealing ring region surrounding the first sealing ring region; and forming a second sealing ring interconnection structure in the second sealing ring region.

[0068] In some embodiments, the method further includes forming one or more semiconductor elements in a wafer, the one or more semiconductor elements being functionally coupled to a second sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify the conductivity of the second sealing ring interconnect structure coupled to the one or more semiconductor elements.

[0069] In some embodiments, a portion of the interposer layer on the designated wafer includes a designated second sealing ring region having diagonal edges at the corners.

[0070] In some embodiments, the method further includes forming one or more crack mitigation features at one or more corners of the second sealing ring region.

[0071] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0072] The nature of this disclosure is best understood from the following detailed description when read with reference to the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 schematically illustrates a cross-sectional view of a portion of a semiconductor system including a first large-area interposer according to some embodiments; Figure 2 is a flowchart illustrating an exemplary method of forming certain layers of an interposer (such as the large-area interposer of Figure 1) according to some embodiments; Figures 3 and 4 schematically illustrate a perspective view and a top view of a second large-area interposer formed in a wafer according to some embodiments; Figures 5 and 6 schematically illustrate a top view and a cross-sectional view of a third large-area interposer according to some embodiments; Figures 7 and 8 schematically illustrate a top view and a cross-sectional view of a fourth large-area interposer according to some embodiments; Figures 9 and 10 schematically illustrate a top view and a cross-sectional view of a fifth large-area interposer according to some embodiments; Figures 11 and 12 schematically illustrate a top view and a cross-sectional view of a sixth large-area interposer according to some embodiments; Figure 13 schematically illustrates a top view of a seventh large-area interposer having a first sealing ring region, the corners of which have diagonal edges according to some embodiments; Figures 14 and 15 schematically show top and cross-sectional views of an eighth large-area interposer layer according to some embodiments; Figures 16 and 17 schematically show top and cross-sectional views of a ninth large-area interposer layer according to some embodiments; Figures 18 and 19 schematically show top and cross-sectional views of a tenth large-area interposer layer according to some embodiments; Figure 20 schematically shows a top view of an eleventh large-area interposer layer having a second sealing ring region and corner portions having diagonal edges according to some embodiments; Figure 21 schematically shows a top view of a twelfth large-area interposer layer having a first sealing ring region and a second sealing ring region and corner portions having diagonal edges according to some embodiments; and Figure 22 is a flowchart illustrating an exemplary method of forming a large-area interposer layer according to some embodiments. [Biomaterial Storage]

[0074] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An interposer layer comprising: an interconnect region including one or more front metal layers, one or more back metal layers, and a plurality of silicon vias connecting the one or more front metal layers in the interconnect region to the one or more back metal layers, wherein the interconnect region is larger than an exposure region of a lithography system for production, wherein, The interconnect region is divided into two or more sub-regions, each of which is equal to or smaller than the exposure region of the lithography system; an exclusion region, wherein the exclusion region surrounds the interconnect region for a circumference; and a first sealing ring region, including a first sealing ring interconnect structure, wherein the first sealing ring region surrounds the exclusion region for a circumference.

2. The intermediary layer as claimed in claim 1, further comprising a second sealing ring region, the second sealing ring region including a second sealing ring interconnection structure, wherein the second sealing ring region surrounds the perimeter of the first sealing ring region.

3. The interposer as claimed in claim 2, further comprising one or more semiconductor elements functionally coupled to one or more exclusion region interconnect structures, the first sealing ring interconnect structure, and / or the second sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify a conductivity of the exclusion region interconnect structure, the first sealing ring interconnect structure, and / or the second sealing ring interconnect structure coupled to the one or more semiconductor elements.

4. A semiconductor system comprising: two or more dies, each of the two or more dies having one or more functional components configured to perform a task; and an interposer layer functionally coupled to each of the two or more dies and configured to transmit a plurality of signals received from each of the two or more dies to another and / or another electronic component of the two or more dies, wherein, The interposer includes: an interconnect region comprising one or more front metal layers, one or more back metal layers, and a plurality of silicon vias connecting the one or more front metal layers in the interconnect region to the one or more back metal layers, wherein the interconnect region is larger than an exposure region of a lithography system for production; an exclusion region, wherein the exclusion region surrounds the perimeter of the interconnect region; a first sealing ring region comprising a first sealing ring interconnect structure, wherein the first sealing ring region surrounds the perimeter of the exclusion region; and one or more semiconductor elements functionally coupled to the one or more exclusion region interconnect structures, and / or the first sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify the conductivity of the exclusion region interconnect structure, and / or the first sealing ring interconnect structure coupled to the one or more semiconductor elements.

5. The semiconductor system of claim 4, further comprising a second sealing ring region including a second sealing ring interconnect structure, wherein the second sealing ring region surrounds the perimeter of the first sealing ring region.

6. The semiconductor system of claim 5, wherein a plurality of corners of the first sealing ring region and / or the second sealing ring region have a plurality of diagonal edges.

7. The semiconductor system of claim 5 further includes one or more crack mitigation features located at one or more corners of the first sealing ring region and / or the second sealing ring region.

8. A method of forming a semiconductor system, comprising: specifying a plurality of portions of an interposer to be produced on a wafer, wherein the portions of the interposer include an interconnect region, an exclusion region, and a first sealing ring region of the interposer, wherein the exclusion region surrounds the interconnect region, and the first sealing ring region surrounds the exclusion region; forming one or more front-side metal layers, one or more back-side metal layers, and a plurality of silicon vias connecting the one or more front-side metal layers to the one or more back-side metal layers in the interconnect region using a lithography system, wherein the interconnect region is larger than an exposure area of ​​the lithography system, wherein the interconnect region is divided into at least the first sub-region and the second sub-region by first exposing a first sub-region with the lithography system and then exposing a second sub-region with the lithography system, each of the first sub-region and the second sub-region being equal to or smaller than the exposure area of ​​the lithography system, wherein a plurality of adjacent edges between the first sub-region and the second sub-region overlap; and forming a first sealing ring interconnect structure in the first sealing ring region.

9. The method of claim 8, further comprising forming one or more semiconductor elements in the wafer, the one or more semiconductor elements being functionally coupled to one or more exclusion region interconnect structures and / or the first sealing ring interconnect structure, wherein the one or more semiconductor elements are configured to modify a conductivity of the exclusion region interconnect structure and / or the first sealing ring interconnect structure coupled to the one or more semiconductor elements.

10. The method of claim 8, further comprising: designating a second sealing ring region surrounding the first sealing ring region; and forming a second sealing ring interconnection structure in the second sealing ring region.

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