Integrated chip and method of forming the same

TW202638946APending Publication Date: 2026-09-16TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
TW114131355
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-06-30
Filing Date
2025-08-18
Publication Date
2026-09-16

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Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a lower inter-level dielectric (ILD) layer on a substrate, and an upper interconnect layer disposed within an upper ILD layer on the substrate. One or more intermediate ILD layers are disposed vertically between the lower ILD layer and the upper ILD layer. One or more intermediate interconnect layers are disposed within the one or more intermediate ILD layers. A via vertically extends between the lower interconnect layer and the upper interconnect layer. The via laterally contacts one or more sidewalls of the one or more intermediate interconnect layers.
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