Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate, pad structures, a filling dielectric layer, and a compressive stress layer. The pad structures and the filling dielectric layer are disposed on the semiconductor substrate, and the filling dielectric layer includes a first portion and a second portion. The first portion is disposed between the pad structures in a horizontal direction. The second portion is disposed above the pad structures in a vertical direction. The compressive stress layer is disposed on the filling dielectric layer and the pad structures. The second portion of the filling dielectric layer comprises an opening located above one of the pad structures in the vertical direction, the opening is filled with the compressive stress layer, and a thickness of the compressive stress layer is greater than a thickness of the second portion of the filling dielectric layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a compressive stress layer and a method for manufacturing the same. [Previous Technology]

[0002] With technological advancements, integrated circuit manufacturing processes have continuously improved, enabling the accumulation / formation of various electronic circuits on wafers. Semiconductor manufacturing processes for wafers include many steps, such as deposition processes to form thin films, photoresist coating to form patterned photoresists, exposure and development processes, and etching processes to pattern the thin films. During these processes, process conditions (such as, but not limited to, high temperatures) and / or the deposition of materials with different properties on the wafer can cause wafer warpage. Excessive warpage can affect the operation of components on the wafer and / or the yield of related processes. [Summary of the Invention]

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, which improves the warpage problem of the semiconductor device by using a combination of a compressive stress layer and a filled dielectric layer.

[0004] One embodiment of the present invention provides a semiconductor device, including a semiconductor substrate, a plurality of pad structures, a filling dielectric layer, and a compressive stress layer. The pad structures and the filling dielectric layer are disposed on the semiconductor substrate, and the filling dielectric layer includes a first portion and a second portion. The first portion is disposed between the plurality of pad structures in a horizontal direction, while the second portion is disposed on the plurality of pad structures in a vertical direction. The compressive stress layer is disposed on the filling dielectric layer and the plurality of pad structures. The second portion of the filling dielectric layer includes an opening located on one of the plurality of pad structures in a vertical direction, the compressive stress layer filling the opening, and the thickness of the compressive stress layer is greater than the thickness of the second portion of the filling dielectric layer.

[0005] One embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: A semiconductor substrate is provided, and a plurality of pad structures and a filling dielectric layer are formed on the semiconductor substrate, wherein the filling dielectric layer includes a first portion and a second portion. The first portion is disposed between the plurality of pad structures in a horizontal direction, and the second portion is disposed on the plurality of pad structures in a vertical direction. A compressive stress layer is formed on the filling dielectric layer and the plurality of pad structures, wherein the second portion of the filling dielectric layer includes an opening located on one of the plurality of pad structures in a vertical direction, the compressive stress layer fills the opening, and the thickness of the compressive stress layer is greater than the thickness of the second portion of the filling dielectric layer.

Implementation Method

[0006] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice the invention. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0007] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0008] The terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but also includes something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0009] The ordinal numbers used in the specification and the claims, such as “first” and “second”, are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element with another claimed element, or the order of manufacturing methods. The use of these ordinal numbers is only to make it clear to distinguish one claimed element with a certain name from another claimed element with the same name.

[0010] The term "etching" is generally used herein to describe a process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" may be considered a broad term that includes etching.

[0011] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0012] Please refer to Figure 1. Figure 1 is a schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. As shown in Figure 1, the semiconductor device 100 includes a semiconductor substrate W, a plurality of pad structures PD, a filling dielectric layer 50, and a compressive stress layer 52. The filling dielectric layer 50 and the plurality of pad structures PD are disposed on the semiconductor substrate W, and the filling dielectric layer 50 includes a first portion 50A and a second portion 50B. The first portion 50A is disposed between the plurality of pad structures PD in a horizontal direction D2, while the second portion 50B is disposed on the plurality of pad structures PD in a vertical direction D1. A compressive stress layer 52 is disposed on a filled dielectric layer 50 and a plurality of pad structures PD. A second portion 50B of the filled dielectric layer 50 includes an opening OP located on one of the plurality of pad structures PD in the vertical direction D1. The compressive stress layer 52 is filled into the opening OP, and the thickness of the compressive stress layer 52 (e.g., thickness TK5 or thickness TK6) is greater than the thickness of the second portion 50B of the filled dielectric layer 50 (e.g., thickness TK4). The design of filling the compressive stress layer 52 into the opening OP can relatively increase the proportion of compressive stress material in the material layer located on the pad structure PD, thereby improving the effect on warpage problems.

[0013] In some embodiments, the aforementioned vertical direction D1 can be considered as the thickness direction of the semiconductor substrate W. The semiconductor substrate W may have an upper surface TS and a bottom surface BS opposite each other in the vertical direction D1, and the aforementioned pad structure PD, filling dielectric layer 50, and compressive stress layer 52 may be disposed on one side of the upper surface TS. Horizontal directions that are substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface TS and / or the bottom surface BS of the semiconductor substrate W, but are not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or component and the bottom surface BS of the semiconductor substrate W may be greater than the distance in the vertical direction D1 between a relatively low position and / or component and the bottom surface BS of the semiconductor substrate W. The lower part or bottom of each component may be closer to the bottom surface BS of the semiconductor substrate W in the vertical direction D1 than the upper part or top of that component. Another component above a certain component may be considered relatively far from the bottom surface BS of the semiconductor substrate W in the vertical direction D1, while another component below a certain component may be considered relatively close to the bottom surface BS of the semiconductor substrate W in the vertical direction D1. The upper surface and upper part of a specific component described herein may respectively include the topmost surface and the uppermost part of that component in the vertical direction D1, while the bottom surface and bottom of a specific component may respectively include the bottommost surface and the bottommost part of that component in the vertical direction D1. The situation in which a specific component is disposed between two other objects in a certain direction may include, but is not limited to, the situation where the component is sandwiched between these two objects in this direction. Furthermore, the thickness of a particular component mentioned herein, unless otherwise specified, generally refers to the thickness of the component in the vertical direction D1.

[0014] In some embodiments, the semiconductor substrate W may include a substrate 10, a dielectric layer 22, an interconnect structure CS, a dielectric layer 28, a dielectric layer 30, and a plurality of via conductors VS. The substrate 10 may include a silicon substrate or other suitable semiconductor or non-semiconductor material. The dielectric layer 22 is disposed on the substrate 10, the interconnect structure CS is disposed in the dielectric layer 22, the dielectric layer 30 is disposed on the dielectric layer 22 and the interconnect structure CS, and the dielectric layer 28 is disposed between the dielectric layer 30 and the dielectric layer 22. The dielectric layers 22, 28, and 30 may respectively include oxide dielectric materials (e.g., silicon oxide), nitride dielectric materials (e.g., silicon nitride), carbide dielectric materials (e.g., silicon carbide), low-k dielectric materials (e.g., but not limited to dielectric materials with a dielectric constant lower than 2.7) or other suitable dielectric materials. The interconnect structure CS may include multiple conductors (e.g., conductors ML) and multiple via conductors (not shown) alternately arranged in the vertical direction D1 to form the required connection paths. In some embodiments, conductors ML may be considered as the uppermost conductors in the interconnect structure CS, via conductors VS may penetrate dielectric layer 30 and dielectric layer 28, and each pad structure PD may be electrically connected to the interconnect structure CS through the corresponding via conductor VS. In some embodiments, conductors ML may include a barrier layer 24 and conductive material 26 disposed on the barrier layer 24, via conductors VS may include a barrier layer 32 and conductive material 34 disposed on the barrier layer 32, and pad structure PD may include a barrier layer 42, a barrier layer 46, and conductive material 44 disposed between the barrier layers 42 and 46, but are not limited thereto. Barrier layers 24, 32, 42 and 46 may include titanium nitride, tantalum nitride or other suitable conductive barrier materials, while conductive materials 26, 34 and 44 may each include materials with relatively low resistivity such as copper, aluminum, tungsten or other suitable conductive materials.

[0015] In some embodiments, the visual design requires active components (e.g., transistors, diodes, etc.), passive components (e.g., capacitors, resistors, etc.), and / or associated wiring to be disposed on the substrate 10, and the pad structure PD can be electrically connected to the components and / or wiring located on the substrate 10 via the interconnect structure CS. In some embodiments, the semiconductor substrate W may include an image signal processor (ISP) or a semiconductor structure with other functions, and the pad structure PD can be regarded as a top metal conductive structure formed on the image signal processor or other semiconductor structure. Furthermore, the thickness TK1 of each pad structure PD may be significantly greater than the thickness of the wires (e.g., but not limited to wires ML) in the interconnect structure CS. For example, the thickness TK1 of each pad structure PD may be greater than 10,000 angstroms, for example, about 13,000 angstroms, but is not limited thereto. Because the pad structure PD is relatively thick, the filling dielectric layer 50 needs to have a good gap-filling effect in order to fill the spaces between the pad structure PD. For example, the filling dielectric layer 50 can be formed by a high-density plasma (HDP) deposition process, but is not limited thereto. The aforementioned high-density plasma deposition process may include a high-density plasma chemical vapor deposition (HDP-CVD) process or other suitable deposition methods, and the filling dielectric layer 50 may include a high-density plasma (HDP) oxide dielectric material or other suitable filling dielectric material. The compressive stress layer 52 includes a material that can provide greater compressive stress, such as tetraethoxysilane (TEOS) oxide or other suitable high-pressure stress materials. In some embodiments, the TEOS oxide can be formed by chemical vapor deposition, such as plasma-enhanced CVD (PECVD), but is not limited thereto. Because the interstitial filling effect of TEOS oxide materials formed by PECVD is relatively poor, a filler dielectric layer 50 can be used to first cover the pad structure PD before forming a compressive stress layer 52 that can provide greater compressive stress to improve the warping problem. Therefore, the compressive stress of the compressive stress layer 52 can be greater than that of the filler dielectric layer 50. For example, the compressive stress of the aforementioned high-density plasma oxide dielectric material can be approximately -136 MPa, while the compressive stress of the aforementioned TEOS oxide material can be approximately -370 MPa, but this is not a limitation. It is worth noting that the value of compressive stress is generally negative to indicate that the object is under compression, but when comparing the compressive stress of two different materials and / or layers in this paper, their absolute values ​​are compared.

[0016] In some embodiments, the bottom surface BS1 of each pad structure PD and the bottom surface BS2 of the first portion 50A of the filled dielectric layer 50 may be substantially coplanar, but are not limited thereto. Furthermore, the upper surface TS2 of the first portion 50A of the filled dielectric layer 50 and the upper surface TS1 of each pad structure PD may be substantially coplanar, or the upper surface TS2 may be slightly higher than the upper surface TS1 in the vertical direction D1. Therefore, the thickness TK2 of the first portion 50A of the filled dielectric layer 50 may be substantially equal to or slightly greater than the thickness TK1 of each pad structure PD, while the upper surface TS2 of the first portion 50A of the filled dielectric layer 50 is lower than the uppermost part TP of the second portion 50B of the filled dielectric layer 50 in the vertical direction D1. The thickness TK1 may be equal to the distance between the bottom surface BS1 and the upper surface TS1 in the vertical direction D1, and the thickness TK2 may be equal to the distance between the bottom surface BS2 and the upper surface TS2 in the vertical direction D1. Furthermore, the second portion 50B of the filling dielectric layer 50 can be directly connected to the first portion 50A. The thickness TK4 of the second portion 50B can be equal to the distance in the vertical direction D1 between the uppermost part TP of the second portion 50B and the upper surface TS1 of the pad structure PD, and the depth of the opening OP in the vertical direction D1 can be approximately equal to the thickness TK4. In some embodiments, the second portion 50B of the filling dielectric layer 50 located on each pad structure PD can have an opening OP corresponding to this pad structure, so the second portion 50B of the filling dielectric layer 50 can have multiple openings OP corresponding to multiple pad structures PD. The compressive stress layer 52 can fill each opening OP, and the compressive stress layer 52 disposed in the opening OP can directly contact the pad structure PD corresponding to this opening OP. In addition, the compressive stress layer 52 can cover the filling dielectric layer 50 and directly contact the first portion 50A and the second portion 50B of the filling dielectric layer 50.

[0017] In some embodiments, by controlling the size and formation position of the opening OP, the second portion 50B of the filling dielectric layer 50 can be minimized without affecting the filling dielectric layer 50 located between the pad structures PD, thereby relatively increasing the proportion of the compressive stress layer 52 in the material layer located above the pad structure PD and improving the effect on improving the warpage problem. Therefore, the thickness of the compressive stress layer 52 is greater than the thickness TK4 of the second portion 50B of the filling dielectric layer 50, and the thickness TK4 of the second portion 50B of the filling dielectric layer 50 can be less than the thickness TK2 of the first portion 50A of the filling dielectric layer 50. In some embodiments, the upper surface TS3 of the compressive stress layer 52 is higher than the uppermost TP of the second portion 50B of the filling dielectric layer 50 in the vertical direction D1, and the distance DS between the upper surface TS3 of the compressive stress layer 52 and the uppermost TP of the second portion 50B of the filling dielectric layer 50 in the vertical direction D1 is greater than the thickness TK4 of the second portion 50B of the filling dielectric layer 50. The thickness of the aforementioned compressive stress layer 52 may be equal to the distance in the vertical direction D1 between the upper surface TS3 of the compressive stress layer 52 and the upper surface TS2 of the first portion 50A of the filling dielectric layer 50 (e.g., equal to the thickness TK5) or the distance in the vertical direction D1 between the upper surface TS3 of the compressive stress layer 52 and the upper surface TS1 of the pad structure PD (e.g., equal to the thickness TK6). The thickness of the compressive stress layer 52 may be less than the thickness TK2 of the first portion 50A of the filling dielectric layer 50, but is not limited thereto.

[0018] Please refer to Figure 1 and Figures 2 through 6. Figures 2 through 6 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein Figure 3 illustrates a state after Figure 2, Figure 4 illustrates a state after Figure 3, Figure 5 illustrates a state after Figure 4, and Figure 6 illustrates a state after Figure 5. In some embodiments, Figure 1 may be considered as illustrating a state after Figure 6, but is not limited thereto. As shown in Figure 1, the fabrication method of this embodiment includes the following steps. First, a semiconductor substrate W is provided, and a plurality of pad structures PD and a filling dielectric layer 50 are formed on the semiconductor substrate W. The filling dielectric layer 50 includes a first portion 50A and a second portion 50B. The first portion 50A is disposed between the plurality of pad structures PD in the horizontal direction D2, and the second portion 50B is disposed on the plurality of pad structures PD in the vertical direction D1. Then, a compressive stress layer 52 is formed on the filled dielectric layer 50 and the plurality of pad structures PD. The second portion 50B of the filled dielectric layer 50 includes an opening OP located above one of the plurality of pad structures PD in the vertical direction D1. The compressive stress layer 52 is filled into the opening OP, and the thickness of the compressive stress layer 52 (e.g., thickness TK5 or thickness TK6) is greater than the thickness TK4 of the second portion 50B of the filled dielectric layer 50.

[0019] Further explanation: The fabrication method of this embodiment may include, but is not limited to, the following steps. As shown in Figure 2, a plurality of pad structures PD can be formed on the semiconductor substrate W. Each pad structure PD may include the aforementioned barrier layer 42, conductive material 44, and barrier layer 46, but is not limited thereto. Then, as shown in Figure 3, a filling dielectric material 50M is formed on the semiconductor substrate W. The filling dielectric material 50M covers the plurality of pad structures PD. A portion of the filling dielectric material 50M is located between the plurality of pad structures PD in the horizontal direction D2, and another portion of the filling dielectric material 50M is located above the plurality of pad structures PD in the vertical direction D1. In some embodiments, the filling dielectric material 50M can be formed by a high-density plasma deposition process. Due to the characteristics of this deposition process, the thickness TK3 of the filling dielectric material 50M located above the plurality of pad structures PD in the vertical direction D1 and the thickness TK2 of the filling dielectric material 50M located between the plurality of pad structures PD in the horizontal direction D2 may be substantially equal, but is not limited thereto. Then, as shown in Figures 3 to 5, an etching process 91 can be performed on the filling dielectric material 50M located above the plurality of pad structures PD in the vertical direction D1. A portion of the filling dielectric material 50M located above the plurality of pad structures PD can be removed by the etching process 91 to form an opening OP, and the opening OP exposes one of the pad structures PD. In some embodiments, a corresponding opening OP can be formed on each pad structure PD, and each opening OP can expose the corresponding pad structure PD. In some embodiments, a patterned mask layer 80 can be formed on the filling dielectric material 50M and the etching process 91 can be performed using the patterned mask layer 80 as a mask, but this is not a limitation. The patterned mask layer 80 may include patterned photoresist or other suitable masking materials, and the patterned mask layer 80 can be removed after the etching process 91.

[0020] After etching process 91, the filling dielectric material 50M located on the plurality of pad structures PD becomes the second portion 50B of the filling dielectric layer 50, and the filling dielectric material 50M located between the plurality of pad structures PD becomes the first portion 50A of the filling dielectric layer 50. The filling dielectric material 50M located between the plurality of pad structures PD in the horizontal direction D2 can be covered by the patterned mask layer 80 in etching process 91 and is not etched. Therefore, the thickness of the filling dielectric material 50M located between the plurality of pad structures PD before etching process 91 can be equal to the thickness of the first portion 50A of the filling dielectric layer 50 (e.g., both are thickness TK2), while the thickness TK3 of the filling dielectric material 50M located on the plurality of pad structures PD before etching process 91 is greater than the thickness TK4 of the second portion 50B of the filling dielectric layer 50. It is worth noting that the method for forming the filled dielectric layer 50 in this embodiment may include, but is not limited to, the steps shown in Figures 3 to 5 above, and the filled dielectric layer 50 with opening OP may be formed by other suitable methods as needed for the design.

[0021] Then, as shown in Figures 4 to 6, after etching process 91, a compressive stress material 52M can be formed covering a plurality of pad structures PD and a filling dielectric layer 50. The compressive stress material 52M can fill the opening OP, and the compressive stress of the compressive stress material 52M is greater than the compressive stress of the filling dielectric material 50M. In some embodiments, the compressive stress material 52M may include the TEOS oxide described above, and the compressive stress material 52M can be formed by chemical vapor deposition, such as plasma-assisted chemical vapor deposition, but is not limited thereto. Then, as shown in Figures 6 and 1, a planarization process 92 can be performed on the compressive stress material 52M, and the compressive stress material 52M becomes a compressive stress layer 52 after the planarization process 92. Planarization process 92 may include chemical mechanical polishing (CMP) or other suitable planarization methods. A portion of the compressive stress material 52M may be removed by planarization process 92, and the compressive stress material 52M remaining on the semiconductor substrate W after planarization process 92 becomes the aforementioned compressive stress layer 52. In this embodiment, the method for forming the compressive stress layer 52 may include, but is not limited to, the steps shown in Figures 6 and 1 above, and may be formed using other suitable methods as required by the design, as shown in Figure 1. The compressive stress layer 52 may directly contact the plurality of pad structures PD, the first portion 50A of the filled dielectric layer 50, and the second portion 50B of the filled dielectric layer 50. The thickness of the compressive stress layer 52 can be controlled by planarization process 92 to avoid excessively thick compressive stress layer 52 from affecting other related processes.

[0022] In summary, in the semiconductor device and its manufacturing method of the present invention, the proportion of fill dielectric material in the material layer above the pad structure can be reduced by the above-described etching process, and the size and formation position of the opening formed by the etching process can be controlled. This allows for the minimization of fill dielectric material above the pad structure in the vertical direction without affecting the fill dielectric material between the pad structures. Furthermore, considering process capability (e.g., but not limited to alignment misalignment errors), some fill dielectric material will remain on the pad structure after the above-described etching process, becoming a second part of the fill dielectric layer. Therefore, the manufacturing method of the present invention forms a second part of the fill dielectric layer with openings. Under this design, the proportion of the compressive stress layer in the material layer above the pad structure can be relatively increased, thereby improving the effect on warpage reduction. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0023] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figures 2 to 6 are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 3 shows a schematic diagram of the situation after Figure 2; Figure 4 shows a schematic diagram of the situation after Figure 3; Figure 5 shows a schematic diagram of the situation after Figure 4; and Figure 6 shows a schematic diagram of the situation after Figure 5.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A plurality of pad structures are disposed on the semiconductor substrate; A filling dielectric layer is disposed on the semiconductor substrate, wherein the filling dielectric layer comprises a high-density plasma oxide dielectric material, and the filling dielectric layer comprises: a first portion disposed in a horizontal direction between the pad structures; and a second portion disposed on the pad structure in a vertical direction; and a compressive stress layer disposed on the filling dielectric layer and the pad structure, wherein the second portion of the filling dielectric layer includes an opening located on one of the pad structures in the vertical direction, the compressive stress layer fills the opening, and the thickness of the compressive stress layer is greater than the thickness of the second portion of the filling dielectric layer.

2. The semiconductor device as claimed in claim 1, wherein the compressive stress of the compressive stress layer is greater than the compressive stress of the filling dielectric layer.

3. The semiconductor device as claimed in claim 1, wherein the compressive stress layer disposed in the opening directly contacts one of the pad structures.

4. The semiconductor device as claimed in claim 1, wherein the compressive stress layer directly contacts the first portion of the filled dielectric layer.

5. The semiconductor device as claimed in claim 1, wherein the upper surface of the compressive stress layer is higher in the vertical direction than the uppermost part of the second portion of the filled dielectric layer.

6. The semiconductor device as claimed in claim 5, wherein the distance between the upper surface of the compressive stress layer and the uppermost portion of the second portion of the filled dielectric layer is greater than the thickness of the second portion of the filled dielectric layer.

7. The semiconductor device as claimed in claim 1, wherein the thickness of the second portion of the filled dielectric layer is less than the thickness of the first portion of the filled dielectric layer.

8. The semiconductor device as claimed in claim 1, wherein the upper surface of the first portion of the filled dielectric layer is lower in the vertical direction than an uppermost portion of the second portion of the filled dielectric layer.

9. The semiconductor device as claimed in claim 1, wherein the thickness of each of the pad structures is greater than 10,000 angstroms.

10. The semiconductor device as claimed in claim 1, wherein the semiconductor substrate includes an interconnect structure and each of the pad structures is electrically connected to the interconnect structure.

11. A method for manufacturing a semiconductor device, comprising: Provide a semiconductor substrate; A plurality of pad structures are formed on the semiconductor substrate; A filling dielectric layer is formed on the semiconductor substrate, wherein the filling dielectric layer comprises a high-density plasma oxide dielectric material, and the filling dielectric layer comprises: a first portion disposed in a horizontal direction between the pad structures; And a second portion disposed on the pad structure in a vertical direction; and a compressive stress layer formed on the filling dielectric layer and the pad structure, wherein the second portion of the filling dielectric layer includes an opening located on one of the pad structures in the vertical direction, the compressive stress layer fills the opening, and the thickness of the compressive stress layer is greater than the thickness of the second portion of the filling dielectric layer.

12. A method for manufacturing a semiconductor device as claimed in claim 11, wherein the method for forming the filled dielectric layer comprises: A filling dielectric material is formed on the semiconductor substrate, wherein the pad structure is covered by the filling dielectric material, a portion of the filling dielectric material is located between the pad structures in the horizontal direction, and another portion of the filling dielectric material is located above the pad structures in the vertical direction; and an etching process is performed on the filling dielectric material located above the pad structures in the vertical direction, wherein a portion of the filling dielectric material located above the pad structures is removed by the etching process to form the opening, and the opening exposes one of the pad structures in the pad structure.

13. A method of fabricating a semiconductor device as claimed in claim 12, wherein the filling dielectric material located on the pad structures after the etching process becomes the second portion of the filling dielectric layer, and the filling dielectric material located between the pad structures after the etching process becomes the first portion of the filling dielectric layer.

14. A method of fabricating a semiconductor device as claimed in claim 13, wherein the thickness of the filling dielectric material located on the pad structure prior to the etching process is greater than the thickness of the second portion of the filling dielectric layer.

15. A method of fabricating a semiconductor device as claimed in claim 13, wherein the thickness of the filling dielectric material located between the pad structures prior to the etching process is equal to the thickness of the first portion of the filling dielectric layer.

16. A method for manufacturing a semiconductor device as described in claim 12, wherein the method for forming the compressive stress layer comprises: After the etching process, a compressive stress material is formed to cover the pad structure and the fill dielectric layer; And a planarization process is performed on the compressive stress material, wherein the compressive stress material becomes the compressive stress layer after the planarization process.

17. A method for fabricating a semiconductor device as claimed in claim 12, wherein the filling dielectric material is formed by a high-density plasma (HDP) deposition process.

18. A method for manufacturing a semiconductor device as claimed in claim 11, wherein the compressive stress of the compressive stress layer is greater than the compressive stress of the filling dielectric layer.

19. A method of manufacturing a semiconductor device as claimed in claim 11, wherein the compressive stress layer directly contacts the pad structure, the first portion of the filled dielectric layer, and the second portion of the filled dielectric layer.

20. A method of manufacturing a semiconductor device as claimed in claim 11, wherein the distance between an upper surface of the compressive stress layer and an uppermost portion of the second portion of the filled dielectric layer is greater than the thickness of the second portion of the filled dielectric layer.

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