Semiconductor package structure and method of manufacturing the same

Abstract

A semiconductor package structure includes at least includes a first die, a second die and a third die that are stacked. The first die includes a first bonding interface structure. The second die includes a bottom bonding interface structure and a top bonding interface structure. The bottom bonding interface structure is disposed on a bottom bonding surface of the second die and bonded to the first bonding interface structure. The top bonding interface structure is disposed on a top bonding surface of the second die. The third die includes a third bonding interface structure, and the third bonding interface structure is bonded to the top bonding interface structure of the second die. The top bonding interface structure includes a multi-layer dielectric layer and bonding pads. A non-flatness interface is within the multi-layer dielectric layer, and the bonding pads are disposed in the multi-layer dielectric layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor packaging technology, and more particularly to a semiconductor packaging structure and a method for manufacturing the same. [Previous Technology]

[0002] As the size of semiconductor devices continues to shrink, 3D advanced packaging technology is being actively developed to achieve high-density interconnection and stacking of wafers (dies). Current wafer-on-wafer (WoW) packaging technology can meet the above development trend.

[0003] Moreover, in order to avoid defective products caused by errors in the front-end process (FEOL), back-end process (BEOL) and wafer bonding process, multiple electrical tests are generally performed during and after the entire packaging process, such as wafer acceptance test (WAT) or final test (FT).

[0004] However, the probes used in the above electrical tests may damage the flatness of the bonding surface, causing the hybrid bonding process in WoW packaging technology to affect the characteristics of the components or even cause the components to fail due to problems such as voids in the metal interface. [Summary of the Invention]

[0005] The present invention provides a semiconductor packaging structure and manufacturing method thereof, which can perform electrical testing after each wafer bonding without affecting the bonding surface of subsequently stacked wafers.

[0006] A method for manufacturing a semiconductor package structure according to the present invention includes the following steps: Manufacturing a plurality of package wafers. Mixing and bonding two of the plurality of package wafers to form a dual-layer package structure, wherein one of the package wafers in the dual-layer package structure has a plurality of substrate through-hole (TSV) structures. Forming a first dielectric layer on the dual-layer package structure to cover the plurality of substrate through-hole structures. Forming a sacrificial wiring layer in the first dielectric layer that is connected to the plurality of substrate through-hole structures. Forming a plurality of first test pads on the sacrificial wiring layer. Performing a first test on the dual-layer package structure via the plurality of first test pads. Removing the plurality of first test pads and the sacrificial wiring layer to form a plurality of trenches in the first dielectric layer. Forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the plurality of trenches. Forming a plurality of bonding pads within the first dielectric layer and the second dielectric layer.

[0007] In one embodiment of the present invention, the first test mentioned above includes wafer acceptance testing or final testing.

[0008] In one embodiment of the present invention, a method of manufacturing one of the plurality of packaged wafers includes forming at least one semiconductor element on a substrate; forming an interconnect structure on the substrate to couple the semiconductor element; forming an additional circuit layer on the interconnect structure; performing a second test on the interconnect structure and the semiconductor element via the additional circuit layer; and removing a portion of the surface of the additional circuit layer.

[0009] In one embodiment of the present invention, after removing a portion of the surface of the additional circuit layer, a bonding interface structure may be formed on the remaining portion of the additional circuit layer.

[0010] In one embodiment of the present invention, the above-mentioned bonding interface structure includes a dielectric layer and a plurality of bonding pads.

[0011] In one embodiment of the present invention, the second test described above includes wafer acceptance testing or final testing.

[0012] In one embodiment of the present invention, before forming the above-mentioned interconnect structure, the substrate through-hole structure passing through the substrate may also be formed.

[0013] A semiconductor packaging structure of the present invention includes a plurality of stacked dies, the plurality of dies including a first die, a second die, and a third die. The first die includes a first bonding interface structure. The second die includes a second bottom bonding interface structure and a second top bonding interface structure, the second bottom bonding interface structure being disposed on the bottom bonding surface of the second die and bonded to the first bonding interface structure, and the second top bonding interface structure being disposed on the top bonding surface of the second die. The third die includes a third bonding interface structure, and the third bonding interface structure is bonded to the second top bonding interface structure of the second die. The second top bonding interface structure includes multiple dielectric layers and a plurality of bonding pads. The multiple dielectric layers have uneven interfaces, and the bonding pads are disposed within the multiple dielectric layers.

[0014] In another embodiment of the present invention, a first portion of the plurality of bonding pads is disposed above an uneven interface in a multilayer dielectric layer, and a second portion of the plurality of bonding pads is disposed in the multilayer dielectric layer and passes through the uneven interface.

[0015] In another embodiment of the present invention, the first die includes a first substrate, at least one first semiconductor element, a first interconnect structure, and the first bonding interface structure. The first semiconductor element is disposed on the first substrate. The first interconnect structure is disposed on the first substrate and coupled to the first semiconductor element. The first bonding interface structure is disposed on the first interconnect structure.

[0016] In another embodiment of the present invention, the first grain may further include an additional circuit layer disposed on top of the first interconnect structure, and the thickness of the additional circuit layer is less than the thickness of the metallization layer in the first interconnect structure.

[0017] In another embodiment of the present invention, the additional circuit layer is electrically connected to the metallization layer in the first interconnect structure.

[0018] In another embodiment of the present invention, the second die further includes a second substrate, at least one second semiconductor element, a second interconnect structure, and a plurality of substrate through-hole (TSV) structures. The second substrate is located between a second bottom bonding interface structure and a second top bonding interface structure. The second semiconductor element is disposed between the second substrate and the second bottom bonding interface structure. The second interconnect structure is disposed between the second semiconductor element and the second bottom bonding interface structure and is coupled to the second semiconductor element. The TSV structure of the second die passes through the second substrate and is coupled to the second interconnect structure and the second top bonding interface structure.

[0019] In another embodiment of the present invention, the second grain may further include an additional circuit layer disposed at the bottom of the second interconnect structure, and the thickness of the additional circuit layer is less than the thickness of the metallization layer in the second interconnect structure.

[0020] In another embodiment of the present invention, the above-mentioned additional circuit layer is electrically connected to the metallization layer in the second interconnect structure.

[0021] In another embodiment of the present invention, the third die includes a third substrate, at least one third semiconductor element, a third interconnect structure, the third bonding interface structure, and a plurality of TSV structures. The third semiconductor element is disposed between the third substrate and the third bonding interface structure. The third interconnect structure is disposed between the third semiconductor element and the third bonding interface structure and is coupled to the third semiconductor element. The third bonding interface structure is disposed between the third interconnect structure and the second die. The TSV structures pass through the third substrate and are coupled to the third interconnect structure.

[0022] In another embodiment of the present invention, the above-described semiconductor package structure may further include a wiring layer and a test pad. The wiring layer is disposed on the top surface of the third die. The test pad is disposed on the wiring layer.

[0023] In another embodiment of the present invention, the third grain further includes an additional circuit layer disposed at the bottom of the third interconnect structure, and the thickness of the additional circuit layer is less than the thickness of the metallization layer in the third interconnect structure.

[0024] In another embodiment of the present invention, the above-mentioned additional circuit layer is electrically connected to the metallization layer in the third interconnect structure.

[0025] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

Implementation Method

[0026] The present invention can be understood by referring to the following detailed description and in conjunction with the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0027] FIG1 is a cross-sectional schematic diagram of a semiconductor packaging structure according to the first embodiment of the present invention.

[0028] Referring to FIG1, the semiconductor package structure 10 of the first embodiment includes a plurality of stacked dies, the plurality of dies including a first die 100, a second die 102, and a third die 104. Although not shown in FIG1, more dies may be stacked in the semiconductor package structure 10, as will be described in detail below. The first die 100 includes a first bonding interface structure B1. In one embodiment, the first die 100 also includes a first substrate 106, a first semiconductor element 108, a first interconnect structure 110, and the aforementioned first bonding interface structure B1. The first semiconductor element 108 is disposed on the first substrate 106, and the number of the first semiconductor element 108 is not limited to that shown in the figure, and may be one or more, and the first semiconductor element 108 may be an element with different functions. A first interconnect structure 110 is disposed on a first substrate 106. The first interconnect structure 110 may include a metallization layer 112, a conductive plug (not shown), and an insulating layer 114. The conductive plug can connect upper and lower metallization layers 112, a first semiconductor element 108, and other components, thereby coupling the first interconnect structure 110 to the first semiconductor element 108. In one embodiment, the first die 100 may further include an additional circuit layer 116 disposed on top of the first interconnect structure 110, and the thickness t1 of the additional circuit layer 116 is less than the thickness t2 of the metallization layer 112 in the first interconnect structure 110. In one embodiment, the additional circuit layer 116 is electrically connected to the metallization layer 112 in the first interconnect structure 110 to perform electrical detection between the first interconnect structure 110 and the first semiconductor element 108 without damaging the metallization layer 112 in the first interconnect structure 110. The aforementioned electrical tests include, for example, Wafer Acceptance Test (WAT) or Final Test (FT). WAT refers to the electrical tests performed on the test structures on the wafer after all manufacturing processes are completed. By analyzing WAT data, problems in the semiconductor manufacturing process can be identified, and process anomalies can be detected. A first bonding interface structure B1 is disposed on the first interconnect structure 110. In one embodiment, the first bonding interface structure B1 includes multiple dielectric layers 118 and multiple bonding pads 120, wherein the bonding pads 120 are, for example, copper pads or other suitable metal pads, and the dielectric layers 118 are, for example, silicon oxide layers or other dielectric material layers. In one embodiment, there is an electrically connected portion (not shown) between the bonding pads 120 and the first interconnect structure 110, so that the first semiconductor element 108 in the first die 100 can be electrically coupled to the upper second die 102.

[0029] Referring again to FIG1, the second die 102 includes a second bottom bonding interface structure B2b and a second top bonding interface structure B2t. The second bottom bonding interface structure B2b is disposed on the bottom bonding surface 102a of the second die 102 and bonded to the first bonding interface structure B1. The second top bonding interface structure B2t is disposed on the top bonding surface 102b of the second die 102. In one embodiment, the second die 102 further includes a second substrate 122, a second semiconductor element 124, a second interconnect structure 126, and a plurality of substrate through-hole (TSV) structures 132. The second substrate 122 is located between the second bottom bonding interface structure B2b and the second top bonding interface structure B2t. In one embodiment, the thickness of the second substrate 122 is thinner than the thickness of the first substrate 106, and the second substrate 122 is, for example, a thinned substrate formed by a thinning process. The second semiconductor element 124 is disposed between the second substrate 122 and the second bottom bonding interface structure B2b. The number of the second semiconductor element 124 is not limited to that shown in the figure; it can be single or multiple, and the second semiconductor element 124 can be elements with different functions. The second interconnect structure 126 is disposed between the second semiconductor element 124 and the second bottom bonding interface structure B2b. The second interconnect structure 126 may include a metallization layer 128, a conductive plug (not shown), and an insulating layer 130. The conductive plug can connect the upper and lower metallization layers 128, the second semiconductor element 124, and other components, so that the second interconnect structure 126 is coupled to the second semiconductor element 124. The substrate through-hole structure 132 of the second die 102 passes through the second substrate 122 and couples the second interconnect structure 126 to the second top bonding interface structure B2b. In one embodiment, the second bottom bonding interface structure B2b includes multiple dielectric layers 136 and a plurality of bonding pads 138, wherein there is an electrically connected portion (not shown) between the bonding pads 138 and the second interconnect structure 126, so that the first semiconductor element 108 in the first die 100 and the second semiconductor element 124 in the second die 102 can be electrically coupled to the upper third die 104. The second top bonding interface structure B2t includes multiple dielectric layers 140 and 142 and a plurality of bonding pads 1461 and 1462. There is an uneven interface 144 between the multiple dielectric layers 140 and 142. This uneven interface 144 is a special structure created for electrical testing in the stage after bonding the first die 100 and the second die 102 but before bonding the third die 104, which will be described in detail below. In Figure 1, bonding pads 1461 and 1462 are therefore located in different locations. For example, bonding pad 1461 is formed on the uneven interface 144, while bonding pad 1462 is disposed in the multilayer dielectric layers 140 and 142 and passes through the uneven interface 144.In one embodiment, the second die 102 may further include an additional circuit layer 134 disposed at the bottom of the second interconnect structure 126, and the thickness of the additional circuit layer 134 is less than the thickness of the metallization layer 128 in the second interconnect structure 126. In one embodiment, the additional circuit layer 134 is electrically connected to the metallization layer 128 in the second interconnect structure 126 to perform electrical detection (such as WAT or FT) between the second interconnect structure 126 and the second semiconductor element 124 through the additional circuit layer 134, without damaging the metallization layer 128 in the second interconnect structure 126.

[0030] Referring again to Figure 1, the third die 104 includes a third bonding interface structure B3, and the third bonding interface structure B3 is bonded to the second top bonding interface structure B2t of the second die 102. In one embodiment, the third die 104 includes a third substrate 148, a third semiconductor element 150, a third interconnect structure 152, the third bonding interface structure B3, and a plurality of substrate through-hole structures 164. The third semiconductor element 150 is disposed between the third substrate 148 and the third bonding interface structure B3, and the number of the third semiconductor element 150 is not limited to that shown in the figure, and may be one or more, and the third semiconductor element 150 may be elements with different functions. In one embodiment, the thickness of the third substrate 148 is thinner than the thickness of the first substrate 106, and the third substrate 148 is, for example, a thinned substrate formed by a thinning process. The third interconnect structure 152 is disposed between the third semiconductor element 150 and the third bonding interface structure B3. The third interconnect structure 152 may include a metallization layer 154, a conductive plug (not shown), and an insulating layer 156. The conductive plug can connect the upper and lower metallization layers 154, the third semiconductor element 150, and other components, thereby coupling the third interconnect structure 152 to the third semiconductor element 150. The third bonding interface structure B3 is disposed between the third interconnect structure 152 and the second die 102. The substrate through-hole structure 164 passes through the third substrate 148 and is coupled to the third interconnect structure 152. In one embodiment, the third die 104 further includes an additional circuit layer 158 disposed at the bottom of the third interconnect structure 152, and the thickness of the additional circuit layer 158 is less than the thickness of the metallization layer 154 in the third interconnect structure 152. In one embodiment, the additional circuit layer 158 is electrically connected to the metallization layer 154 in the third interconnect structure 152 so as to perform electrical detection (such as WAT or FT) between the third interconnect structure 152 and the third semiconductor element 150 through the additional circuit layer 158, without damaging the metallization layer 154 in the third interconnect structure 152.

[0031] In one embodiment, the third bonding interface structure B3 includes multiple dielectric layers 160 and multiple bonding pads 162, wherein there is an electrically connected portion (not shown) between the bonding pads 162 and the third interconnect structure 152, so that the first semiconductor element 108 in the first die 100, the second semiconductor element 124 in the second die 102, and the third semiconductor element 150 in the third die 104 can be electrically coupled to the test structure above, such as the wiring layer 168 in the insulating layer 166 disposed above the third substrate 148 and multiple test pads 170 disposed on the wiring layer 168. In one embodiment, the semiconductor package structure 10 can be tested via the multiple test pads 170, such as wafer acceptance test (WAT) or final test (FT), wherein FT is the final test performed on the wafer after packaging is completed, and only wafers that pass the test will be shipped.

[0032] If four dies (or chips) are to be stacked, the wiring layer 168 and test pad 170 above the third die 104 can be removed after testing. After forming a bonding interface structure similar to the second top bonding interface structure B2t, it can be bonded to another die through a hybrid bonding process. Additionally, a wiring layer and test pad for testing can be formed above the other die at the top.

[0033] Figures 2A to 2G are schematic cross-sectional views of the manufacturing process of a semiconductor wafer in a semiconductor packaging structure according to a second embodiment of the present invention.

[0034] Referring to FIG2A, in order to fabricate a semiconductor wafer (packaged wafer), at least one semiconductor element 204 and a substrate through-hole (TSV) structure 208 through the substrate 200 can be formed on a substrate 200 first. In one embodiment, before forming the substrate through-hole structure 208, a conductive structure such as a contact window 206 can be formed in the dielectric layer 202 on the substrate 200 to electrically connect with the semiconductor element 204, and then the substrate through-hole structure 208 is formed in the dielectric layer 202 and the substrate 200 using through-hole technology.

[0035] Referring to FIG2B, an interconnect structure 210 is formed on the substrate 200 using a BEOL process. The interconnect structure 210 may include an insulating layer 212 and a metallization layer 214 and an interlayer window 216 formed within the insulating layer 212. The interlayer window 216 can connect the upper and lower metallization layers 214. Furthermore, an additional circuit layer 218 is formed on the interconnect structure 210. This additional circuit layer 218 has, for example, the same circuit pattern as the top metallization layer 214 and is electrically connected to the metallization layer 214.

[0036] Referring to Figure 2C, the interconnect structure 210 and the semiconductor device 204 are tested via the additional circuit layer 218, for example, wafer acceptance testing or final testing. WAT or FT testing generally uses a probe card 220 and the probes 222 below the probe card 220 are swiped across the additional circuit layer 218 on the surface of the interconnect structure 210.

[0037] Refer to Figure 2D. After the test, the surface of the interconnect structure 210 may form a damaged surface 224 due to the probe 222, resulting in an uneven surface on the surface above the interconnect structure 210.

[0038] Referring to FIG2E, a portion of the surface of the additional circuit layer 218 of FIG2D is removed using a removal process 226 to obtain a thinner additional circuit layer 218', that is, the thickness t2 of the remaining additional circuit layer 218' is less than the thickness t1 of the additional circuit layer 218 of FIG2D. The removal process 226 is, for example, an etching process or a chemical mechanical planarization (CMP) process, and a portion of the surface of the insulating layer 212 is also removed. In one embodiment, the additional circuit layer 218' and the insulating layer 212 are coplanar, but this is not a limitation.

[0039] Referring to Figure 2F, a dielectric layer 228 may be formed on the additional wiring layer 218' and the insulating layer 212. This dielectric layer 228 can planarize the surface of the interconnect structure 210, and can form wiring structures such as redistribution lines (not shown) within the dielectric layer 228.

[0040] Referring to Figure 2G, a bonding interface structure 234 is formed on the dielectric layer 228 to obtain the packaged wafer 20. The bonding interface structure 234 includes a dielectric layer 230 and a plurality of bonding pads 232. In addition, in order to reduce the height of the subsequently stacked semiconductor package structure, the back side of the substrate 200 can be ground to thin it.

[0041] Before explaining the packaging process, please refer to Figures 3 and 4. Figure 3 is a top view of the test component of the semiconductor package structure; Figure 4 is a cross-sectional view of the test component of Figure 3, where most of the structure is omitted and only a simplified diagram representing the test component is shown. The test component of the semiconductor package structure generally consists of a test key 300 and multiple test pads 302. The test key 300 contains complex circuitry and is electrically connected to the part under test, while the test pads 302 are electrically connected to the test key 300. When the probe 222 contacts the test pad 302, scratches (represented by a star shape in Figure 3) are easily formed on its surface. In this invention, the test pads 302 that contact the probe 222 are separately fabricated on the metallization layers M1~M3 of the interconnect structure, replacing the previous method of directly testing the metallization layers M3 of the interconnect structure with the probe 222. Therefore, the present invention does not affect the internal wiring of the original design, and can also remove a portion of the surface of the test pad 302 after testing, as shown in Figure 2E, to make its overall surface flat.

[0042] Figures 5A to 5F are schematic cross-sectional views of the manufacturing process of a semiconductor packaging structure according to the second embodiment of the present invention, wherein the same element symbols as those in Figure 2G are used to represent the same or similar parts and components, and the relevant content of the related or similar parts and components can also be referred to the content of Figures 2A to 2G, which will not be repeated here.

[0043] Referring to FIG5A, two of the multiple packaged chips are mixed and bonded to form a double-layer packaged structure including packaged chip 50a and packaged chip 50b. Packaged chip 50a has the same structure as packaged chip 20 in FIG2G, while packaged chip 50b is a structure in which the substrate 200 of packaged chip 20 in FIG2G is thinned and flipped, wherein multiple substrate through-hole structures 208 protrude from the back surface 200b of substrate 200. Then, a first dielectric layer 500 is formed on the double-layer packaged structure to cover the multiple substrate through-hole structures 208. In another embodiment, packaged chip 50a, as the bottom packaged chip, may omit the substrate through-hole structures.

[0044] Referring to FIG5B, a sacrificial wiring layer 502 connected to a plurality of substrate through-hole structures 208 is formed in the first dielectric layer 500, and a plurality of first test pads TP1 are formed on the sacrificial wiring layer 502. In one embodiment, the method for forming the sacrificial wiring layer 502 is, for example, to first form a patterned photoresist (not shown) on the first dielectric layer 500 and expose a portion of the first dielectric layer 500; then, using the patterned photoresist as an etching mask, the exposed first dielectric layer 500 is removed to form a trench, and then metal material is filled into the trench and the metal material outside the trench is removed to obtain the sacrificial wiring layer 502.

[0045] Referring to FIG5C, a first test is performed on the dual-layer package structure (i.e., the stacked package wafers 50a and 50b) via multiple first test pads TP1. In one embodiment, the first test includes a wafer acceptance test (WAT) or a final test (FT) via probe 504. Therefore, this embodiment can perform WAT or FT testing after each wafer bonding, and accurately detect at which stage of the process the abnormality occurred. Because the probe 504 has high hardness, such as a metal probe, an uneven damaged surface 506 is easily formed on the surface of the first test pads TP1.

[0046] Referring to FIG5D, the first test pad TP1 and the sacrificial wiring layer 502 of FIG5C are removed to form a plurality of trenches in the first dielectric layer 500. A portion of the surface of the first dielectric layer 500 may also be removed in this step, exposing the substrate through-hole structure 208. In one embodiment, the aforementioned removal method is, for example, etching. The surface of the first dielectric layer 500 thus becomes an uneven interface 508, wherein the thickness t4 of the trench portion of the first dielectric layer 500 is less than the thickness t3 of the remaining portion.

[0047] Referring to FIG5E, a second dielectric layer 510 is formed on the first dielectric layer 500, and the second dielectric layer 510 fills the trenches in the first dielectric layer 500. In one embodiment, the method for forming the second dielectric layer 510 is, for example, CVD process, ALD process, PECVD process, high-density CVD process, PVD process, etc., and the second dielectric layer 510 may be selected as a dielectric material with fluidity. Then, a plurality of bonding pads 512 are formed in the first dielectric layer 500 and the second dielectric layer 510. The first dielectric layer 500, the second dielectric layer 510 and the bonding pads 512 constitute a bonding interface structure 514, which can be used to bond with other wafers without metal interface void problems. The uneven interface 508 between the first dielectric layer 500 and the second dielectric layer 510 is a special structure generated for testing before stacking other packaged wafers, and therefore will not appear in semiconductor package structures where all wafers are stacked before FT testing.

[0048] Referring to Figure 5F, repeating the steps of Figures 5A to 5E, a wafer-on-wafer (WoW) package can be implemented on the packaged wafer 50b to stack another packaged wafer 50c, and the packaged wafer 50c and packaged wafer 50b may have the same structure. In another embodiment, the semiconductor elements and interconnect structure of the packaged wafer 50c may be different from that of the packaged wafer 50b, but have similar bonding interface structures 234 and 514. Then, a fourth packaged wafer 50d can be bonded to the bonding interface structure 514 of the packaged wafer 50c via hybrid bonding, and then an insulating layer 516, a wiring layer 518, and a plurality of test pads TP2 are generally formed on the packaged wafer 50d as shown in Figure 5B. Then, a second test is performed on the entire semiconductor package structure, for example, wafer acceptance testing or final testing using probe 504. Since no other wafers are bonded after the test, it is not a problem even if a destructive surface 506 is formed on the surface of the test pads TP2. After the semiconductor packaging structure is fabricated, it can be diced to form a die.

[0049] Although this embodiment stacks four packaged chips, it is not limited to this; in other embodiments, the number of packaged chips may be more or only three packaged chips may be stacked, as shown in the semiconductor package structure 10 of FIG1.

[0050] Based on the above, the present invention improves the manufacturing process of semiconductor packaging structures so that wafer testing (such as WAT or FT) can be performed using probes after each wafer bonding stage without affecting subsequent bonding processes and bonding interface structures. Therefore, the present invention can not only obtain the electrical test results of each packaged wafer (or die), but also obtain the electrical test results between two stacked wafers (or dies) without causing problems such as metal interface gaps caused by the test probes damaging the package bonding surface.

[0051] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0052] FIG1 is a cross-sectional schematic diagram of a semiconductor packaging structure according to a first embodiment of the present invention. FIG2A to FIG2G are cross-sectional schematic diagrams of the manufacturing process of a semiconductor wafer in a semiconductor packaging structure according to a second embodiment of the present invention. FIG3 is a top view of a test component of the semiconductor packaging structure. FIG4 is a cross-sectional schematic diagram of the test component of FIG3. FIG5A to FIG5F are cross-sectional schematic diagrams of the manufacturing process of a semiconductor packaging structure according to a second embodiment of the present invention.

Claims

1. A method for manufacturing a semiconductor package structure, comprising: Manufacturing multiple packaged chips; Two of the plurality of packaged wafers are hybridized to form a dual-layer package structure, wherein one of the packaged wafers in the dual-layer package structure has a plurality of substrate through-via (TSV) structures; a first dielectric layer is formed on the dual-layer package structure to cover the plurality of substrate through-via structures; a sacrificial wiring layer connected to the plurality of substrate through-via structures is formed in the first dielectric layer; a plurality of first test pads are formed on the sacrificial wiring layer; a first test is performed on the dual-layer package structure via the plurality of first test pads; the plurality of first test pads and the sacrificial wiring layer are removed to form a plurality of trenches in the first dielectric layer; a second dielectric layer is formed on the first dielectric layer and the second dielectric layer fills the plurality of trenches; and a plurality of bonding pads are formed in the first dielectric layer and the second dielectric layer.

2. A method for manufacturing a semiconductor package structure as claimed in claim 1, wherein the first test includes wafer acceptance testing or final testing.

3. A method for manufacturing a semiconductor package structure as claimed in claim 1, wherein the method for manufacturing one of the plurality of package wafers comprises: At least one semiconductor element is formed on a substrate; An interconnect structure is formed on the substrate to couple the at least one semiconductor element; An additional circuit layer is formed on the interconnect structure; a second test is performed on the interconnect structure and the at least one semiconductor device via the additional circuit layer; And the surface from which a portion of the additional circuit layer was removed.

4. A method of manufacturing a semiconductor package structure as claimed in claim 3, wherein after removing a portion of the surface of the additional circuit layer, a bonding interface structure is further formed on the remaining portion of the additional circuit layer.

5. A method for manufacturing a semiconductor package structure as claimed in claim 4, wherein the bonding interface structure includes a dielectric layer and a plurality of bonding pads.

6. A method for manufacturing a semiconductor package structure as claimed in claim 3, wherein the second test includes wafer acceptance testing or final testing.

7. A method for manufacturing a semiconductor package structure as claimed in claim 3, wherein before forming the interconnect structure, the method further includes forming the plurality of substrate through-hole (TSV) structures through the substrate.

8. A semiconductor package structure comprising a plurality of stacked dies, said plurality of dies comprising: The first grain includes a first bonding interface structure; The second grain includes a second bottom bonding interface structure and a second top bonding interface structure. The second bottom bonding interface structure is disposed on the bottom bonding surface of the second grain and bonded to the first bonding interface structure of the first grain, and the second top bonding interface structure is disposed on the top bonding surface of the second grain. And a third grain, including a third bonding interface structure, a second top bonding interface structure bonded to the second grain, wherein the second top bonding interface structure includes: a multilayer dielectric layer, wherein the multilayer dielectric layer has an uneven interface. And a plurality of bonding pads are disposed in the multilayer dielectric layer, wherein a first portion of the plurality of bonding pads is disposed above the uneven interface in the multilayer dielectric layer, and a second portion of the plurality of bonding pads is disposed in the multilayer dielectric layer and passes through the uneven interface.

9. The semiconductor package structure as claimed in claim 8, wherein the first die comprises: First substrate; At least one first semiconductor element is disposed on the first substrate; A first interconnect structure is disposed on the first substrate and coupled to the at least one first semiconductor element; And the first bonding interface structure is disposed on the first interconnect structure.

10. The semiconductor package structure as claimed in claim 9, wherein the first die further comprises: An additional wiring layer is disposed on top of the first interconnect structure, and the thickness of the additional wiring layer is less than the thickness of the metallization layer in the first interconnect structure.

11. The semiconductor package structure as claimed in claim 10, wherein the additional circuit layer is electrically connected to the metallization layer in the first interconnect structure.

12. The semiconductor package structure as claimed in claim 8, wherein the second die further comprises: The second substrate is located between the second bottom bonding interface structure and the second top bonding interface structure; At least one second semiconductor element is disposed between the second substrate and the second bottom bonding interface structure; a second interconnect structure is disposed between the at least one second semiconductor element and the second bottom bonding interface structure, and coupled to the at least one second semiconductor element. And multiple substrate through-hole (TSV) structures, which pass through the second substrate and couple the second internal interconnect structure to the second top bonding interface structure.

13. The semiconductor package structure as claimed in claim 12, wherein the second die further comprises: An additional circuit layer is disposed at the bottom of the second interconnect structure, and the thickness of the additional circuit layer is less than the thickness of the metallization layer in the second interconnect structure.

14. The semiconductor package structure as claimed in claim 13, wherein the additional circuit layer is electrically connected to the metallization layer in the second interconnect structure.

15. The semiconductor package structure as claimed in claim 8, wherein the third die comprises: Third substrate; At least one third semiconductor element is disposed between the third substrate and the third bonding interface structure; A third interconnect structure is disposed between the at least one third semiconductor element and the third bonding interface structure, and coupled to the at least one third semiconductor element; the third bonding interface structure is disposed between the third interconnect structure and the second die; and a plurality of substrate through-hole (TSV) structures pass through the third substrate and are coupled to the third interconnect structure.

16. The semiconductor package structure as described in claim 15, further comprising: A wiring layer is disposed on the top surface of the third die; And test pads, which are placed on the wiring layer.

17. The semiconductor package structure as claimed in claim 15, wherein the third die further comprises: An additional circuit layer is disposed at the bottom of the third interconnect structure, and the thickness of the additional circuit layer is less than the thickness of the metallization layer in the third interconnect structure.

18. The semiconductor package structure of claim 17, wherein the additional circuit layer is electrically connected to the metallization layer in the third interconnect structure.

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