Manufacturing method of semiconductor structure

Abstract

A manufacturing method of a semiconductor structure including the following steps is provided. A wafer structure is provided. A first wafer is bonded to the wafer structure. The first wafer includes a first substrate and a first device layer located on the first substrate. After the first wafer is bonded to the wafer structure, a first opening is formed in the first substrate. The first opening exposes the first device layer. A dielectric layer is formed on the first substrate and in the first opening. A first through-substrate via (TSV) passing through the first opening is formed in the dielectric layer. The first TSV extends into the first device layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure having a through-substrate via (TSV). Prior Technology

[0002] Some semiconductor structures have through-substrate vias that penetrate the substrate. These vias can be used to electrically connect stacked integrated circuits together. However, current through-substrate fabrication processes can adversely affect the semiconductor components within the component layer. Summary of the Invention

[0003] This invention provides a method for manufacturing a semiconductor structure that can prevent the substrate perforation process from adversely affecting the semiconductor elements in the element layer.

[0004] This invention provides a method for manufacturing a semiconductor structure, comprising the following steps: Providing a wafer structure. Bonding a first wafer to the wafer structure. The first wafer includes a first substrate and a first element layer located on the first substrate. After bonding the first wafer to the wafer structure, forming a first opening in the first substrate. The first opening exposes the first element layer. Forming a dielectric layer on the first substrate and in the first opening. Forming a first through-substrate via (TSV) through the first opening in the dielectric layer. The first substrate via extends into the first element layer.

[0005] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the minimum width of the first opening may be greater than the maximum width of the first substrate via.

[0006] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the first substrate via can directly contact the dielectric layer.

[0007] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the first substrate via can pass through the first element layer.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the first substrate via can be extended into the wafer structure.

[0009] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the width of the portion of the first opening closest to the first element layer may be smaller than the width of the portion of the first opening furthest from the first element layer.

[0010] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method for forming a first substrate via may include the following steps: forming a second opening in the dielectric layer and the first element layer; and forming a first substrate via in the second opening.

[0011] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method of bonding the first wafer to the wafer structure can be fusion bonding.

[0012] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method of bonding the first wafer to the wafer structure can be a hybrid bonding method.

[0013] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: Before forming the first opening, a thinning process is performed on the first substrate.

[0014] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the wafer structure may include a second wafer. The second wafer may include a second substrate and a second element layer located on the second substrate.

[0015] According to an embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, the second substrate does not have an opening aligned with the first opening.

[0016] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the second substrate may have a second opening aligned with the first opening.

[0017] According to one embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, the wafer structure may include a barrier layer. The bottom of the first substrate via may directly contact the barrier layer.

[0018] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: A second opening is formed in a first substrate. The second opening exposes a first element layer. A dielectric layer is formed in the second opening. A second substrate via is formed in the dielectric layer, extending through the second opening. The second substrate via extends into the first element layer.

[0019] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the second substrate via can directly contact the dielectric layer.

[0020] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the depths of the first substrate via and the second substrate via in the wafer structure may be different.

[0021] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the wafer structure may include a second wafer. The second wafer may include a second substrate and a second element layer located on the second substrate.

[0022] According to one embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the second substrate may have a third opening aligned with the first opening. The second substrate may not have an opening aligned with the second opening.

[0023] According to one embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the second substrate may have a third opening aligned with the first opening. The second substrate may also have a fourth opening aligned with the second opening.

[0024] Based on the above, in the semiconductor structure manufacturing method proposed in this invention, after the first wafer is bonded to the wafer structure, a first opening is formed in the first substrate. The first opening exposes the first element layer. A dielectric layer is formed on the first substrate and in the first opening. A first substrate via is formed in the dielectric layer, passing through the first opening. Since the first opening, dielectric layer, and first substrate via are formed after the first wafer is bonded to the wafer structure, the fabrication processes of the first opening, dielectric layer, and first substrate via can be prevented from adversely affecting the semiconductor elements in the first element layer. Furthermore, since the fabrication processes of the first opening, dielectric layer, and first substrate via are performed after the first wafer is bonded to the wafer structure, design freedom can be increased.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0026] Figures 1A to 1F are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Figure 2 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 3 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 4 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 5 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 7 is a top view of the semiconductor structure of Figure 1 according to some embodiments of the present invention. Figure 8 is a top view of the semiconductor structure of Figure 1 according to some other embodiments of the present invention. Implementation

[0027] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, the features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0028] Figures 1A to 1F are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention.

[0029] Referring to Figure 1A, a wafer structure WS1 is provided. The wafer structure WS1 may include a wafer W1. The wafer W1 may include a substrate 100 and a device layer 102 located on the substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the device layer 102 may include a semiconductor device 104, a dielectric structure 106, and a redistribution layer (RDL) 108. The semiconductor device 104 is located on the substrate 100. In some embodiments, the semiconductor device 104 is, for example, a logic device or a memory device. The dielectric structure 106 is located on the substrate 100. The semiconductor device 104 may be located within the dielectric structure 106. In some embodiments, the dielectric structure 106 may be a multilayer structure. In some embodiments, the material of the dielectric structure 106 is, for example, silicon oxide, silicon nitride, or a combination thereof. The redistribution layer 108 is located within the dielectric structure 106. The redistribution layer 108 may be a single-layer structure or a multilayer structure. The redistribution layer 108 may be electrically connected to the semiconductor element 104. In some embodiments, the material of the redistribution layer 108 is, for example, copper, tantalum, tantalum nitride, or a combination thereof.

[0030] Referring to Figure 1B, wafer W2 is bonded to wafer structure WS1. Wafer W2 includes a substrate 200 and a device layer 202 located on the substrate 200. In some embodiments, the substrate 200 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, device layer 202 may include semiconductor device 204, dielectric structure 206, and redistribution layer 208. Semiconductor device 204 is located on substrate 200. In some embodiments, semiconductor device 204 is, for example, a logic device or a memory device. Dielectric structure 206 is located on substrate 200. Semiconductor device 204 may be located within dielectric structure 206. In some embodiments, dielectric structure 206 may be a multilayer structure. In some embodiments, the material of dielectric structure 206 is, for example, silicon oxide, silicon nitride, or a combination thereof. Redistribution layer 208 is located within dielectric structure 206. Redistribution layer 208 may be a single-layer structure or a multilayer structure. Redistribution layer 208 may be electrically connected to semiconductor device 204. In some embodiments, the material of the redistribution layer 208 is, for example, copper, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the method for bonding the wafer W2 to the wafer structure WS1 may be fusion bonding or hybrid bonding.

[0031] In some embodiments, the substrate 200 may undergo a thinning process. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing process, or a combination thereof.

[0032] Referring to FIG1C, after wafer W2 is bonded to wafer structure WS1, an opening OP1 is formed in substrate 200. Opening OP1 exposes device layer 202. In some embodiments, the width WD1 of the portion of opening OP1 closest to device layer 202 may be smaller than the width WD2 of the portion of opening OP1 furthest from device layer 202. In this embodiment, substrate 100 does not have an opening aligned with opening OP1. In some embodiments, opening OP1 may be formed by patterning substrate 200 using lithography and etching processes.

[0033] Referring to Figure 1D, a dielectric layer 210 is formed on the substrate 200 and in the opening OP1. The wafer W2 may further include the dielectric layer 210. In some embodiments, the material of the dielectric layer 210 is, for example, silicon oxide. In some embodiments, the method for forming the dielectric layer 210 is, for example, chemical vapor deposition.

[0034] Referring to Figure 1E, an opening OP2 can be formed in the dielectric layer 210 and the device layer 202. In some embodiments, the opening OP2 can pass through the device layer 202. The opening OP2 can extend into the wafer structure WS1. In some embodiments, the opening OP2 can be formed by patterning the dielectric layer 210, the device layer 202, and the wafer structure WS1 using lithography and etching processes. In the process of forming the opening OP2, the redistribution layer 108a can be used as a barrier layer. That is, the wafer structure WS1 may include a barrier layer (e.g., redistribution layer 108a).

[0035] Referring to Figure 1F, a substrate via T1 can be formed in the opening OP2. This allows the substrate via T1 to be formed in the dielectric layer 210, passing through the opening OP1. The substrate via T1 extends into the device layer 202. The substrate via T1 can directly contact the dielectric layer 210. In some embodiments, the substrate via T1 can pass through the device layer 202. In some embodiments, the substrate via T1 can further extend into the wafer structure WS1. In some embodiments, the bottom of the substrate via T1 can directly contact a barrier layer (e.g., redistribution layer 108a). In some embodiments, the minimum width of the opening OP1 (e.g., width WD1) can be greater than the maximum width of the substrate via T1 (e.g., width WD3). In some embodiments, the material of the substrate via T1 is, for example, copper, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the method of forming the substrate via T1 may include the following steps: First, a substrate via material layer (not shown) filling the opening OP2 can be formed on the dielectric layer 210. Then, the substrate via material layer located outside the opening OP2 can be removed to form the substrate via T1. In some embodiments, the method for removing the substrate perforated material layer located outside the opening OP2 is, for example, chemical mechanical polishing.

[0036] Next, a redistribution layer 212 and a dielectric layer 214 may be formed on the dielectric layer 210. The redistribution layer 212 may be electrically connected to the substrate via T1. In some embodiments, the material of the redistribution layer 212 is, for example, copper, tantalum, tantalum nitride, or a combination thereof. The dielectric layer 214 is located on the dielectric layer 210. The redistribution layer 212 is located within the dielectric layer 214. In some embodiments, the material of the dielectric layer 214 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0037] As can be seen from the above embodiments, in the manufacturing method of semiconductor structure 10, after wafer W2 is bonded to wafer structure WS1, an opening OP1 is formed in substrate 200. Opening OP1 exposes device layer 202. A dielectric layer 210 is formed on substrate 200 and in opening OP1. A substrate via T1 is formed in dielectric layer 210, passing through opening OP1. Since opening OP1, dielectric layer 210, and substrate via T1 are formed after wafer W2 is bonded to wafer structure WS1, the fabrication processes of opening OP1, dielectric layer 210, and substrate via T1 can prevent adverse effects on semiconductor devices (e.g., semiconductor device 204) in device layers (e.g., device layer 202). Furthermore, since the fabrication processes of opening OP1, dielectric layer 210, and substrate via T1 are performed after wafer W2 is bonded to wafer structure WS1, design freedom can be increased.

[0038] Figure 2 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0039] Please refer to Figures 1F and 2. The differences between the semiconductor structure 20 in Figure 2 and the semiconductor structure 10 in Figure 1 are as follows: In Figure 1, wafer W2 is bonded to wafer structure WS1, and in Figure 2, wafer W2 is bonded to wafer structure WS2. Wafer structures WS1 and WS2 have different structures. In some embodiments, the method for bonding wafer W2 to wafer structure WS2 may be fusion bonding or hybrid bonding.

[0040] The differences between the wafer structure WS2 in Figure 2 and the wafer structure WS1 in Figure 1 are as follows. Wafer structure WS2 further includes at least one wafer W3. In this embodiment, the number of wafers W3 is taken as an example of multiple wafers, but the present invention is not limited thereto. As long as the number of wafers W3 is at least one, it falls within the scope of the present invention. In wafers W2 and W3, the same or similar components are represented by the same or similar symbols, and their descriptions are omitted. Furthermore, wafers W2 and W3 may have the same or different layout designs, and multiple wafers W3 may have the same or different layout designs.

[0041] In the wafer structure WS2, wafer W31 can be bonded to wafer W1, and wafer W32 can be bonded to wafer W31. In some embodiments, the method for bonding wafer W31 to wafer W1 may be fusion bonding or hybrid bonding. In some embodiments, the method for bonding wafer W32 to wafer W31 may be fusion bonding or hybrid bonding. In some embodiments, the substrate 200 of wafer W31 may have an opening OP11 aligned with opening OP1, and the substrate 200 of wafer W32 may have an opening OP12 aligned with opening OP1.

[0042] Furthermore, in semiconductor structure 10 and semiconductor structure 20, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0043] Figure 3 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0044] Referring to Figures 2 and 3, the differences between the semiconductor structure 30 in Figure 3 and the semiconductor structure 20 in Figure 2 are as follows. The method for manufacturing the semiconductor structure 30 may further include the following steps: An opening OP3 is formed in the substrate 200. The opening OP3 exposes the device layer 202. A dielectric layer 210 is formed in the opening OP3. A substrate via T2 is formed in the dielectric layer 210, passing through the opening OP3. The substrate via T2 extends into the device layer 202. The substrate via T2 can directly contact the dielectric layer 210. In some embodiments, the substrate via T2 can pass through the device layers 202 of wafer W2 and W3. In some embodiments, the depths of the substrate via T1 and the substrate via T2 in the wafer structure WS2 may be different. For example, as shown in Figure 3, the depth of the substrate via T1 in the wafer structure WS2 may be greater than the depth of the substrate via T2 in the wafer structure WS2. In this embodiment, as shown in FIG3, the substrate 200 of wafer W31 may have an opening OP11 for aligning opening OP1, and the substrate 200 of wafer W31 does not have an opening for aligning opening OP3. In this embodiment, as shown in FIG3, the substrate 200 of wafer W32 may have an opening OP12 for aligning opening OP1, and the substrate 200 of wafer W32 may have an opening OP31 for aligning opening OP3. Furthermore, a redistribution layer 213 may be formed on the dielectric layer 210. The redistribution layer 213 is located in the dielectric layer 214. The redistribution layer 213 may be electrically connected to the substrate via T2.

[0045] In some embodiments, the width WD4 of the portion of opening OP3 closest to component layer 202 may be smaller than the width WD5 of the portion of opening OP3 furthest from component layer 202. In some embodiments, the minimum width of opening OP3 (e.g., width WD4) may be greater than the maximum width of substrate via T2 (e.g., width WD6).

[0046] In some embodiments, wafer W31 may further include a redistribution layer 216. The redistribution layer 216 is located within dielectric layer 210. The redistribution layer 216 may be a single-layer or multi-layer structure. In some embodiments, the material of the redistribution layer 216 is, for example, copper, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the bottom of the substrate via T2 may directly contact a barrier layer (e.g., redistribution layer 216a).

[0047] Furthermore, in semiconductor structure 20 and semiconductor structure 30, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0048] Figure 4 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0049] Referring to Figures 3 and 4, the differences between the semiconductor structure 40 in Figure 4 and the semiconductor structure 30 in Figure 3 are as follows: In semiconductor structure 40, the substrate 200 of wafer W31 may have an opening OP32 for aligning opening OP3. In semiconductor structure 40, wafer structure WS2 may further include a barrier layer 218. The barrier layer 218 is located in the dielectric structure 206 of wafer W32. The bottom of the substrate via T2 may directly contact the barrier layer 218. In semiconductor structure 40, wafer structure WS2 may further include a barrier layer 220. The barrier layer 220 is located in the dielectric layer 210 of wafer W31. The barrier layer 220 may directly contact the barrier layer 218. In some embodiments, the barrier layer 218 and the barrier layer 220 may be bonding pads or redistribution layers.

[0050] Furthermore, in semiconductor structure 30 and semiconductor structure 40, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0051] Figure 5 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0052] Please refer to Figures 1F and 5. The differences between the semiconductor structure 50 in Figure 5 and the semiconductor structure 10 in Figure 1 are as follows. In Figure 1, wafer W2 is bonded to wafer structure WS1, and in Figure 5, wafer W2 is bonded to wafer structure WS3. Wafer structures WS1 and WS3 have different structures. In some embodiments, the method for bonding wafer W2 to wafer structure WS3 can be fusion bonding or hybrid bonding. In this embodiment, as shown in Figure 5, the bottom of the substrate via T1 can directly contact the barrier layer (e.g., redistribution layer 208a).

[0053] The wafer structure WS3 may include wafers W4, W5, and W6. Wafer W5 is bonded to wafer W4. In some embodiments, the method for bonding wafer W5 to wafer W4 may be a hybrid bonding method. Wafer W6 is bonded to wafer W5. In some embodiments, the method for bonding wafer W6 to wafer W5 may be a hybrid bonding method. Wafer W2 is bonded to wafer W6. In some embodiments, the method for bonding wafer W2 to wafer W6 may be a fusion bonding method or a hybrid bonding method.

[0054] Wafer W4 may include a substrate 300 and a component layer 302. Component layer 302 may include a semiconductor component 304, a dielectric structure 306, and a bonding pad 308. Wafer W5 may include a substrate 400, a component layer 402, a dielectric layer 404, a bonding pad 406, and a substrate via 408. Component layer 402 may include a semiconductor component 410, a dielectric structure 412, a redistribution layer 414, and a bonding pad 416. The substrate via 408 passes through the substrate 400 and is electrically connected to the bonding pad 406 and the redistribution layer 414. The dielectric structure 412 may be bonded to the dielectric structure 306, and the bonding pad 416 may be bonded to the bonding pad 308. In wafers W2 and W6, the same or similar components are represented by the same or similar symbols, and their descriptions are omitted. Furthermore, wafers W2 and W6 may have the same or different layout designs. The component layer 202 of wafer W6 may further include a bonding pad 222. The dielectric structure 206 of wafer W6 can be bonded to the dielectric layer 404, and the bonding pad 222 can be bonded to the bonding pad 406. The substrate 200 of wafer W6 may have an opening OP13 for alignment opening OP1, while the substrate 300 of wafer W4 does not have an opening for alignment opening OP1.

[0055] Furthermore, in semiconductor structure 50 and semiconductor structure 10, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0056] Figure 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0057] Please refer to Figures 1F and 6. The differences between the semiconductor structure 60 in Figure 6 and the semiconductor structure 10 in Figure 1 are as follows: In Figure 1, wafer W2 is bonded to wafer structure WS1, and in Figure 6, wafer W2 is bonded to wafer structure WS4. Wafer structures WS1 and WS4 have different structures. In some embodiments, the method for bonding wafer W2 to wafer structure WS4 may be fusion bonding or hybrid bonding.

[0058] The wafer structure WS3 may include wafer W1 and at least one wafer W7. Wafer W71 is bonded to wafer W1. In some embodiments, the method for bonding wafer W71 to wafer W1 may be fusion bonding or hybrid bonding. Wafer W72 is bonded to wafer W71. In some embodiments, the method for bonding wafer W72 to wafer W71 may be hybrid bonding. Wafer W2 is bonded to wafer W72. In some embodiments, the method for bonding wafer W2 to wafer W72 may be fusion bonding or hybrid bonding.

[0059] In wafers W2 and W7, identical or similar components are represented by identical or similar symbols, and their descriptions are omitted. Furthermore, wafers W2 and W7 may have identical or different layout designs. Wafer W71 may further include bonding pads 224. Bonding pads 224 are located in dielectric layer 210. The component layer 202 of wafer W72 may further include bonding pads 226. Bonding pads 226 are located in dielectric structure 206. The dielectric structure 206 of wafer W72 may be bonded to the dielectric layer 210 of wafer W71, and bonding pads 226 may be bonded to bonding pads 224. The substrate 200 of wafer W71 may have an opening OP14 for alignment opening OP1, and the substrate 200 of wafer W72 may have an opening OP15 for alignment opening OP1.

[0060] In this embodiment, as shown in FIG6, the bottom of the substrate via T1 can directly contact the barrier layer (e.g., redistribution layer 208a). In some embodiments, the wafer structure WS3 may further include the substrate via T3. The substrate via T3 is electrically connected to the bonding pad 224 and the redistribution layer 108. In this embodiment, as shown in FIG6, the bottom of the substrate via T3 can directly contact the barrier layer (e.g., redistribution layer 108a).

[0061] Furthermore, in semiconductor structure 60 and semiconductor structure 10, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0062] Figure 7 is a top view of the semiconductor structure of Figure 1 according to some embodiments of the present invention. Figure 8 is a top view of the semiconductor structure of Figure 1 according to other embodiments of the present invention. In Figures 7 and 8, some components in Figure 1 are omitted to clearly illustrate the positional relationship between the components in Figures 7 and 8.

[0063] Referring to Figures 7 and 8, the semiconductor structure 10 may include a plurality of substrate vias T1. In some embodiments, as shown in Figure 7, the substrate 200 may include a plurality of openings OP1, and each substrate via T1 may be located in a corresponding opening OP1. In other embodiments, as shown in Figure 7, the substrate 200 may include a single opening OP1, and the plurality of substrate vias T1 may be located in the same opening OP1.

[0064] Furthermore, in Figures 1F, 7 and 8, identical or similar components are represented by the same symbols, and their descriptions are omitted.

[0065] In summary, the semiconductor structure in the above embodiments includes the following steps: A wafer structure is provided. A first wafer is bonded to the wafer structure. The first wafer includes a first substrate and a first element layer located on the first substrate. After bonding the first wafer to the wafer structure, a first opening is formed in the first substrate. The first opening exposes the first element layer. A dielectric layer is formed on the first substrate and in the first opening. A first substrate via is formed in the dielectric layer, passing through the first opening. The first substrate via extends into the first element layer. Since the first opening, dielectric layer, and first substrate via are formed after the first wafer is bonded to the wafer structure, the fabrication processes of the first opening, dielectric layer, and first substrate via can be prevented from adversely affecting the semiconductor elements in the first element layer. Furthermore, since the fabrication processes of the first opening, dielectric layer, and first substrate via are performed after the first wafer is bonded to the wafer structure, design freedom is increased.

[0066] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0067] 10, 20, 30, 40, 50, 60: Semiconductor structure 100, 200, 300, 400: Base 102, 202, 302, 402: Component layers 104, 204, 304, 410: Semiconductor components 106, 206, 306, 412: Dielectric structure 108, 108a, 208, 212, 213, 216, 414: Rewire Layer 210, 214, 404: Dielectric layers 218, 220: Barrier layer 222, 224, 226, 308, 406, 416: Joint pads OP1, OP2, OP3, OP11, OP12, OP13, OP14, OP15, OP31, OP32: Openings T1, T2, 408: Substrate perforation W1, W2, W3, W4, W5, W6, W7, W31, W32, W71, W72: Wafers WD1, WD2, WD3, WD4, WD5, WD6: Width WS1, WS2, WS3, WS4: Wafer Structure

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide wafer structure; A first wafer is bonded to the wafer structure, wherein the first wafer includes a first substrate and a first element layer located on the first substrate; After the first wafer is bonded to the wafer structure, a first opening is formed in the first substrate, wherein the first opening exposes the first element layer; a dielectric layer is formed on the first substrate and in the first opening; And forming a first substrate via through the first opening in the dielectric layer, wherein the first substrate via extends into the first element layer, and the method of forming the first substrate via includes: forming a second opening in the dielectric layer and the first element layer; And forming the first substrate perforation in the second opening.

2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the minimum width of the first opening is greater than the maximum width of the first substrate via.

3. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate via directly contacts the dielectric layer.

4. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate through-hole passes through the first element layer.

5. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate via extends further into the wafer structure.

6. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the width of the portion of the first opening closest to the first element layer is smaller than the width of the portion of the first opening furthest from the first element layer.

7. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method of bonding the first wafer to the wafer structure includes a fusion bonding method.

8. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method of bonding the first wafer to the wafer structure includes a hybrid bonding method.

9. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: Before forming the first opening, the first substrate is thinned.

10. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the wafer structure includes a second wafer, and the second wafer includes a second substrate and a second element layer located on the second substrate.

11. A method of manufacturing a semiconductor structure as claimed in claim 10, wherein the second substrate does not have an opening aligned with the first opening.

12. A method of manufacturing a semiconductor structure as claimed in claim 10, wherein the second substrate has a third opening aligned with the first opening.

13. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the wafer structure includes a barrier layer and the bottom of the first substrate via is in direct contact with the barrier layer.

14. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: A third opening is formed in the first substrate, wherein the third opening exposes the first element layer; The dielectric layer is formed in the third opening; And a second substrate via is formed in the dielectric layer through the third opening, wherein the second substrate via extends into the first element layer.

15. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the second substrate via directly contacts the dielectric layer.

16. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the first substrate via and the second substrate via have different depths in the wafer structure.

17. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the wafer structure includes a second wafer, and the second wafer includes a second substrate and a second element layer located on the second substrate.

18. A method of manufacturing a semiconductor structure as claimed in claim 17, wherein the second substrate has a fourth opening aligned with the first opening, and the second substrate does not have an opening aligned with the third opening.

19. A method of manufacturing a semiconductor structure as claimed in claim 17, wherein the second substrate has a fourth opening aligned with the first opening, and the second substrate has a fifth opening aligned with the third opening.

Images