Method for manufacturing semiconductor device by wafer on wafer and semiconductor devices thereof

Abstract

The present disclosure is related to a method for manufacturing semiconductor device by wafer on wafer and semiconductor devices thereof. The method includes the steps of: determining a first good die and a first bad die of a first wafer; and at least one first micro bump is formed only on the surface of the first good die of the first wafer. Thus, in the wafer on wafer packaging process, the bad die does not contact and bond with the good die, so the good die will not be regarded as a bad product due to the contact and bonding with the bad die.

Description

[Technical Field]

[0001] This application relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device based on wafer stacking. [Previous Technology]

[0002] Semiconductor devices are used in various electronic devices and are implemented by at least one die. Circuit elements and circuit components are formed on the at least one die to perform the intended functions. For example, logic circuits, processor circuits, or memory are formed on the at least one die.

[0003] To improve the performance and size of semiconductor devices, three-dimensional packaging processes that integrate dies of different processes and properties have been proposed, such as WoW (Wafer-on-Wafer), CoWoS (Chip-on-Wafer-on-Substrate), and SoIC (Small-Outline Integrated Circuit). Among these, wafer-on-wafer (WoW) packaging involves stacking at least two wafers on top of each other and then dicing the stacked wafers to form a semiconductor device. In mass production of semiconductor devices, wafer-on-wafer packaging offers advantages such as high yield and low cost, and is therefore widely used in advanced processes. [Summary of the Invention]

[0004] This application proposes a semiconductor device manufacturing method and semiconductor device based on wafer stacking, which forms microbumps only on the good dies of the wafer and does not form microbumps on the surface of the bad dies. Therefore, in the wafer stacking wafer packaging process, the bad dies do not contact and bond with the good dies, and thus the good dies are not considered defective due to contact and bonding with the bad dies.

[0005] In order to achieve the above objectives, this application proposes a semiconductor device manufacturing method based on wafer stacking wafers, which includes: identifying a first good die and a first bad die of a first wafer; and forming at least one first microbump only on the surface of the first good die of the first wafer.

[0006] In order to achieve the above objectives, this application proposes a semiconductor device based on wafer stacking wafers, which is implemented by the above-described semiconductor device manufacturing method.

[0007] Based on the above, the semiconductor device manufacturing method and semiconductor device based on wafer stacking of this application form microbumps only on the good dies of the wafer, without forming microbumps on the surface of bad dies. Therefore, in the wafer stacking wafer packaging process, bad dies do not come into contact with good dies, and good dies are not considered defective because they come into contact with bad dies.

Implementation Method

[0009] Please refer to Figure 1, which is a schematic diagram of a wafer embodiment. Generally, multiple dies 11 are formed on the wafer 10, and each die 11 has an integrated circuit with the same function. For example, an integrated circuit of logic circuit, processor circuit or memory.

[0010] Please refer to Figures 2 to 4. Figure 2 is a schematic diagram of the first wafer of this application. Figure 3 is a schematic diagram of the second wafer of this application. Figure 4 is a schematic diagram of the semiconductor device manufacturing method based on wafer stacking of wafers of this application, which includes steps S100 to S600.

[0011] In step S100, a first wafer 100 and a second wafer 200 are provided. In this step, the first wafer 100 and the second wafer 200 are prepared. A plurality of dies 110 are formed on the first wafer 100, and a plurality of dies 210 are formed on the second wafer 200. The function of the integrated circuit of the die 110 and the function of the integrated circuit of the die 210 may be the same or different. The first wafer 100 and the second wafer 200 can be implemented by the wafer embodiment of FIG1.

[0012] In step S200, the first good die 111 and the first bad die 112 of the first wafer 100 are confirmed, and the second good die 211 and the second bad die 212 of the second wafer 200 are confirmed. In this step, the first wafer 100 and the second wafer 200 are tested to confirm the first good die 111 and the first bad die 112 of the first wafer 100 and the second good die 211 and the second bad die 212 of the second wafer 200. For example, probe cards are used to perform circuit testing on the die 110 of the first wafer 100 and the die 210 of the second wafer 200.

[0013] In step S300, at least one first microbump 120 is formed only on the first good die 111 of the first wafer 100, and at least one second microbump 220 is formed only on the second good die 211 of the second wafer 200. As shown in FIG5, in this step, at least one first microbump 120 is formed only on one surface of the first good die 111 of the first wafer 100, and at least one first microbump 120 is not formed on the first bad die 112 of the first wafer 100. At least one second microbump 220 is formed only on one surface of the second good die 211 of the second wafer 200, and at least one second microbump 220 is not formed on the second bad die 212 of the second wafer 200.

[0014] In step S400, a wafer stacking device 300 is formed by bonding the first wafer 100 and the second wafer 200, with at least one first microbump 120 and at least one second microbump 220 in contact connection. In this step, the surface of the first wafer 100 with at least one first microbump 120 is oriented towards the surface of the second wafer 200 with at least one second microbump 220, and the first wafer 100 and the second wafer 200 are bonded to each other after alignment. The bonded first wafer 100 and the second wafer 200 are stacked along the first direction D1 in FIG. 5. The first good die 111 of the first wafer 100 is in contact connection with at least one second microbump 220 of the second good die 211 of the second wafer 200 through at least one first microbump 120 thereon. The vertical projections of a first good die 111a and a second good die 211a, which are contacted and connected through at least one first microbump 120 and at least one second microbump 220, on the first wafer 100 or the second wafer 200 overlap with each other. As shown in FIG. 5, the first good die 111a and the second good die 211a are contacted and connected through at least one first microbump 120 and at least one second microbump 220, and the vertical projections of the first good die 111a and the second good die 211a on the first wafer 100 or the second wafer 200 overlap with each other. Meanwhile, since at least one first microbump 120 is not formed on the surface of the first bad die 112a in this embodiment, the first bad die 112a will not contact or connect with any die 210 of the second wafer 200 after the first wafer 100 and the second wafer 200 are stacked and bonded. As shown in FIG. 5, the first bad die 112b does not contact or connect with the second good die 211b of the second wafer 200.

[0015] In step S500, the wafer stacking assembly 300 is diced to form at least one semiconductor device 400. In this step, the wafer stacking assembly 300 is diced along a first direction D1 to form at least one semiconductor device 400, at least one semiconductor device 500, and / or at least one semiconductor device 600. The at least one semiconductor device 400 includes a first good die 111 and a second good die 211 that are in contact with each other. For example, the at least one semiconductor device 400 includes a first good die 111a and a second good die 211a that are in contact with each other. That is, the at least one semiconductor device 400 is a good product. The at least one semiconductor device 500 includes the first bad die 112 and the second bad die 212. The surfaces of the first bad die 112 and the second bad die 212 do not have at least one first microbump 120 and at least one second microbump 220 formed. The first bad die 112 and the second bad die 212 are not in contact with each other. At least one semiconductor device 500 is defective. At least one semiconductor device 600 includes a first defective die 112 and a second good die 211, or includes a first good die 111 and a second defective die 212. For example, as shown in FIG5, semiconductor device 600 includes a first defective die 112b and a second good die 211b. The first defective die 112b and the second good die 211b are not in contact with each other.

[0016] In step S600, the good and bad dies of the semiconductor device 600 are separated. In this step, the good and bad dies of the semiconductor device 600 are separated so that the good dies in the semiconductor device 600 can be used in other products or processes. As shown in FIG5, the first bad die 112b and the second good die 211b of the semiconductor device 600 are separated from each other so that the second good die 211b can be used in other products or processes. For example, the second good die 211b can be used in the CoWoS (Chip on Wafer on Substrate) packaging process. Since the good and bad dies of the semiconductor device 600 are not in contact with each other, the good dies of the semiconductor device 600 will not be considered defective because they are connected to the bad dies, thus preventing the entire semiconductor device 600 from being considered defective. This effectively improves the overall wafer yield.

[0017] Please refer to Figures 6 to 12. Figure 6 is a schematic diagram of an embodiment of step S300. Step S300 further includes steps S310 to S350. Figures 7 to 12 are schematic diagrams of an embodiment of forming microbumps. The following description uses a first wafer 100 as an example.

[0018] In step S310, a photoresist layer is formed. In this step, a photoresist layer 130 is formed on the surface of the first wafer 100. For example, a photoresist is coated on the surface of the first wafer 100 to form the photoresist layer 130.

[0019] In step S320, an exposure process is performed. In this step, based on the location of at least one first die 111 on the first wafer 100, an exposure process is performed on the photoresist layer 130 to transfer at least one solder joint location 140 to the photoresist layer 130. The at least one solder joint location 140 is the location where at least one first microbump 120 is formed on the surface of the first wafer 100. In one embodiment, the exposure process can be implemented using a photomask-free exposure technique. In another embodiment, the exposure process can be implemented using a photomask exposure technique. In the embodiment where the exposure process is implemented using a photomask exposure technique, the exposure process includes multiple exposure procedures, each exposure procedure being used to expose a single solder joint location 140. The exposure process is, for example, ultraviolet light exposure (UV exposure). For example, as shown in FIG9, after completing the exposure procedure for solder joint location 140a, the exposure procedure for solder joint location 140b is then completed to sequentially transfer multiple solder joint locations 140 to the photoresist layer 130. Therefore, in this embodiment, the number of exposure cycles is at least equal to or greater than the number of at least one first microbump 120. In an embodiment implementing this exposure process using a photomask-less exposure technique, multiple solder joint locations 140 can be simultaneously transferred to the photoresist layer 130. For example, solder joint locations 140a and 140b can be simultaneously transferred to the photoresist layer 130.

[0020] In step S330, a development process is performed. In this step, a development process is performed on the photoresist layer 130 to form a patterned photoresist layer 131 based on at least one solder joint location 140. For example, unexposed areas of the photoresist layer 130 are removed by spraying developer. As shown in FIG10, the material of the photoresist layer 130 corresponding to at least one solder joint location 140 is removed, thereby forming a patterned photoresist layer 131.

[0021] In step S340, a microbump is formed. In this step, at least one first microbump 120 is formed at at least one solder joint location 140, as shown in FIG11. For example, at least one first microbump 120 is formed at at least one solder joint location 140 by electroplating.

[0022] In step S350, the patterned photoresist layer 131 is removed. In this step, the patterned photoresist layer 131 is stripped, as shown in FIG12. Here, at least one first microbump 120 is formed on the surface of the first wafer 100, and at least one first microbump 120 is formed only on the surface of the first good die 111. The formation method of at least one second microbump 220 of the second wafer 200 is the same as that of at least one first microbump 120, so it will not be described again here.

[0023] In summary, the semiconductor device manufacturing method and semiconductor device based on wafer stacking of this application form microbumps only on the good dies of the wafer, without forming microbumps on the surface of bad dies. Therefore, in the wafer stacking wafer packaging process, bad dies do not contact and bond with good dies, so good dies will not be considered defective due to contact and bonding with bad dies, thereby improving the overall yield of the wafer and avoiding unnecessary costs caused by good dies being considered defective. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a schematic diagram of a wafer embodiment; Figure 2 is a schematic diagram of a first wafer according to an embodiment of the present application; Figure 3 is a schematic diagram of a second wafer according to an embodiment of the present application; Figure 4 is a schematic flowchart of a semiconductor device manufacturing method according to an embodiment of the present application; Figure 5 is a schematic diagram of wafer stacking according to an embodiment of the present application; Figure 6 is another schematic flowchart of a semiconductor device manufacturing method according to an embodiment of the present application; Figure 7 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (first); Figure 8 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (second); Figure 9 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (third); Figure 10 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (fourth); Figure 11 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (fifth); Figure 12 is a schematic flowchart of a semiconductor device manufacturing process according to an embodiment of the present application (sixth).

Claims

1. A method for manufacturing a semiconductor device based on wafer stacking, comprising: Identify the first good and first bad grains of a first wafer; The method involves forming at least one first microbump only on the surface of the first good die of the first wafer, comprising: forming a photoresist layer on the surface of the first wafer; performing an exposure process on the photoresist layer to transfer at least one solder joint location to the photoresist layer, wherein the exposure process is performed using a maskless exposure technique or a photomask exposure technique; performing a development process on the photoresist layer to form a patterned photoresist layer based on the at least one solder joint location; forming the at least one first microbump at the at least one solder joint location; and removing the patterned photoresist layer.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein, When the exposure process is performed using the photomask exposure technology, the exposure process includes multiple exposure procedures, the number of which is equal to or greater than the number of the at least one first microbump.

3. A method for manufacturing a semiconductor device as claimed in claim 1, comprising: Identify the second good grain and the second bad grain of a second wafer; And at least one second microbump is formed only on the surface of the second good grain of the second wafer.

4. A method for manufacturing a semiconductor device as described in claim 3, comprising: The first wafer and the second wafer are joined to form a wafer stacking device, and the at least one first microbump is in contact with the at least one second microbump. And to cut the wafer stacking device to form a semiconductor device.

5. The method for manufacturing a semiconductor device as claimed in claim 4, wherein, The semiconductor device includes a first good die or a first bad die from the first wafer and a second good die or a second bad die from the second wafer.

6. The method for manufacturing a semiconductor device as described in claim 5, further comprising: When the semiconductor device includes the first bad die and the second good die or includes the first good die and the second bad die, the plurality of dies of the semiconductor device are separated from each other.

7. A semiconductor device based on wafer stacking wafers, the semiconductor device being implemented by the semiconductor device manufacturing method of claim 1.

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