Test circuit and semiconductor device including the test circuit

Abstract

A test circuit is provided that reduces a threshold voltage shift due to BTI of an input transistor without consuming electric current, even in high-temperature environments. The circuit includes a PMOS transistor having a gate receiving a reference voltage, a source connected to a bulk transmitting a test signal from an input terminal, and a drain connected to a VSS terminal via a pull-down circuit. A diode serving as a backflow prevention circuit is connected between the input terminal and the source and bulk of the PMOS transistor to prevent signal backflow. Additionally, a diode serving as a clamp circuit is connected between the gate and the source and bulk of the PMOS transistor. The clamp circuit clamps a voltage drop of the bulk relative to the gate to a predetermined voltage.

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