Semiconductor device and method of forming fan-out wafer level cpo with through silicon conductive via
TW202640210APending Publication Date: 2026-10-01STATS CHIPPAC LTD
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Patent Information
- Application Number
- TW115102363
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-25
- Filing Date
- 2026-01-21
- Publication Date
- 2026-10-01
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Figure TWG2TA001079135_001 
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Abstract
A semiconductor device has a first electrical component with a coupler formed on a first surface of the first electrical component. The first electrical component can be a PIC and the coupler is an optically sensitive region. An encapsulant is deposited over and around the first electrical component. A conductive via is formed through the first electrical component. A clear coating is disposed over the coupler. A first interconnect structure is formed within a cavity of the encapsulant over the first surface of the first electrical component outside the coupler. A second interconnect structure is formed over a second surface of the first electrical component. An optical interposer panel is disposed over the first interconnect structure and encapsulant with an optical block disposed over the coupler. A second electrical component is disposed over the optical interposer panel. A heat spreader is disposed over the second electrical component.
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