Variable-length instruction set mode

Abstract

a variable-length instruction set mode, front end circuitry decodes instructions according to an encoding scheme based on an architectural encoding constraint requiring that a given instruction is encoded fully within a G-bit fetch granule, where G is a fixed power-of-2 integer, and no valid instruction is allowed to cross a boundary between G-bit fetch granules. A predetermined subset of bit positions within a given G-bit fetch granule is used to determine whether the granule is encoded according to a first subset of valid encodings encoding instructions corresponding to instructions of a fixed-length legacy instruction set, or a second subset of valid encodings encoding, according to a layout identified by a layout descriptor in the predetermined subset of bit positions, one or more instructions including at least one instruction of different length to the instructions encoded in the first subset of valid encodings. [Figure

Images