Flash memory access interface, flash memory module, and electronic device

Abstract

An access interface of a flash memory circuit, a flash memory module, and an electronic device are provided. The electronic device includes a host processor, a system bus, and the flash memory module. The host processor transmits a flash memory access command to the system bus. The access interface of the flash memory circuit includes a multiplexer, a command reroute module, and a de-multiplexer. The command reroute module includes an internal bus, a command passing circuit, and an agent processor. After receiving the flash memory access command, the de-multiplexer transmits a flash access command to a flash memory circuit or the command reroute module according to a component identification address. When the command reroute module receives the access command code, the agent processor accesses the flash memory circuit according to the access command code.

Description

[Technical Field]

[0001] This invention relates to a flash memory circuit access interface, a flash memory module and an electronic device, and more particularly to a flash memory circuit access interface, a flash memory module and an electronic device that reduces the waiting time for the main processor to perform access operations on the flash memory circuit. [Previous Technology]

[0002] Flash memory has advantages such as light weight, small size, and low power consumption. Therefore, many electronic products use flash memory as a built-in and / or external storage device.

[0003] Please refer to Figure 1, which is a schematic diagram of a conventional electronic device. The conventional electronic device 1 includes: a functional circuit 11, a host processor (HP), a system bus (SYS_BUS), and a flash memory circuit (fmCKT). The flash memory circuit (fmCKT) includes: a flash memory controller (fmCTL) and a flash memory array (fmARR).

[0004] In electronic device 1, system bus SYS_BUS is electrically connected to peripheral device 11 and main processor HP. When main processor HP needs to read data from flash memory circuit fmCKT, delete data, or write data to flash memory circuit fmCKT, main processor HP will first transmit the flash memory access address to system bus SYS_BUS. Then, system bus SYS_BUS, in conjunction with flash memory controller fmCTL, performs the corresponding read operation, delete operation, or write operation on the flash memory access address.

[0005] With the development of flash memory technology, different types of flash memory circuits (fmCKTs) have also developed different control methods. When the main processor HP is paired with certain types of flash memory circuits (e.g., Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)), the control flow required is relatively complex. When the main processor HP accesses such flash memory circuits (fmCKTs) with more complex control flows, it may require more control steps.

[0006] Even when using a non-SONOS technology flash memory circuit fmCKT, the main processor HP may have to wait for the flash memory circuit fmCKT to respond to access commands due to time-consuming operations such as erasing or writing large amounts of data. In short, in conventional electronic devices 1, the access speed of the flash memory circuit fmCKT causes efficiency delays in electronic devices 1. [Summary of the Invention]

[0007] This invention relates to a flash memory circuit access interface, a flash memory module, and an electronic device. By providing a flash memory circuit access interface between the system bus and the flash memory circuit, this invention improves the efficiency of the main processor's access to the flash memory circuit.

[0008] According to a first aspect of the present invention, a flash memory circuit access interface for an electronic device is provided. The electronic device includes a main processor and a system bus. The main processor transmits a flash memory access instruction including an access instruction code, a component identification address, and a flash memory access address to the system bus. The flash memory circuit access interface includes: a multiplexer, an access instruction rerouting module, and a demultiplexer. The multiplexer is electrically connected to the flash memory circuit. The access instruction rerouting module includes: an internal bus, an access instruction transfer circuit, and a proxy processor. The internal bus is electrically connected to the main processor and the multiplexer. The access instruction transfer circuit is electrically connected to the internal bus. The proxy processor is electrically connected to the internal bus and the access instruction transfer circuit. The demultiplexer is electrically connected to the system bus, the multiplexer, and the internal bus. After receiving flash memory access instructions via the system bus, the demultiplexer transmits the access instruction code and flash memory access address to either the multiplexer or the internal bus based on the component identification address. When the demultiplexer transmits the access instruction code and flash memory access address to the multiplexer, the main processor accesses the flash memory access address in the flash memory circuit according to the access instruction code. When the demultiplexer transmits the access instruction code and flash memory access address to the internal bus, the access instruction delivery circuit receives the access instruction code via the internal bus. Furthermore, the proxy processor accesses the flash memory access address in the flash memory circuit according to the access instruction code.

[0009] According to a second aspect of the present invention, a flash memory module is provided. The flash memory module includes: flash memory circuitry and flash memory circuitry access interface.

[0010] According to a third aspect of the present invention, an electronic device is provided. The electronic device includes: a system bus, a main processor, and a flash memory module.

[0011] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0012] As mentioned above, in conventional electronic devices, the main processor HP must wait for the flash memory circuit fmCKT to complete the control steps required for the access process, resulting in poor efficiency. Therefore, the embodiments of the electronic device disclosed herein provide multiple memory access paths, allowing the main processor HP to route the operation of the flash memory access instruction fmaccCMD according to considerations such as the purpose of the access, the required time, and the access order when accessing the flash memory circuit fmCKT. By this method of routed access to the flash memory access instruction fmaccCMD, the main processor HP does not need to spend time waiting for the response from the flash memory controller fmCTL.

[0013] Please refer to Figure 2, which is a schematic diagram of an electronic device according to a conceptual embodiment disclosed herein. The electronic device 2 includes: a functional circuit 21, a main processor HP, a semiconductor intellectual property core (IP) circuit ipCKT, a system bus SYS_BUS, and a flash memory module 22.

[0014] The flash memory module 22 includes: a flash memory access interface 29 and a flash memory circuit fmCKT. The flash memory access interface 29 is located between the system bus SYS_BUS and the flash memory circuit fmCKT. The flash memory circuit fmCKT includes: a flash memory controller fmCTL and a flash memory array fmARR.

[0015] The main processor HP and functional circuit 21 are electrically connected to the system bus SYS_BUS. Furthermore, the main processor HP is electrically connected to the semiconductor silicon intellectual property circuit ipCKT and the flash memory circuit access interface 29.

[0016] The flash memory circuit access interface 29 is electrically connected to the system bus SYS_BUS, the main processor HP, the semiconductor silicon intellectual property circuit ipCKT, and the flash memory controller fmCTL. Furthermore, the flash memory circuit access interface 29 is selectively electrically connected to the test equipment TM.

[0017] The flash memory circuit access interface 29 includes: a de-multiplexer DMUX, an access command reroute module cmdRRMdl, and a multiplexer MUX. The de-multiplexer DMUX, the access command reroute module cmdRRMdl, and the multiplexer MUX are electrically connected to each other.

[0018] The multiplexer DMUX is electrically connected to the system bus SYS_BUS. The access instruction rerouting module cmdRRMdl is selectively electrically connected to the test machine TM. The multiplexer MUX is electrically connected to the flash memory controller fmCTL.

[0019] Please refer to Figure 3, which is a schematic diagram of the composition of the flash memory access instruction fmaccCMD transmitted by the main processor HP. The flash memory access instruction fmaccCMD transmitted by the main processor HP includes: access instruction code cmdTYPE and instruction access address accADDR. Some flash memory access instructions fmaccCMD (e.g., write instruction wrtCMD) may further include: access data accDAT.

[0020] The access instruction code cmdTYPE varies depending on the type of operation the host processor HP is performing. For example, the host processor HP may issue write instructions wrtCMD, read instructions rdCMD, and erase instructions ersCMD to the flash memory circuit fmCKT. The types of operations provided by the host processor HP to the flash memory circuit fmCKT, and how these operation types correspond to the values ​​of the access instruction codes, are all application-specific variations and will not be detailed in this disclosure.

[0021] The instruction access address accADDR includes: the component identification address compADDR and the flash memory access address fmADDR. This disclosure assumes that the length of the instruction access address accADDR is M bits (e.g., M=32), the length of the component identification address compADDR is X bits (e.g., X=16), and the length of the flash memory access address fmADDR is Y bits (e.g., Y=4). Where M, X, and Y are all positive integers, and M≥(X+Y).

[0022] Please refer to Figure 4, which is a flowchart illustrating how the flash memory circuit access interface and the main processor HP dynamically change the access instruction code cmdTYPE and the transmission path of the flash memory access address fmADDR according to the type of access instruction issued by the main processor HP, based on the concept of the present disclosure. First, the main processor HP determines whether to perform a read operation on the flash memory circuit fmCKT (step S501).

[0023] If the judgment result of step S501 is positive, the main processor HP issues an access instruction code cmdTYPE field corresponding to the read instruction rdCMD (cmdTYPE=rdCMD), and the component identification address compADDR corresponds to the flash memory access instruction fmaccCMD of the multiplexer MUX (step S503).

[0024] If the judgment result of step S501 is negative, it means that the access instruction code cmdTYPE field in the flash memory access instruction fmaccCMD issued by the main processor HP corresponds to other types of access instructions, and the component identification address compADDR field in the flash memory access instruction fmaccCMD corresponds to the access instruction rerouting module cmdRRMdl (step S505).

[0025] After steps S503 and S505 are completed, the main processor HP transmits the flash memory access instruction fmaccCMD to the demultiplexer DMUX via the system bus SYS_BUS (step S507). As mentioned above, the flash memory access instruction fmaccCMD includes the access instruction code cmdTYPE field and the instruction access address accADDR field. The instruction access address accADDR field further includes the component identification address compADDR and the flash memory access address fmADDR. Furthermore, the component identification address compADDR may correspond to the multiplexer MUX (as described in step S503) or to the access instruction rerouting module cmdRRMdl (as described in step S505).

[0026] Therefore, after the demultiplexer DMUX receives the flash memory access instruction fmaccCMD from the system bus SYS_BUS, the demultiplexer DMUX can determine whether the flash memory access instruction fmaccCMD received from the system bus SYS_BUS corresponds to the multiplexer MUX based on the component identification address compADDR field of the flash memory access instruction fmaccCMD (step S551).

[0027] If the determination result of step S551 is positive, the demultiplexer DMUX transmits the access instruction code cmdTYPE=rdCMD and the flash memory access address fmADDR to the multiplexer MUX (step S553). Furthermore, the flash memory controller fmCTL executes the read instruction rdCMD on the flash memory located at flash memory access address fmADDR via the demultiplexer DMUX (step S555). Figure 5 shows the signal transmission direction between the main processor and the flash memory circuit fmCKT when the determination result of step S551 is positive.

[0028] If the judgment result of step S551 is negative, the demultiplexer DMUX transmits the access instruction code cmdTYPE and the flash memory access address fmADDR to the access instruction rerouting module cmdRRMdl (step S557). Furthermore, the access instruction rerouting module cmdRRMdl, according to the access instruction corresponding to the access instruction code cmdTYPE, and in conjunction with the flash memory controller fmCTL, accesses the flash memory access address fmADDR in the flash memory array fmARR (step S559). Figure 6 shows the signal transmission direction between the main processor HP and the flash memory circuit fmCKT when the judgment result of step S551 is negative.

[0029] Please refer to Figure 5, which is a schematic diagram of the main processor HP directly accessing the flash memory circuit fmCKT without going through the flash memory circuit access interface. Please also refer to Figures 4 and 5. Figure 5 corresponds to steps S503, S507, S553, and S555 in Figure 4.

[0030] When the main processor HP needs to perform a general read operation nmrdOP on the flash memory circuit fmCKT, the interaction between the main processor HP and the flash memory circuit fmCKT is indicated by the dashed arrow AR_hpNfm. That is, the main processor HP reads the data stored in the flash memory array fmARR sequentially via the system bus SYS_BUS, the demultiplexer DMUX, the multiplexer MUX, and the flash memory controller fmCTL. Furthermore, the data stored in the flash memory array fmARR is transmitted back to the main processor HP via the flash memory controller fmCTL, the multiplexer MUX, the demultiplexer DMUX, and the system bus SYS_BUS.

[0031] Please refer to Figure 6, which is a schematic diagram of the main processor HP indirectly accessing the flash memory circuit fmCKT via the flash memory circuit access interface. Please also refer to Figures 4 and 6. Figure 6 corresponds to steps S505, S507, S557, and S559 in Figure 4.

[0032] In Figure 6, the main processor HP and the flash memory circuit fmCKT need to interact through the access instruction rerouting module cmdRRMdl. As shown by the dashed arrow AR_hpNarc, the main processor HP can first transmit the flash memory access instruction fmaccCMD to the access instruction rerouting module cmdRRMdl via the system bus SYS_BUS and the demultiplexer DMUX. After the main processor HP transmits the flash memory access instruction fmaccCMD to the access instruction rerouting module cmdRRMdl, it can be used to execute other functions unrelated to the flash memory circuit fmCKT. For example, control function circuit 21, etc.

[0033] The access instruction rerouting module cmdRRMdl can execute the flash memory access instruction fmaccCMD issued by the main processor HP. While the main processor HP executes the control function circuit 21, the access instruction rerouting module cmdRRMdl, through the multiplexer MUX and the flash memory controller fmCTL, acts as an agent for the processor AP to execute the flash memory access instruction fmaccCMD of the main processor HP on the flash memory array fmARR, as shown by the dashed arrow AR_arcNfm. When the access instruction rerouting module cmdRRMdl confirms that the flash memory circuit fmCKT has completed the flash memory access instruction fmaccCMD previously issued by the main processor HP, the access instruction rerouting module cmdRRMdl then reports to the main processor HP that the flash memory access instruction fmaccCMD has been completed, in the manner shown by the dashed arrow AR_hpNarc, through the demultiplexer DMUX and the system bus SYS_BUS.

[0034] According to the concept disclosed herein, the flash memory circuit access interface 29 can be applied to a variety of applications. Firstly, it saves the main processor's HP waiting time; secondly, it assists the test equipment TM in testing the function of the flash memory circuit fmCKT; and thirdly, it is used in conjunction with the semiconductor silicon intellectual property circuit ipCKT for parameter calibration. Hereinafter, the internal components of the flash memory circuit access interface 29 will be explained using Figure 7. Next, it will be explained how to apply the flash memory circuit access interface 29 to these three applications.

[0035] Please refer to Figure 7, which is a block diagram of the flash memory circuit access interface. As mentioned above, the flash memory circuit access interface 29 includes: a demultiplexer DMUX, an access instruction rerouting module cmdRRMdl, and a multiplexer MUX. The demultiplexer DMUX, the access instruction rerouting module cmdRRMdl, and the multiplexer MUX are electrically connected to each other. Furthermore, the demultiplexer DMUX is electrically connected to the system bus SYSBUS, and the multiplexer MUX is electrically connected to the flash memory controller fmCTL.

[0036] The access instruction rerouting module cmdRRMdl includes: access instruction transfer circuit 2931, agent processor AP, internal reroute bus SUBSYS_BUS, non-volatile storage circuit 2935, volatile storage circuit 2937, and low pin count (LPC) interface circuit 2939.

[0037] The access instruction transfer circuit 2931 includes multiple registers for different purposes. These registers are all electrically connected to the internal bus SUBSYS_BUS. Through these registers, the main processor HP and the agent processor AP can exchange information related to the flash memory access instruction fmaccCMD, such as instruction type and instruction execution status.

[0038] Before the electronic device 2 leaves the factory, the manufacturer can connect the test equipment TM and the access instruction rerouting module cmdRRMdl using a Joint Test Action Group (JTAG) cable. The agent processor AP and the test equipment TM communicate via an LPC interface circuit 2939 with a relatively small number of pins. For example, the LPC interface circuit 2939 can be a Serial Peripheral Interface Bus (SPI) or an Inter-Integrated Circuit (I2C). The configuration of the LPC interface circuit 2939 allows the test equipment TM to simultaneously connect to a larger number of flash memory circuits fmCKT for functional testing.

[0039] Furthermore, since the access instruction rerouting module cmdRRMdl includes non-volatile storage circuit 2935 and volatile storage circuit 2937, the proxy processor AP can be used in conjunction with the non-volatile storage circuit 2935 and volatile storage circuit 2937 to assist the test equipment TM in performing more advanced and diverse tests on the flash memory circuit fmCKT.

[0040] The non-volatile storage circuit 2935 can be read-only memory (ROM) or flash memory. Preferably, the non-volatile storage circuit 2935 is read-only memory. The volatile storage circuit 2937 is random-access memory (RAM).

[0041] The instruction transfer circuit 2931 includes: an instruction register (cmdREG), a status register (stsREG), a start register (strtREG), a completion register (cpltREG), a calibration data register (ipREG), and an address register (addrREG). According to the concept disclosed herein, the instruction register (cmdREG), the status register (stsREG), the start register (strtREG), and the completion register (cpltREG) can be regarded as communication media between the proxy processor (AP) and the main processor (HP) and the test equipment (TM) (see Figures 8-18); the address register (addrREG) can be regarded as communication media between the proxy processor (AP) and the test equipment (TM) (see Figures 19-20); and the calibration data register (ipREG) can be used to assist the semiconductor silicon intellectual property circuit (ipCKT) in calibration (see Figures 21-23).

[0042] According to the concept disclosed herein, the number of bits contained in the instruction register cmdREG and the status register stsREG depends on the number of access instructions issued by the main processor HP and the types of access instruction execution results. On the other hand, the start register strtREG and the completion register cpltREG can be regarded as flags with a length of one bit.

[0043] For example, when the main processor HP needs to notify the agent processor AP to start executing a access instruction, the main processor HP will set the start register strtREG (for example, strtREG="1"). The set start register strtREG will generate an agent processor interrupt signal intrSIG2ap to notify the agent processor AP that it should start executing the access instruction. After receiving the agent processor interrupt signal intrSIG2ap from the start register strtREG, the agent processor AP will execute the corresponding access instruction according to the access instruction code cmdTYPE stored in the instruction register cmdREG by the main processor HP, and will also clear the setting of the start register strtREG (for example, strtREG="0"), so as to wait for the main processor HP to set the start register strtREG again.

[0044] For example, when the proxy processor AP finishes executing the access instruction, the proxy processor AP sets the completion register cpltREG (for example, cpltREG="1"). The set completion register cpltREG will generate a main processor interrupt signal intrSIG2hp to notify the main processor HP that the access instruction has been completed. After receiving the main processor interrupt signal intrSIG2hp from the completion register cpltREG, the main processor HP will read the value stored in the status register stsREG by the proxy processor AP and clear the setting of the completion register cpltREG (for example, cpltREG="0"), so as to wait for the proxy processor AP to set the completion register cpltREG again.

[0045] The calibration data register ipREG is used to store the calibration parameters corresponding to the silicon intellectual property circuit ipCKT. Therefore, the number of calibration data registers ipREG is equal to the number of silicon intellectual property circuits ipCKT. Furthermore, the calibration data register ipREG is directly electrically connected to the corresponding silicon intellectual property circuit ipCKT. The silicon intellectual property circuit ipCKT can obtain the calibration parameters in the calibration data register ipREG via a physical wiring signal, achieving the effect of parameter calibration.

[0046] Figures 8, 9A, 9B, and 10 will illustrate the various access paths in electronic device 2 related to the main processor HP executing access instructions on the flash memory circuit fmCKT. Subsequently, flowcharts will be used to illustrate how the main processor HP performs various types of access operations based on the access paths in Figures 8, 9A, 9B, and 10.

[0047] Please refer to Figure 8, which is a schematic diagram of the access path with the main processor HP as the main body when the main processor HP performs operations related to the flash memory circuit fmCKT through the flash memory circuit access interface. The cross-element access paths exchPATH_hp2strt, exchPATH_hp2sts, and exchPATH_hp2cmd are described in sequence below.

[0048] The cross-element access path exchPATH_hp2strt refers to the access path set by the main processor HP via the system bus SYS_BUS, the demultiplexer DMUX, and the internal bus SUBSYS_BUS, using the start register strtREG. The setting of the start register strtREG means that the agent processor AP can begin executing the flash memory access instruction fmaccCMD from the main processor HP.

[0049] The cross-element access path exchPATH_hp2sts refers to the access path through which the main processor HP reads the contents stored in the status register stsREG via the system bus SYS_BUS, the demultiplexer DMUX, and the internal bus SUBSYS_BUS. The contents stored in the status register stsREG represent the state of instruction execution, such as instruction execution in progress, instruction execution result error, instruction execution completed, etc.

[0050] The cross-element access path exchPATH_hp2cmd refers to the process by which the main processor HP first writes the access instructions to be executed on the flash memory circuit fmCKT to the instruction register cmdREG via the system bus SYS_BUS, the demultiplexer DMUX, and the internal bus SUBSYS_BUS. These access instructions include, but are not limited to, erasing operations on a specific sector or page in the flash memory array fmARR, or performing write and read tests.

[0051] Please refer to Figures 9A and 9B, which are schematic diagrams of the access paths related to the internal components of the flash memory circuit access interface. As mentioned above, the flash memory circuit access interface 29 includes: access instruction transfer circuit 2931, proxy processor AP, correction data register ipREG, non-volatile storage circuit 2935, volatile storage circuit 2937, and LPC interface circuit 2939. The access paths related to access instruction transfer circuit 2931 and proxy processor AP are described below.

[0052] As shown in Figure 9A, the access paths related to the internal components of the access instruction transfer circuit 2931 include: the interactive access path exchPATH_cplt2hp and the internal access path intPATH_strt2ap. The interactive access path exchPATH_cplt2hp lies between the completion register cpltREG and the main processor HP. The completion register cpltREG transmits the main processor interrupt signal intrSIG2hp to the main processor HP through the cross-component access path exchPATH_cplt2hp. The internal access path intPATH_strt2ap lies between the start register strtREG and the proxy processor AP. The start register strtREG transmits the proxy processor interrupt signal intrSIG2ap to the proxy processor AP through the internal access path intPATH_strt2ap. As explained above, the signals emitted from both the completion register cpltREG and the start register strtREG are interrupt signals. Table 1 compares the completion register cpltREG and the start register strtREG.

[0053] Table 1 Complete the temporary register cpltREG Start register strtREG Components used to set the register Agent processor AP main processor HP Used to set the access path of the temporary register. Internal access path intPATH_ap2cplt Cross-component access path exchPATH_hp2strt Interrupt signal generated by temporary register Main processor interrupt signal intrSIG2hp Agent processor interrupt signal intrSIG2ap Access path of interrupt signal generated by transfer register Interactive access path exchPATH_cplt2hp Internal access path intPATH_strt2ap Components used to receive interrupt signals main processor HP Agent processor AP Component used to clear the settings of the temporary register main processor HP Agent processor AP

[0054] As can be seen from Table 1, the settings of the completion register cpltREG and the start register strtREG are relative to each other. The completion register cpltREG is used to notify the master processor HP that the flash memory access instruction fmaccCMD has been completed. After receiving the master processor interrupt signal intrSIG2hp from the completion register cpltREG, the master processor HP will clear the settings in the completion register cpltREG to facilitate the next setting by the agent processor AP. On the other hand, the start register strtREG is used to notify the agent processor AP that the flash memory access instruction fmaccCMD can be started. After receiving the agent processor interrupt signal intrSIG2ap from the master processor HP, the agent processor AP will clear the settings in the start register strtREG to facilitate the next setting by the master processor HP.

[0055] As shown in Figure 9B, the access paths related to the agent processor AP include: cross-element access path exchPATH_ap2fm, internal access paths intPATH_ap2cmd, intPATH_ap2sts, intPATH_ap2cplt, intPATH_ap2ram, and intPATH_ap2rom. These access paths are described below.

[0056] The cross-element access path exchPATH_ap2fm refers to the transmission path between the agent processor AP and the flash memory circuit fmCKT, which transmits signals via the internal bus SUBSYS_BUS and the multiplexer MUX. The agent processor AP can use the cross-element access path exchPATH_ap2fm to issue access commands to the flash memory circuit fmCKT.

[0057] The internal access path intPATH_ap2cmd refers to the transmission path between the agent processor AP and the instruction register cmdREG, which transmits signals via the internal bus SUBSYS_BUS. Through the internal access path intPATH_ap2cmd, the agent processor AP can read access instructions stored in the instruction register cmdREG from the main processor HP.

[0058] The internal access path intPATH_ap2sts refers to the transmission path for transmitting signals via the internal bus SUBSYS_BUS between the agent processor AP and the status register stsREG. Through the internal access path intPATH_ap2sts, the agent processor AP can set the execution result of the access instruction (e.g., whether an error occurred) in the status register stsREG.

[0059] The internal access path intPATH_ap2cplt refers to the transmission path of signals transmitted via the internal bus SUBSYS_BUS between the agent processor AP and the completion register cpltREG. Through the internal access path intPATH_ap2cplts, the agent processor AP can set the completion register cpltREG to "1", indicating that the flash memory access instruction fmaccCMD executed by the agent processor AP on behalf of the main processor HP has been completed.

[0060] The internal access path intPATH_ap2ram refers to the transmission path between the agent processor AP and the volatile storage circuit 2937, which transmits signals via the internal bus SUBSYS_BUS and the multiplexer MUX. The agent processor AP can write data to the volatile storage circuit 2937 or read data from the volatile storage circuit 2937 via the internal access path intPATH_ap2ram.

[0061] The internal access path intPATH_ap2rom refers to the transmission path between the agent processor AP and the non-volatile storage circuit 2935, through the internal bus SUBSYS_BUS and the multiplexer MUX. The agent processor AP can write data to the non-volatile storage circuit 2935 or read data from the non-volatile storage circuit 2935 through the internal access path intPATH_ap2rom.

[0062] Table 2 summarizes the access paths in Figures 8, 9A, and 9B.

[0063] Table 2 Schematic Name of access path Components on the access path Figure 8 Cross-component access path exchPATH_hp2strt Main processor HP → System bus SYS_BUS → Internal bus SUBSYS_BUS → Start register strtREG Cross-component access path exchPATH_hp2sts Main processor HP → System bus SYS_BUS → Internal bus SUBSYS_BUS → Status register stsREG Cross-component access path exchPATH_hp2cmd Main processor HP → System bus SYS_BUS → Internal bus SUBSYS_BUS → Instruction register cmdREG Figure 9A Cross-component access path exchPATH_cplt2hp Complete the temporary register cpltREG à main processor HP Internal access path intPATH_strt2ap Start temporary register strtREGà agent processor AP Figure 9B Cross-component access path exchPATH_ap2fm Agent processor AP → Internal bus SUBSYS_BUS → Multiplexer MUX → Flash memory circuit fmCKT Internal access path intPATH_ap2cmd Agent processor AP → Internal bus SUBSYS_BUS → Instruction register cmdREG Internal access path intPATH_ap2sts Agent processor AP → Internal bus SUBSYS_BUS → Status register stsREG Internal access path intPATH_ap2cplt Agent processor AP → Internal bus SUBSYS_BUS → Completion register cpltREG Internal access path intPATH_ap2ram Agent processor AP → Internal bus SUBSYS_BUS → Volatile storage circuit 2937 Internal access path intPATH_ap2rom Agent processor AP → Internal bus SUBSYS_BUS → Non-volatile memory circuit 2935

[0064] Regarding the main processor HP in the electronic device 2, how to access the flash memory circuit fmCKT through the flash memory circuit access interface 29, thereby avoiding the situation where the main processor HP slows down due to waiting for the flash memory circuit fmCKT to respond, as is the case with conventional technology, please refer to the following explanation.

[0065] Based on the access paths illustrated in Figures 8, 9A, and 9B, Figures 10 and 11 will illustrate how the proxy processor AP is used as an access medium between the main processor HP and the flash memory circuit fmCKT, taking as an example how the proxy processor AP assists the main processor HP in performing page or sector erase and write operations on the flash memory circuit fmCKT.

[0066] Please refer to Figure 10, which is a flowchart illustrating how the flash memory circuit access interface assists the main processor HP in shortening the time required to wait for the flash memory circuit fmCKT to respond, using an erase operation as an example. Please also refer to Figures 9A, 9B, and 10.

[0067] First, the main processor HP issues an erase instruction ersCMD, which is transmitted to the instruction register cmdREG via the cross-element access path exchPATH_hp2cmd (step S101a). Then, the main processor HP sets the start register strtREG via the cross-element access path exchPATH_hp2Strt (step S103a).

[0068] After the start register strtREG is set, the agent processor interrupt signal intrSIG2ap is sent to the agent processor AP via the internal access path intPATH_strt2ap (step S105a).

[0069] After receiving the agent processor interrupt signal intrSIG2ap, the agent processor AP clears the settings in the start register strtREG via the internal access path intPATH_ap2strt (step S106a). Furthermore, the agent processor AP reads the erase instruction ersCMD from the instruction register cmdREG via the internal access path intPATH_ap2cmd (step S107a).

[0070] Next, the agent processor AP issues an erase instruction ersCMD (step S109a) to the flash memory circuit fmCKT via the cross-element access path exchPATH_ap2fm, in accordance with the control flow specified in the specification of the flash memory circuit fmCKT.

[0071] In practical applications, the control flow specified in the flash memory circuit fmCKT specifications may involve multiple steps and cannot be completed in a single step. According to the proxy processor AP of this disclosure, the erase instruction ersCMD transmitted by the main processor HP can be converted into a control flow conforming to the specifications of the flash memory circuit fmCKT, based on the control flow specified in the flash memory circuit fmCKT specifications. Since the main processor HP does not need to execute the control flow specified in the flash memory circuit fmCKT specifications itself, but rather it is executed by the proxy processor AP, the main processor HP retains performance in the control of other circuits. Because the instruction conversion process performed by the proxy processor AP to conform to the specifications of the flash memory circuit fmCKT is an application-specific change, it will not be detailed in this disclosure.

[0072] Next, the agent processor AP determines whether it has received a report from the flash memory controller fmCTL, indicating that the areas to be erased in the flash memory array fmARR have been erased (step S111a). If the result of step S111a is negative, the agent processor AP continues to wait for a report from the flash memory controller fmCTL (step S112a) and repeats the determination of step S111a. If the result of step S111a is positive, the agent processor AP writes the execution result (e.g., normal / error) of the erase instruction ersCMD to the status register stsREG via the internal access path intPATH_ap2sts (step S113a).

[0073] Next, the agent processor AP sets the completion register cpltREG via the internal access path intPATH_ap2cplt (step S115a). And, the completion register cpltREG sends the main processor interrupt signal intrSIG2hp to the main processor HP via the internal access path intPATH_strt2ap (step S117a).

[0074] After receiving the main processor interrupt signal intrSIG2hp, the main processor HP will read the contents of the status register stsREG via the cross-element access path exchPATH_hp2sts (step S118a). Furthermore, the main processor HP will clear the settings in the completion register cpltREG via the cross-element access path exchPATH_hp2cplt (step S119a).

[0075] Please refer to Figure 11, which is a flowchart illustrating how the flash memory circuit access interface assists the main processor in shortening the time required to wait for the flash memory circuit fmCKT to respond, taking a write operation as an example. Please also refer to Figures 9A, 9B, and 11.

[0076] First, the main processor HP issues a write instruction wrtCMD to the instruction register cmdREG via the cross-element access path exchPATH_hp2cmd (step S101c). Next, the main processor HP sets the start register strtREG via the cross-element access path exchPATH_hp2Strt (step S103c). After the start register strtREG is set, the proxy processor interrupt signal intrSIG2ap is issued (step S105c). The proxy processor interrupt signal intrSIG2ap is transmitted to the proxy processor AP via the internal access path intPATH_strt2ap.

[0077] After receiving the agent processor interrupt signal intrSIG2ap, the agent processor AP clears the settings in the start register strtREG via the internal access path intPATH_ap2strt (step S106c). Furthermore, the agent processor AP reads the write instruction wrtCMD from the instruction register cmdREG via the internal access path intPATH_ap2cmd (step S107c).

[0078] The agent processor AP issues a write command wrtCMD to the flash memory circuit fmCKT via the cross-element access path exchPATH_ap2fm (step S109c) according to the specifications of the flash memory circuit fmCKT. Thereafter, the agent processor AP determines whether it has received a response from the flash memory controller fmCTL indicating that the write command wrtCMD has been executed (step S111c).

[0079] If the judgment result of step S111c is negative, the agent processor AP continues to wait for the response from the flash memory controller fmCTL (step 112c) and repeats step S111c. If the judgment result of step S111c is positive, the agent processor AP writes the execution result (e.g., normal / error) of the write instruction wrtCMD to the status register stsREG via the internal access path intPATH_ap2sts (step S113c).

[0080] After the write instruction wrtCMD is completed, the agent processor AP sets the completion register cpltREG via the internal access path intPATH_ap2cplt (step 115c). After the completion register cpltREG is set by the agent processor AP, it sends a master processor interrupt signal intrSIG2hp to the master processor HP via the cross-element access path exchPATH_cplt2hp (step S117c). After the master processor HP receives the master processor interrupt signal intrSIG2hp transmitted by the completion register cpltREG, the master processor HP reads the contents of the status register stsREG previously set by the agent processor AP via the cross-element access path exchPATH_hp2sts to know whether the write instruction wrtCMD was successfully completed (step S118c); and the master processor HP clears the settings in the completion register cpltREG via the cross-element access path exchPATH_hp2cplt (step S119c).

[0081] As can be seen from Figures 10 and 11, when performing general erase and write operations, the configuration of the access instruction rerouting module cmdRRMdl can save the time required for the main processor HP to wait for the flash memory circuit fmCKT to respond. The access instruction rerouting module cmdRRMdl disclosed herein can be used with different types of flash memory circuits fmCKT. Among them, for the SONOS flash memory circuit fmCKT, whose control flow is inherently more complex, the benefits of using the access instruction rerouting module cmdRRMdl in conjunction with the flash memory circuit fmCKT are even more significant. According to the concept disclosed herein, in addition to performing the general erase and write operations shown in Figures 10 and 11, the access instruction rerouting module cmdRRMdl can also provide the main processor HP with the function of random writing to the flash memory array fmARR, as shown in Figures 12A and 12B.

[0082] Please refer to Figures 12A and 12B, which are flowcharts showing how the access instruction redirection module cmdRMdl provides random writes to the main processor HP. The main processor HP issues a random write instruction rnwrtCMD, which is transmitted to the instruction register cmdREG via the cross-element access path exchPATH_hp2cmd (step S301). The main processor HP sets the start register strtREG via the cross-element access path exchPATH_hp2Strt (step S303).

[0083] After the start register strtREG is set by the main processor HP, an agent processor interrupt signal intrSIG2ap will be issued. The agent processor interrupt signal intrSIG2ap is transmitted to the agent processor AP via the internal access path intPATH_strt2ap (step S305).

[0084] After receiving the agent processor interrupt signal intrSIG2ap, the agent processor AP clears the settings previously set by the main processor HP in the start register strtREG via the internal access path intPATH_ap2strt. Furthermore, the agent processor AP reads the random write instruction rnwrtCMD written by the main processor HP in the instruction register cmdREG via the internal access path intPATH_ap2cmd (step S307).

[0085] The agent processor AP reads the data in the page containing the flash memory access address fmADDR in the flash memory array fmARR via the cross-element access path exchPATH_ap2fm, according to the flash memory access address fmADDR in the flash memory access instruction fmaccCMD (step S309). Furthermore, the agent processor AP copies all the data in the page containing the flash memory access address fmADDR read from the flash memory array fmARR to the volatile storage circuit 2937 via the internal access path intPATH_ap2ram (step S311).

[0086] The agent processor AP modifies the copy of the paging data in the volatile storage circuit 2937 according to the access data accDAT in the random write instruction rnwrtCMD (step S313).

[0087] Next, the proxy processor AP determines whether the main processor HP executes the random write instruction rnwrtCMD in batch mode (step S315). In short, a negative result in step S315 is suitable for situations where the main processor HP only wants to randomly write one byte of data. A positive result in step S315 means that the main processor HP can perform multiple random writes within a page space until the main processor HP no longer needs to write data to that page.

[0088] If the judgment result of step S315 is negative, the agent processor APAP will copy the modified page data to the volatile storage circuit 2937 via the internal access path intPATH_ap2ram and the cross-element access path exchPATH_ap2fm, and write it to the page to which the flash memory access address fmADDR belongs in the flash memory array fmARR (step S321).

[0089] On the other hand, if the determination result of step S315 is affirmative, the proxy processor AP, after receiving other data to be written to the same page from the main processor HP, modifies the copy of the page data in the volatile storage circuit 2937 (step S317). After step S317, the proxy processor AP will determine whether the main processor HP wants to continue writing other data in the same page (step S319). If the determination result of step S319 is negative, the proxy processor AP will execute step S321. If the determination result of step S319 is affirmative, the proxy processor AP will repeat step S317. Steps S317 and S319 will be repeated until the main processor HP no longer needs to write data to the same page.

[0090] After step S321, the agent processor AP writes the execution result of the random write instruction rnwrtCMD to the status register stsREG via the internal access path intPATH_ap2sts (step S323). Furthermore, the agent processor AP sets the completion register cpltREG via the internal access path intPATH_ap2cplt (step S325). In accordance with the settings of the agent processor AP, the completion register cpltREG sends a main processor interrupt signal intrSIG2hp to the main processor HP via the internal access path intPATH_strt2ap (step S327).

[0091] After receiving the main processor interrupt signal intrSIG2hp, the main processor HP learns that the proxy processor AP has completed the execution of the random write instruction rnwrtCMD. Therefore, the main processor HP will read the contents of the status register stsREG via the cross-element access path exchPATH_hp2sts to understand the execution result of the random write instruction rnwrtCMD (step S329). In addition, the main processor HP will clear the settings previously set by the proxy processor AP in the completion register cpltREG via the cross-element access path exchPATH_hp2cplt (step S331).

[0092] Summarizing the implementation in Figures 12A and 12B, it can be seen that the setting of the access instruction rerouting module cmdRMdl allows the main processor HP to temporarily store the data to be randomly written in the volatile storage circuit 2937. Because the volatile storage circuit 2937 has a fast access speed, the main processor HP can quickly modify the data in the pages of the volatile storage circuit 2937. Furthermore, after storing the data in the volatile storage circuit 2937, the main processor HP can continue to execute other control processes unrelated to the flash memory circuit fmCKT. Subsequently, the proxy processor AP executes the write process to the flash memory circuit fmCKT based on the page data in the volatile storage circuit 2937.

[0093] Since the write speed of the volatile storage circuit 2937 is much faster than that of the flash memory circuit fmCKT, once the main processor HP writes data to the volatile storage circuit 2937, the main processor HP does not need to wait for the slower flash memory circuit fmCKT to perform the write process, and can continue to perform other functions. In other words, with the assistance of the proxy processor AP, the volatile storage circuit 2937 can be regarded as a buffer or cache for the main processor HP to store data to the flash memory circuit fmCKT.

[0094] In addition to basic erase and write operations, the flash memory circuit access interface 29 can provide more advanced applications. For example, Figures 13 and 14 show an example of the flash memory circuit access interface 29 combined with the memory access permission partitioning method of the flash memory array fmARR, providing an example with access protection function.

[0095] According to the concept disclosed herein, the flash memory array fmARR can be divided into three types of memory access permission partitions based on different access permissions: general access area nmZONE, system reserved area resZONE, and access permission protection area protZONE. The purpose of the general access area nmZONE, system reserved area resZONE, and access permission protection area protZONE is briefly described below.

[0096] First, the general access area nmZONE represents storage space that can be used for writing, reading, and erasing without any restrictions. Second, the system reserved area resZONE is storage space that users are not allowed to modify. Third, the access protection area protZONE represents protected storage space. The agent processor AP can use methods such as password authentication to control whether the main processor HP can access data located in the access protection area protZONE.

[0097] According to the concept disclosed herein, the user can define how the storage space in the flash memory array fmARR is divided into regions with different access permissions. Based on the different access permissions of each region defined in the specifications, the main processor HP can access each region in the flash memory array fmARR in different ways.

[0098] Please refer to Figures 13A-13D, which are schematic diagrams illustrating the partitioning methods for memory access permissions that can be adopted by a flash memory array fmARR. According to the concept disclosed herein, the storage space in the flash memory array fmARR can be divided into areas with different access permissions according to the different attributes and uses of the stored data.

[0099] For ease of explanation, in Figures 13A-13D, white squares represent the general access area nmZONE, which has unrestricted access rights and can be freely accessed; squares with a diagonal grid background represent the system reserved area resZONE, which should not be accessed by the main processor HP; and squares with a dotted grid background represent the access protection area protZONE, where access rights can be selectively granted based on whether the main processor HP has passed password verification. The partitioning method in Figures 13A-13D is for illustrative purposes only. In actual applications, the partitioning method of memory access rights in the flash memory array fmARR is not limited to the examples in Figures 13A-13D.

[0100] In Figure 13A, it is assumed that the entire flash memory array fmARR is a general access area nmZONE. When using this partitioning method, the main processor HP can arbitrarily access the contents of the flash memory array fmARR. Therefore, the partitioning method in Figure 13A is the simplest.

[0101] In Figure 13B, assume that the flash memory array fmARR contains a system reserved area resZONE and an access control protected area protZONE. The proxy processor AP needs to determine whether the master processor HP has passed the access control verification. If the master processor HP fails to pass the access control verification mechanism of the proxy processor AP, the proxy processor AP will prohibit the master processor HP from accessing the flash memory array fmARR.

[0102] In Figure 13C, assume that the flash memory array fmARR includes a system reserved area resZONE, an access control protected area protZONE, and a general access area nmZONE. The proxy processor AP needs to determine the area to which the master processor HP's access operation belongs. If the access operation to be performed by the master processor HP corresponds to the general access area nmZONE, the proxy processor AP does not need to restrict it. On the other hand, if the access operation to be performed by the master processor HP corresponds to the access control protected area protZONE, the proxy processor AP needs to further verify the access rights of the master processor HP. If the master processor HP fails the access rights verification, the proxy processor AP will prohibit the master processor HP from accessing the access control protected area protZONE.

[0103] In Figure 13D, it is assumed that the flash memory array fmARR includes a system reserved area resZONE, access control protected areas protZONE1 and protZONE2, and general access areas nmZONE1 and nmZONE2. This diagram illustrates that the number of areas with different access rights in the flash memory array fmARR is unlimited, and the positions of the areas with different access rights can be staggered.

[0104] By dividing the flash memory array fmARR into areas corresponding to different access permissions, the flash memory circuit access interface 29 can provide a function to prevent the data in the access permission protection area protZONE from being accidentally deleted or written for the purpose of data protection. Furthermore, data that is not allowed to be accessed by the user is stored in the system reserved area resZONE.

[0105] If the main processor HP wants to delete data in the system reserved area resZONE and / or the access protection area protZONE, or write data to the system reserved area resZONE and / or the access protection area protZONE, the agent processor AP will first confirm whether the address of the data to be erased or written belongs to a page of the system reserved area resZONE and / or the access protection area protZONE.

[0106] If the data to be erased or written by the main processor HP belongs to the system reserved area resZONE, the agent processor AP will not perform the erase operation or the write operation. Alternatively, if the main processor HP wants to write data to the system reserved area resZONE, the agent processor AP will not perform the write operation. Furthermore, the agent processor AP can use the status register stsREG to notify the main processor HP that the erase operation or the write operation is invalid.

[0107] The difference between the system reserved area resZONE and the access protection area protZONE is that data stored in the system reserved area resZONE is not allowed to be erased or written; data stored in the access protection area protZONE can be erased or written under certain conditions. For example, the agent processor AP can verify whether the master processor HP can perform erase or write operations on the access protection area protZONE based on password authentication.

[0108] That is, the proxy processor AP can read the pre-stored authentication password dfltPIN from the system reserved area resZONE. Only when the input password inPIN provided by the master processor HP matches the pre-stored authentication password dfltPIN (inPIN=dfltPIN) will the proxy processor AP grant the master processor HP access to the protected area protZONE for erasure or write operations. Conversely, if the master processor HP fails to provide the input password inPIN, or if the input password inPIN provided by the master processor HP does not match the pre-stored authentication password dfltPIN (inPIN≠dfltPIN), the proxy processor AP will notify the master processor HP that the erasure or write operation is invalid. This disclosure does not elaborate on the application variations in this part.

[0109] The access protection zone (protZONE) is well-suited for storing the bootloader of electronic device 2. During normal operation of electronic device 2, the agent processor (AP) ensures that the bootloader stored in the access protection zone (protZONE) cannot be accessed arbitrarily. However, when the main processor (HP) needs to perform a system update or upgrade of electronic device 2, the agent processor (AP) determines whether to enable access permissions for the access protection zone (protZONE) based on a password verification comparison.

[0110] Please refer to Figures 14A-14C, which are flowcharts illustrating how the flash memory circuit access interface provides write protection for the flash memory circuit to prevent the main processor HP from performing accidental write operations and / or accidental erase operations. After the electronic device 2 is powered on, the agent processor AP first obtains the location (range) of the system reserved area resZONE and / or the access permission protection area protZONE in the flash memory array fmARR from the non-volatile storage circuit 2935 via the internal access path intPATH_ap2ram (step S401). Subsequently, the agent processor AP temporarily stores the location (range) of the system reserved area resZONE and / or the access permission protection area protZONE in the flash memory array fmARR in the volatile storage circuit 2937 via the internal access path intPATH_ap2ram (step S403).

[0111] Next, the proxy processor AP determines whether the main processor HP has issued a write command wrtCMD or an erase command ersCMD (step S404). If the determination result of step S404 is negative, the access command redirection module cmdRRMdl continues to wait for the main processor HP to issue a write command wrtCMD and / or an erase command ersCMD (step S405).

[0112] If the determination result of step S404 is affirmative, the main processor HP issues a write instruction wrtCMD and / or an erase instruction ersCMD to the instruction register cmdREG via the cross-electrode access path exchPATH_hp2cmd (step S406). Furthermore, the main processor HP sets the start register strtREG via the cross-electrode access path exchPATH_hp2strt (step S407).

[0113] After the start register strtREG is set by the main processor HP, an interrupt signal intrSIG2ap is sent to the proxy processor AP via the internal access path intPATH_strt2ap (step S409). After receiving the proxy processor interrupt signal intrSIG2ap, the proxy processor AP clears the setting in the start register strtREG via the internal access path intPATH_ap2strt (step S410). Furthermore, the proxy processor AP reads the write instruction wrtCMD and / or erase instruction ersCMD from the instruction register cmdREG via the internal access path intPATH_ap2cmd (step S411).

[0114] As can be seen from the foregoing description, the flash memory access instruction fmaccCMD issued by the main processor HP not only includes the write instruction wrtCMD and / or the erase instruction ersCMD, but also includes the flash memory access address fmADDR in the flash memory array fmARR to write the access data accDAT.

[0115] The proxy processor AP determines, based on the location (range) of the system reserved area resZONE and / or the access permission protection area protZONE temporarily stored in the volatile storage circuit 2937 in the flash memory array fmARR, whether the flash memory access address fmADDR received with the write instruction wrtCMD and / or erase instruction ersCMD belongs to the system reserved area resZONE and cannot be written to and / or erased (step S415).

[0116] If the judgment result of step S415 is positive, the agent processor AP sets the state stored in the state register stsREG to invalid operation via the internal access path intPATH_ap2sts (step S417). Next, the agent processor AP completes the setting of the register cpltREG via the internal access path intPATH_ap2cplt (step S419). After the register cpltREG is set by the agent processor AP, it will send the main processor interrupt signal intrSIG2hp to the main processor HP via the internal access path intPATH_strt2ap (step S421). After receiving the main processor interrupt signal intrSIG2hp, the main processor HP reads the contents of the state register stsREG via the cross-element access path exchPATH_hp2sts, thereby knowing that the write instruction wrtCMD and / or the erase instruction ersCMD cannot be executed (step S423).

[0117] On the other hand, if the determination result of step S415 is positive, the agent processor AP further determines whether the flash memory access address fmADDR received by the write instruction wrtCMD and / or erase instruction ersCMD belongs to the access permission protection area protZONE (step S427).

[0118] If the determination result of step S427 is negative, it means that the flash memory access address fmADDR received by the write instruction wrtCMD and / or erase instruction ersCMD belongs to the general access area nmZONE. At this time, the agent processor AP issues the write instruction wrtCMD and / or erase instruction ersCMD to the flash memory circuit fmCKT via the cross-element access path exchPATH_ap2fm according to the control flow specified in the flash memory circuit fmCKT's datasheet (step S433). Next, the agent processor AP determines whether it has received a response from the flash memory controller fmCTL that the write instruction wrtCMD and / or erase instruction ersCMD have been executed (step S435).

[0119] If the judgment result of step S435 is negative, the agent processor AP continues to wait for the response from the flash memory controller fmCTL (step S437) and repeats step S435. On the other hand, if the judgment result of step S435 is positive, the agent processor AP knows that the access instruction has been completed. At this time, the agent processor AP writes the execution result of the write instruction wrtCMD and / or the erase instruction ersCMD to the status register stsREG via the internal access path intPATH_ap2sts (step S439). Furthermore, the agent processor AP sets the completion register cpltREG via the internal access path intPATH_ap2cplt (step S441).

[0120] After the temporary register cpltREG is set by the proxy processor AP, it will send a main processor interrupt signal intrSIG2hp to the main processor HP via the internal access path intPATH_strt2ap (step S443). After receiving the main processor interrupt signal intrSIG2hp, the main processor HP reads the contents of the status temporary register stsREG via the cross-element access path exchPATH_hp2sts to know the execution result after the proxy processor AP executes the write instruction wrtCMD and / or erase instruction ersCMD on its behalf (step S445).

[0121] After steps S423 and S445 are completed, the main processor HP clears the settings in the temporary register cpltREG via the cross-element access path exchPATH_hp2cplt (step S425).

[0122] On the other hand, if the judgment result of step S427 is positive, it means that the flash memory access address fmADDR received by the write instruction wrtCMD and / or erase instruction ersCMD belongs to the access protection area protZONE. At this time, the agent processor AP and the autonomous processor HP receive the input password inPIN (step S429). Furthermore, the agent processor AP compares the input password inPIN received from the main processor HP with the pre-stored verification password dfltPIN (step S431). If the judgment result of step S431 is negative, then step S417 is executed. Conversely, if the judgment result of step S431 is positive, then step S433 is executed.

[0123] In practical applications, the write protection function provided by the flash memory circuit access interface 29 for the access permission protection area protZONE can be applied to protect the boot loader of the electronic device 2. The boot loader is a piece of code stored at the starting address of the flash memory, responsible for guiding the boot process of the electronic device 2 or providing system code updates for the electronic device 2. Unless the electronic device 2 needs to update the boot loader version, under normal circumstances, once the boot loader code of the electronic device 2 is written and / or erased, the electronic device 2 will not be able to operate normally. Therefore, the flash memory circuit access interface 29 can protect the boot loader using the flow shown in Figures 14A to 14C.

[0124] For this type of application, the agent processor AP can pre-store the authentication password dfltPIN for the access protection zone protZONE in the system reserved area resZONE. When the main processor HP needs to write data to the access protection zone protZONE or erase data in the access protection zone protZONE, the agent processor AP retrieves the authentication password from the access protection zone protZONE.

[0125] When the input password inPIN transmitted by the main processor HP matches the verification password dfltPIN obtained by the proxy processor AP from the access protection zone protZONE, the proxy processor AP grants the main processor HP the permission to write to or erase the access protection zone protZONE. How the proxy processor AP coordinates the access permissions of the system reserved zone resZONE, the access protection zone protZONE, and the general access zone nmZONE to provide various application-specific protection functions for the flash memory array fmARR can be derived by modifying the flow diagrams 14A-14C, and will not be detailed in this disclosure.

[0126] In the flash memory circuit access interface 29, a non-volatile storage circuit 2935 can also be used to store settings related to access permissions, so that the agent processor AP can provide more flexibility and advanced applications. For example, a set of access identification codes is stored in the non-volatile storage circuit 2935, and the agent processor AP uses this set of access identification codes to determine whether the main processor HP can modify all or part of the contents of the flash memory circuit fmCKT. When the user of the operating electronic device 2 wants to modify the data stored in the system reserved area resZONE in the flash memory circuit fmCKT, the agent processor AP can request the main processor HP to send an identification code. Furthermore, the agent processor AP determines whether the user has the permission to modify the data based on the comparison result between the identification code sent by the main processor HP and the pre-stored access identification code. This part regarding application changes will not be detailed in this disclosure.

[0127] According to the concept disclosed herein, the access instruction rerouting module cmdRRMdl can not only serve as a communication medium between the main processor HP and the flash memory circuit fmCKT, but can also be used with the test equipment TM to test the function of the flash memory array fmARR. Figures 15-20 illustrate that in practical applications, the access instruction rerouting module cmdRRMdl can also be used with the test equipment TM to test the function of the flash memory array fmARR.

[0128] Please refer to Figure 15, which is a schematic diagram of the test instrument TM accessing the flash memory circuit via the flash memory circuit access interface. As shown by the dashed arrow AR_tstNarc, the test instrument TM can first transmit the test command to the access command redirection module cmdRRMdl via the system bus SYS_BUS and the demultiplexer DMUX. After the test instrument TM transmits the test command to the access command redirection module cmdRRMdl, it can be used to test the flash memory circuit fmCKT in other flash memory modules 22.

[0129] The access instruction rerouting module cmdRRMdl can execute test instructions and test programs issued by the test equipment TM. While the test equipment TM is testing the flash memory circuit fmCKT in other flash memory modules 22, the access instruction rerouting module cmdRRMdl, through the multiplexer MUX and the flash memory controller fmCTL, executes the test instructions and test programs issued by the test equipment TM on behalf of the test equipment TM on the flash memory array fmARR, as shown by the dashed arrow AR_arcNfm'.

[0130] Please refer to Figure 16A, which is a schematic diagram of the test access path starting from the test machine TM when the agent processor AP is used in conjunction with the test machine TM. The access paths related to the operation of the test machine TM include: the internal access path intPATH_strt2ap, and the test access paths tstPATH_tm2cmd, tstPATH_tm2sts, tstPATH_tm2strt, and tstPATH_tm2ram.

[0131] The test access path tstPATH_tm2cmd refers to the access path through which test instructions are written to the instruction register cmdREG after being transmitted from the test machine TM via the LPC interface circuit 2939 and the internal bus SUBSYS_BUS.

[0132] The test access path tstPATH_tm2sts refers to the access path that reads the status register stsREG after being transmitted from the test machine TM via the LPC interface circuit 2939 and the internal bus SUBSYS_BUS.

[0133] The test access path tstPATH_tm2strt refers to the access path of the start register strtREG set by the LPC interface circuit 2939 and the internal bus SUBSYS_BUS after it is transmitted from the test machine TM.

[0134] The test access path tstPATH_tm2ram refers to the access path through which test data is transmitted from the test machine TM to the volatile storage circuit 2937 via the LPC interface circuit 2939 and the internal bus SUBSYS_BUS.

[0135] Please refer to Figure 16B, which is a schematic diagram of the access path starting from the agent processor AP when used with the test machine TM. Please also refer to Figures 9B and 16B. Since Figure 16B is largely similar to Figure 9B, the various paths in Figure 16B will not be described in detail here. The difference between Figures 9B and 16B is that in Figure 16B, no internal access path intPATH_ap2cplt is provided between the agent processor AP and the completion register cpltREG.

[0136] Table 3 summarizes the access paths in Figures 16A and 16B.

[0137] Table 3 Schematic Name of access path Components on the access path Figure 16A Internal access path intPATH_strt2ap Start temporary register strtREGà agent processor AP Test access path tstPATH_tm2cmd Test bench TM → LPC interface circuit 2939 → Internal bus SUBSYS_BUS → Instruction register cmdREG Test access path tstPATH_tm2sts Test bench TM → LPC interface circuit 2939 → Internal bus SUBSYS_BUS → Status register stsREG Test access path tstPATH_tm2strt Test bench TM → LPC interface circuit 2939 → Internal bus SUBSYS_BUS → Start register strtREG Test access path tstPATH_tm2ram Test instrument TM → LPC interface circuit 2939 → Internal bus SUBSYS_BUS → Volatile storage circuit 2937 Figure 16B Internal access path intPATH_ap2cmd Agent processor AP → Internal bus SUBSYS_BUS → Instruction register cmdREG Internal access path intPATH_ap2sts Agent processor AP → Internal bus SUBSYS_BUS → Status register stsREG Internal access path intPATH_ap2ram Agent processor AP → Internal bus SUBSYS_BUS → Volatile storage circuit 2937 Internal access path intPATH_ap2rom Agent processor AP → Internal bus SUBSYS_BUS → Non-volatile memory circuit 2935 Cross-component access path exchPATH_ap2fm Agent processor AP → Internal bus SUBSYS_BUS → Multiplexer MUX → Flash memory circuit fmCKT

[0138] Based on the access paths shown in Figures 16A and 16B, the proxy processor AP can be paired with a test instrument TM to perform flexible and diverse tests on the flash memory circuit fmCKT. The following disclosure will provide three methods for testing the flash memory circuit fmCKT using the proxy processor AP and the test instrument TM. In practical applications, the methods for testing the flash memory circuit fmCKT using the proxy processor AP and the test instrument TM are not limited to the examples given here.

[0139] The first method is to use the agent processor AP in conjunction with the test machine TM to perform write and read tests based on the preset test data pattern (see the explanation of Figures 17A and 17B).

[0140] The second method is to store the pre-stored test program tstPGM in the flash memory array fmARR, and then execute the pre-stored test program tstPGM with the proxy processor AP, thereby sharing the load of the test machine TM (see the description of Figures 18 and 19).

[0141] The third method involves the test instrument TM storing the extended test program extTstOGN in the volatile storage circuit 2937, and then using the proxy processor AP in conjunction with the test instrument TM to execute the extended test program extTstOGN. This method allows the test instrument TM to perform functional testing on the flash memory circuit fmCKT in a more flexible manner.

[0142] Please refer to Figures 17A and 17B, which are flowcharts showing the writing and reading tests of the testing data pattern TstDAT performed by the agent processor AP in conjunction with the test instrument TM. In this disclosure, the testing data pattern TstDAT refers to a data format arranged according to a specific rule. For example, a data format consisting entirely of "1", a data format consisting entirely of "0", or a data format with alternating "0 / 1" characters, etc.

[0143] The test machine TM sends a data pattern testing command ptnTstCMD to the instruction register cmdREG via the test access path tstPATH_tm2cmd (step S701). The test machine TM sets the start register strtREG via the test access path tstPATH_tm2strt (step S703). After the start register strtREG is set by the test machine TM, it sends an interrupt signal intrSIG2ap to the agent processor AP via the internal access path intPATH_strt2ap (step S705).

[0144] After receiving the agent processor interrupt signal intrSIG2ap, the agent processor AP clears the settings in the start register strtREG via the internal access path intPATH_ap2Strt (step S706). Furthermore, the agent processor AP reads the data type test instruction ptnTstCMD previously set in the instruction register cmdREG by the test machine TM via the internal access path intPATH_ap2cmd (step S707).

[0145] After receiving the data sample test command ptnTstCMD, the agent processor AP will read the preset test data sample dfltTstDAT stored in the non-volatile storage circuit 2935 via the internal access path intPATH_ap2rom. In actual applications, the format of the preset test data sample dfltTstDAT is not limited. Furthermore, the non-volatile storage circuit 2935 can provide multiple sets of preset test data samples dfltTstDAT for the test equipment TM and / or agent processor AP to choose from.

[0146] The agent processor AP issues a data sample test command ptnTstCMD to the flash memory circuit fmCKT via the cross-element access path exchPATH_ap2fm (step S709). Step S709 further includes the following steps: the agent processor AP repeatedly writes the preset test data sample dfltTstDAT to the flash memory array fmARR via the cross-element access path exchPATH_ap2fm (step S709a); and the agent processor AP reads the preset test data sample dfltTstDAT stored in the flash memory array fmARR via the cross-element access path exchPATH_ap2fm (step S709c). For ease of explanation, the result of the agent processor AP reading the preset test data sample from the flash memory array fmARR via the cross-element access path exchPATH_ap2fm is represented here as the read data wrTstDAT after the write-read test.

[0147] Next, the proxy processor AP compares the preset test data sample dfltTstDAT with the read data wrTstDAT after the write-read test (step S711). If the proxy processor AP determines that the preset test data sample dfltTstDAT is completely consistent with the read data wrTstDAT after the write-read test read from the flash memory array fmARR, it means that the write and read functions of the flash memory array fmARR are normal. In other words, the execution result of the data sample test instruction ptnTstCMD is normal (step S715). On the other hand, if the proxy processor AP determines that the preset test data sample dfltTstDAT read from the non-volatile storage circuit 2935 is inconsistent with the read data wrTstDAT after the write-read test read from the flash memory array fmARR, it means that the write and read functions of the flash memory array fmARR are missing. In other words, the execution result of the data sample test instruction ptnTstCMD is abnormal (step S713).

[0148] After steps S713 and S715, the agent processor AP writes the execution result of the data type test instruction ptnTstCMD to the status register stsREG via the internal access path intPATH_ap2sts (step S717). The test machine TM polls the status register stsREG via the test access path tstPATH_tm2sts. That is, the test machine TM checks the status register stsREG at regular intervals to see if the status has been updated, thereby confirming the execution result of the agent processor AP after executing the test instruction tstCMD (step S719).

[0149] The test equipment TM determines whether the content of the status register stsREG indicates that the agent processor AP has completed the data type test instruction ptnTstCMD (step S721). For example, if the status register stsREG was originally "0", after the agent processor AP executes the test instruction tstCMD, the agent processor AP sets the status register stsREG to "1". In this way, the test equipment TM can know that the content of the status register stsREG has been set to "1" when it polls the status register stsREG. In this way, the test equipment TM can know that the agent processor AP has completed the data type test instruction ptnTstCMD. If the determination result of step S721 is positive, the process ends. If the determination result of step S721 is negative, step S719 is repeated.

[0150] Please refer to Figure 18, which is a flowchart of storing the pre-stored test program tstPGM in a non-volatile storage circuit, and then executing the pre-stored test program tstPGM by the proxy processor AP, thereby sharing the load of the test machine TM.

[0151] First, the test machine TM stores the pre-stored test program execution instruction pgmTstCMD into the instruction register cmdREG via the test access path tstPATH_tm2cmd (step S801). The test machine TM sets the start register strtREG via the test access path tstPATH_tm2strt (step S803).

[0152] The start register strtREG sends an interrupt signal intrSIG2ap to the agent processor AP via the internal access path intPATH_strt2ap (step S805). After receiving the interrupt signal intrSIG2ap, the agent processor AP clears the settings in the start register strtREG via the internal access path intPATH_ap2strt (step S806). The agent processor AP reads the pre-stored test program in the instruction register cmdREG via the internal access path intPATH_ap2cmd and executes the instruction pgmTstCMD (step S807).

[0153] After receiving the pre-stored test program execution instruction pgmTstCMD, the agent processor AP learns that the test machine TM needs the agent processor AP to assist in executing the pre-stored test program execution instruction pgmTstCMD. Therefore, the agent processor AP loads the pre-stored test program tstPGM stored in the non-volatile storage circuit 2935 via the internal access path intPATH_ap2rom (step S809).

[0154] The proxy processor AP executes the pre-stored test program tstPGM obtained from the non-volatile storage circuit 2935 on the flash memory circuit fmCKT via the cross-element access path exchPATH_ap2fm (step S811). Furthermore, the proxy processor AP writes the execution result of the pre-stored test program tstPGM to the status register stsREG via the internal access path intPATH_ap2sts (step S813).

[0155] The test instrument TM reads the status register stsREG in a round-robin fashion via the test access path tstPATH_tm2sts to confirm whether the pre-stored test program tstPGM has been executed, and the execution result generated by the agent processor AP after executing the pre-stored test program tstPGM (step S815). Based on the reading results of the status register stsREG in a round-robin fashion, the test instrument TM determines whether the status register stsREG represents that the pre-stored test program tstPGM has been executed (step S817).

[0156] If the judgment result of step S817 is negative, the agent processor AP repeats step S813. On the other hand, if the judgment result of step S817 is positive, the test instrument TM reads the test result of the pre-stored test program tstPGM on the flash memory circuit fmCKT via the test access path tstPATH_tm2sts (step S819). That is, the test instrument TM only needs to read the contents of the state register stsREG to know the test result of the pre-stored test program tstPGM on the flash memory array fmARR.

[0157] The process in Figure 18 is equivalent to using the proxy processor AP to replace the functional testing process of the flash memory array fmARR that should originally be performed by the test equipment TM. Therefore, the functional testing process of the flash memory array fmARR by the test equipment TM can be greatly simplified, and the test equipment TM can also test multiple flash memory arrays fmARR simultaneously, thereby improving the overall testing efficiency of the test equipment TM.

[0158] Figures 17 and 18 illustrate the method by which the test instrument TM first stores the preset test data sample dfltTstDAT and the pre-stored test program tstPGM in the non-volatile storage circuit 2935, and then the proxy processor AP assists the test instrument TM in testing the flash memory circuit fmCKT. Therefore, it can be seen that the proxy processor AP according to the present disclosure can indeed reduce the loading burden on the test instrument TM when testing the flash memory circuit fmCKT.

[0159] In practical applications, the test equipment TM may be unable to pre-store all test programs in the non-volatile storage circuit 2935 due to factors such as limited storage space of the non-volatile storage circuit 2935 and the need to add new test items to the flash memory circuit fmCKT. To address this, the proxy processor AP disclosed herein can be further used in conjunction with the address register addrREG and the volatile storage circuit 2937, allowing the proxy processor AP to assist the test equipment TM in executing the newly added extended test program extTstPGM. Figures 19 and 20 will illustrate how the proxy processor AP, in conjunction with the address register addrREG, assists the test equipment TM in executing the extended test program extTstPGM.

[0160] Please refer to Figure 19, which is a schematic diagram of the internal access path intPATH_ap2addr from the agent processor AP to the address register addrREG. The internal access path intPATH_ap2addr refers to the transmission path from the agent processor AP, through the internal bus SUBSYS_BUS to the address register addrREG.

[0161] Please refer to Figures 20A and 20B, which are flowcharts showing how the test equipment TM stores the extended test program extTstOGN in the volatile storage circuit, and then uses the proxy processor AP to execute the extended test program extTstPGM in conjunction with the test equipment TM, thereby sharing the load of the test equipment TM on the functional testing of the flash memory circuit fmCKT.

[0162] The test instrument TM loads the extended test program extTstPGM into the volatile storage circuit 2937 via the test access path tstPATH_tm2ram. Here, the address at which the extended test program extTstPGM is loaded into the volatile storage circuit 2937 is defined as the test program load address tstPGM_ldADDR (step S901). The test instrument TM fills the address register addrREG with the test program load address tstPGM_ldADDR (step S903).

[0163] Next, the test machine TM stores the extended test instruction extTstCMD into the instruction register cmdREG via the test access path tstPATH_tm2cmd (step S905). Furthermore, the test machine TM sets the start register strtREG via the test access path tstPATH_tm2Strt (step S907).

[0164] After the start register strtREG is set by the test equipment TM, the agent processor interrupt signal intrSIG2ap is sent to the agent processor AP via the internal access path intPATH_strt2ap (step S909). Furthermore, the agent processor AP clears the setting of the start register strtREG via the internal access path intPATH_ap2intr (step S910).

[0165] The agent processor AP reads the extended test instruction extTstCMD from the instruction register cmdREG via the internal access path intPATH_ap2cmd (step S911). Based on the extended test instruction extTstCMD, the agent processor AP retrieves the test program and loads it at address tstPGM_ldADDR via the address register addrREG via the internal access path intPATH_ap2add (step S913). The agent processor AP executes the extended test program extTstPGM on the volatile memory circuit 2937 via the internal access path intPATH_ap2ram (step S915).

[0166] The agent processor AP writes the execution result of the extended test program extTstPGM to the status register stsREG via the internal access path intPATH_ap2sts (step S917). The test machine TM polls the status register stsREG via the test access path tstPATH_tm2sts to confirm the execution result of the extended test program extTstPGM (step S919).

[0167] Next, the test equipment TM determines whether the content stored in the status register stsREG represents confirmation that the extended test program extTstPGM has been executed (step S921). If the determination result of step S921 is negative, step S919 is repeated. If the determination result of step S921 is positive, the test equipment TM clears the setting of the status register stsREG through the test access path tstPATH_tm2sts (step S923).

[0168] When testing using the method shown in Figures 15-20, because the LPC interface circuit 2939 requires fewer pins and the proxy processor AP offloads the testing work that the test equipment TM needs to perform, the test equipment TM can save the time required to test the flash memory array fmARR. In other words, the setting of the access instruction rerouting module cmdRRMdl can significantly improve the efficiency of the test equipment TM in testing the flash memory array fmARR.

[0169] According to the concept disclosed herein, when the access instruction rerouting module cmdRRMdl is used with the test equipment TM, it can also provide a read protection function to determine whether the test equipment TM should test the flash memory array fmARR, based on the architecture of the access permission protection zone protZONE set in the flash memory array fmARR as illustrated in Figures 13 and 14. That is, the access instruction rerouting module cmdRRMdl can determine whether the test equipment TM should be allowed or prohibited from testing the flash memory array fmARR based on the settings in the access permission protection zone protZONE.

[0170] For example, the manufacturer of electronic device 2 may pre-define a specific protection bit, protBIT, for the proxy processor AP to read in the access protection area protZONE of the flash memory array fmARR. When this specific protection bit protBIT is set to "1", the proxy processor AP prevents the test instrument TM from testing the functionality of the flash memory array fmARR. That is, when the proxy processor AP reads the access protection area protZONE of the flash memory array fmARR via the cross-element access path exchPATH_ap2fm, if it finds that the protection bit protBIT is set to "1", the proxy processor AP will refuse the test instrument TM from executing the process shown in Figures 15-18.

[0171] According to the concept disclosed herein, both the main processor HP and the test instrument TM may update the protection bit protBIT through the proxy processor AP. To ensure that the protection bit protBIT is not updated from "1" to "0" by the main processor HP or the test instrument TM, thereby allowing the test instrument TM to read the data or code in the flash memory array fmARR, this disclosure further provides related protection mechanisms. For example, when the proxy processor AP reads the access permission protection area protZONE of the flash memory array fmARR via the cross-element access path exchPATH_ap2fm, if it finds that the setting of the protection bit protBIT has been updated from the original "1" to "0", the proxy processor AP will automatically clear the data or code in the flash memory array fmARR. Furthermore, the proxy processor AP only enables the test instrument TM to test the flash memory array fmARR after completely clearing the data or code in the flash memory array fmARR.

[0172] By designing a specific protection bit, protBIT, within the protZONE access control area of ​​the flash memory array fmARR, it can be ensured that the data stored in the flash memory array fmARR can only be read by the main processor HP. Once the test equipment TM attempts to test the flash memory array fmARR, all data stored in the flash memory array fmARR will be pre-deleted by the proxy processor AP. In this way, the proxy processor AP can provide read protection for the data or code stored in the flash memory array fmARR. The applications and variations in this section are not limited to the examples given here.

[0173] Next, Figures 21-23 will explain how this disclosure uses the settings of the access instruction rerouting module cmdRRMdl to allow the test equipment TM to store calibration parameters corresponding to the semiconductor silicon intellectual property circuit ipCKT in the flash memory circuit fmCKT. These calibration parameters corresponding to the semiconductor silicon intellectual property circuit ipCKT can be regarded as trimming data trimDAT used to fine-tune the relevant setting values ​​of the semiconductor silicon intellectual property circuit ipCKT, and after the electronic device 2 is powered on, the semiconductor silicon intellectual property circuit ipCKT is calibrated using this trimming data trimDAT. For ease of explanation, this disclosure assumes that the electronic device 2 contains K semiconductor silicon intellectual property circuit ipCKTs. When the electronic device 2 contains K semiconductor silicon intellectual property circuit ipCKTs, the access instruction transmission circuit 2931 contains K calibration data temporary registers ipREG. Each of the K correction data registers ipREG is used to store the K sets of trim data trimDAT corresponding to each of the K semiconductor silicon intellectual property circuits ipCKT. For example, the k-th correction data register ipREG is used to temporarily store the k-th set of trim data trimDAT corresponding to the k-th semiconductor silicon intellectual property circuit ipCKT. Here, K and k are both positive integers, and k≤K.

[0174] Please refer to Figure 21, which is a schematic diagram of the access paths related to the process of the test instrument TM in correcting the semiconductor silicon intellectual property circuit ipCKT after the flash memory circuit fmCKT stores the trim data trimDAT corresponding to the semiconductor silicon intellectual property circuit ipCKT. The cross-component access path exchPATH_ap2fm, the internal access path intPATH_ap2ram, and the test access path tstPATH_tm2ram listed in Figure 21 have been mentioned in the foregoing description and will not be repeated here.

[0175] In Figure 21, the internal access path intPATH_ap2ip refers to the path by which the agent processor AP sets the calibration data register ipREG via the internal bus SUBSYS_BUS. Furthermore, the cross-element access path exchPATH_ip2ip refers to the path by which the calibration data register ipREG transmits the trim data trimDAT to the semiconductor silicon intellectual property circuit ipCKT via physical wiring signals.

[0176] Please refer to Figure 22, which is a flowchart of the test instrument TM, equipped with the access instruction rerouting module cmdRRMdl, storing the trim data trimDAT corresponding to the semiconductor silicon intellectual property circuit ipCKT into the flash memory array fmARR. Please also refer to Figures 21 and 22.

[0177] The test instrument TM stores the trimming data trimDAT into the volatile storage circuit 2937 via the test access path tstPATH_tm2ram (step S201). The agent processor AP reads the trimming data trimDAT temporarily stored in the volatile storage circuit 2937 via the internal access path intPATH_ap2ram (step S203). The agent processor AP stores the trimming data trimDAT into the flash memory array fmARR via the cross-element access path exchPATH_ap2fm (step S205).

[0178] The test instrument TM can store the trim data trimDAT used for calibrating the silicon intellectual property circuit ipCKT into the flash memory array fmARR through the process shown in Figure 22. According to the concept disclosed herein, the trim data trimDAT stored in the flash memory array fmARR can provide a function similar to an electronic fuse (eFuse).

[0179] Please refer to Figure 23, which is a flowchart showing how, before the electronic device is powered on and performs normal operations, the access instruction redirection module cmdRRMdl is used to provide the fine-tuning data trimDAT stored in the flash memory circuit fmCKT to the semiconductor silicon intellectual property circuit ipCKT for parameter correction. Please also refer to Figures 21 and 23.

[0180] When the electronic device 2 is powered on, the agent processor AP first reads the trimming data trimDAT stored in the non-volatile storage circuit 2935 via the cross-element access path exchPATH_ap2fm (step S251). Then, the agent processor AP writes the trimming data trimDAT read from the non-volatile storage circuit 2935 to the correction data register ipREG via the internal access path intPATH_ap2ip (step S253). Furthermore, the correction data register ipREG transmits the trimming data trimDAT to the semiconductor silicon intellectual property circuit ipCKT via the cross-element access path exchPATH_ip2ip, so that the semiconductor silicon intellectual property circuit ipCKT can modify the setting parameters related to its activation according to the trimming data trimDAT, thereby achieving the effect of functional correction of the semiconductor silicon intellectual property circuit ipCKT (step S255). In this way, the main processor HP can perform system initialization of electronic device 2 (step S259) with the calibrated and properly functioning semiconductor silicon intellectual property circuit ipCKT (step S257).

[0181] As previously stated, this disclosure assumes that the electronic device 2 includes K semiconductor silicon intellectual property circuits (ipCKTs). Therefore, the test instrument TM must store K sets of trim data (trimDAT) corresponding to each of the K semiconductor silicon intellectual property circuits (ipCKTs) in the flash memory circuit fmCKT. Furthermore, the agent processor AP needs to read out the K sets of trim data (trimDAT) for each of the K semiconductor silicon intellectual property circuits (ipCKTs) to set the K correction data registers (ipREGs). The implementation details of this part are not provided in this disclosure.

[0182] As can be seen from Figure 23, when the electronic device 2 is powered on, the semiconductor silicon intellectual property circuit ipCKT can read the trim data trimDAT stored in the access instruction rerouting module cmdRRMdl, and use the trim data trimDAT to correct the internal setting parameters. In this way, the trim data trimDAT stored in the flash memory array fmARR can provide a function similar to an electronic fuse.

[0183] As can be seen from the foregoing description, by setting up the flash memory circuit access interface 29, a wide variety of functions can be provided in conjunction with the flash memory circuit fmCKT. For example, it can assist the main processor HP in performing control processes related to the flash memory circuit fmCKT, and assist the test equipment TM in performing or expanding test processes related to the flash memory circuit fmCKT. In addition, setting up the flash memory circuit access interface 29 can further reduce the cost of using electronic fuses. In conclusion, setting up the flash memory circuit access interface 29 can improve the efficiency of electronic devices that set up the flash memory circuit fmCKT, the efficiency and flexibility of functional testing, and also save hardware costs.

[0184] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0185] Figure 1 is a schematic diagram of a conventional electronic device; Figure 2 is a schematic diagram of an electronic device according to an embodiment of the present invention; Figure 3 is a schematic diagram of the composition of the flash memory access instruction fmaccCMD transmitted by the main processor HP; Figure 4 is a flowchart of the transmission path of the flash memory circuit access interface and the main processor HP according to the present invention, dynamically changing the access instruction code cmdTYPE and the flash memory access address fmADDR according to the type of access instruction issued by the main processor HP; Figure 5 is a schematic diagram of the main processor HP directly accessing the flash memory circuit fmCKT without going through the flash memory circuit access interface; Figure 6 is a schematic diagram of the main processor HP indirectly accessing the flash memory circuit fmCKT through the flash memory circuit access interface; Figure 7 is a block diagram of the flash memory circuit access interface. Figure 8 is a schematic diagram of the access path with the main processor HP as the main action subject when performing operations related to the flash memory circuit fmCKT through the flash memory circuit access interface; Figures 9A and 9B are schematic diagrams of the access paths related to the internal components of the flash memory circuit access interface; Figure 10 is a flowchart illustrating how the flash memory circuit access interface helps the main processor shorten the time required to wait for the flash memory circuit fmCKT to respond, taking an erase operation as an example; Figure 11 is a flowchart illustrating how the flash memory circuit access interface helps the main processor shorten the time required to wait for the flash memory circuit fmCKT to respond, taking a write operation as an example; Figures 12A and 12B are flowcharts illustrating how the access instruction redirection module cmdRRMdl provides random writing to the main processor HP; Figures 13A-13D are schematic diagrams illustrating the memory access permission partitioning methods that can be used by the flash memory array fmARR. Figures 14A-14C are flowcharts illustrating the write protection function of the flash memory circuit fmCKT provided by the flash memory circuit access interface to prevent the main processor HP from performing accidental write operations and / or accidental erase operations; Figure 15 is a schematic diagram of the test instrument TM accessing the flash memory circuit fmCKT via the flash memory circuit access interface; Figure 16A is a schematic diagram of the test access path starting from the test instrument TM when the proxy processor AP is used with the test instrument TM; Figure 16B is a schematic diagram of the test access path starting from the proxy processor AP when the proxy processor AP is used with the test instrument TM; Figures 17A and 17B are flowcharts illustrating the write and read tests of the testing data pattern performed by the proxy processor AP with the test instrument TM.Figure 18 is a flowchart illustrating how the pre-stored test program tstPGM is stored in a non-volatile memory circuit, and then executed by the proxy processor AP to alleviate the load on the test machine TM. Figure 19 is a schematic diagram illustrating how the proxy processor AP sets the address register addrREG through the internal access path intPATH_ap2addr. Figures 20A and 20B are flowcharts illustrating how the test machine TM stores the extended test program extTstOGN in a volatile memory circuit, and then executes the extended test program extTstOGN with the proxy processor AP, thereby alleviating the load on the test machine TM for functional testing of the flash memory circuit fmCKT. Figure 21 is a schematic diagram illustrating how the test machine TM stores the trim data trimDAT corresponding to the semiconductor silicon intellectual property circuit ipCKT in the flash memory circuit fmCKT by setting the access instruction redirection module cmdRRMdl. Figure 22 shows a flowchart illustrating how the test instrument TM, equipped with the access instruction rerouting module cmdRRMdl, stores the trim data trimDAT corresponding to the silicon intellectual property circuit ipCKT into the flash memory array fmARR; and Figure 23 shows a flowchart illustrating how, before the electronic device is powered on and performs normal operations, the access instruction rerouting module cmdRRMdl provides the trim data trimDAT stored in the flash memory circuit fmCKT to the silicon intellectual property circuit ipCKT for parameter calibration.

Claims

1. A flash memory circuit access interface for an electronic device, wherein the electronic device includes a main processor and a system bus, and the main processor transmits a flash memory access instruction including an access instruction code, a component identification address and a flash memory access address to the system bus, wherein the flash memory circuit access interface includes: a multiplexer electrically connected to a flash memory circuit; and an access instruction rerouting module including: an internal bus electrically connected to the main processor and the multiplexer; An access instruction transmission circuit is electrically connected to the internal bus; a proxy processor is electrically connected to the internal bus and the access instruction transmission circuit; and a demultiplexer is electrically connected to the system bus, the multiplexer, and the internal bus. After receiving the flash memory access instruction via the system bus, the demultiplexer transmits the access instruction code and the flash memory access address to one of the multiplexer and the internal bus based on the element identification address. When the demultiplexer transmits the access instruction code and the flash memory access address to the multiplexer, the main processor accesses the flash memory access address in the flash memory circuit according to the access instruction code. When the demultiplexer transmits the access instruction code and the flash memory access address to the internal bus, the access instruction transmission circuit receives the access instruction code via the internal bus, and the proxy processor accesses the flash memory access address in the flash memory circuit according to the access instruction code.

2. The flash memory circuit access interface as described in claim 1, wherein the access instruction transmission circuitry includes: an instruction register electrically connected to the internal bus, which receives and stores the access instruction code through the internal bus.

3. The flash memory circuit access interface as described in claim 2, wherein the access instruction transmission circuit further comprises: an initial register electrically connected to the internal bus and the proxy processor, which generates a proxy processor interrupt signal to the proxy processor in response to the settings of the main processor, wherein the proxy processor reads the access instruction code stored in the instruction register via the internal bus in response to the generation of the proxy processor interrupt signal.

4. The flash memory circuit access interface as described in claim 1, wherein the access instruction transmission circuitry includes: a status register electrically connected to the internal bus, wherein the proxy processor updates the contents of the status register via the internal bus as a result of accessing the flash memory circuit.

5. The flash memory circuit access interface as described in claim 4, wherein the access instruction transmission circuit further includes: a completion register electrically connected to the main processor and the internal bus, wherein the proxy processor sets the completion register through the internal bus after completing the access to the flash memory circuit, and the completion register generates a main processor interrupt signal transmitted to the main processor after being set.

6. The flash memory circuit access interface as described in claim 5, wherein the main processor reads the contents stored in the state register via the system bus, the demultiplexer and the internal bus after receiving the main processor interrupt signal.

7. The flash memory circuit access interface as described in claim 1, wherein the access instruction rerouting module further comprises: a non-volatile storage circuit electrically connected to the internal bus; and a volatile storage circuit electrically connected to the internal bus.

8. The flash memory circuit access interface as described in claim 1, wherein the access instruction rerouting module further comprises: a low pin number interface circuit electrically connected to the internal bus and selectively electrically connected to a test instrument, wherein the test instrument accesses the access instruction transmission circuit through the low pin number interface circuit and the internal bus.

9. The flash memory circuit access interface as described in claim 8, wherein the access instruction rerouting module further comprises: a non-volatile storage circuit electrically connected to the internal bus, wherein the test instrument stores a preset test data sample in the non-volatile storage circuit through the low pin number interface circuit and the internal bus, and the proxy processor, after reading the preset test data sample stored in the non-volatile storage circuit through the internal bus, performs a write-read test on the flash memory circuit according to the preset test data sample, wherein after the write-read test is completed, the proxy processor stores the execution result of the write-read test into the access instruction transmission circuit, and the test instrument reads the execution result of the write-read test stored by the proxy processor in the access instruction transmission circuit through the low pin number interface circuit and the internal bus.

10. The flash memory circuit access interface as described in claim 9, wherein when the proxy processor performs the write-read test on the flash memory circuit, the proxy processor first stores the preset test data sample read from the non-volatile storage circuit into the flash memory circuit, then reads the preset test data sample from the flash memory circuit, and the proxy processor compares whether the preset test data sample read from the non-volatile storage circuit is consistent with the preset test data sample read from the flash memory circuit.

11. The flash memory circuit access interface as described in claim 8, wherein the access instruction rerouting module further comprises: an volatile storage circuit electrically connected to the internal bus, wherein the test instrument system stores an extended test program for testing the flash memory circuit in the volatile storage circuit through the low pin number interface circuit and the internal bus, and the proxy processor executes the extended test program.

12. The flash memory circuit access interface as described in claim 11, wherein the access instruction transmission circuitry includes: an address register electrically connected to the internal bus, wherein the test instrument stores the expansion test program at a test program load address in the volatile memory circuit, and the test instrument stores the test program load address into the address register via the low pin number interface circuitry and the internal bus.

13. The flash memory circuit access interface as described in claim 12, wherein after the proxy processor reads the test program load address stored in the address register via the internal bus, the proxy processor accesses the test program load address of the volatile memory circuit via the internal bus and executes the extended test program.

14. The flash memory circuit access interface as described in claim 8, wherein the low pin count interface circuit is a serial peripheral interface or an internal integrated circuit, and the low pin count interface circuit is selectively electrically connected to the test equipment via a Joint Test Action Group (JTAG) cable.

15. The flash memory circuit access interface as described in claim 8, wherein the electronic device further comprises: K semiconductor silicon intellectual property circuits electrically connected to the main processor and the access instruction rerouting module, wherein the test instrument stores K sets of calibration parameters corresponding to the K semiconductor silicon intellectual property circuits in the flash memory circuit through the low pin number interface circuit, the proxy processor and the internal bus, wherein K is a positive integer.

16. The flash memory circuit access interface as described in claim 15, wherein the access instruction transmission circuit includes: K calibration data registers electrically connected to the internal bus and each of the K semiconductor silicon intellectual property circuits, wherein the proxy processor reads the K sets of calibration parameters from the flash memory circuit through the internal bus when the electronic device is powered on, and the proxy processor stores each of the K sets of calibration parameters into each of the K calibration data registers through the internal bus.

17. The flash memory circuit access interface as described in claim 16, wherein the kth calibration data register of the K calibration data registers transmits a kth set of calibration parameters of the K sets of calibration parameters to the kth semiconductor silicon intellectual property circuit of the K semiconductor silicon intellectual property circuits via a physical wiring signal, and the kth semiconductor silicon intellectual property circuit performs calibration according to the kth set of calibration parameters transmitted by the physical wiring signal when the electronic device is powered on, wherein k is a positive integer and k is less than or equal to K.

18. The flash memory circuit access interface as described in claim 1, wherein the flash memory circuit comprises: a flash memory controller electrically connected to the multiplexer, which receives the flash memory access address from the multiplexer; and a flash memory array electrically connected to the flash memory controller, wherein the flash memory controller performs an operation corresponding to the access instruction code at the flash memory access address in the flash memory array under the control of either the main processor or the proxy processor.

19. A flash memory module for an electronic device, wherein the electronic device includes a main processor and a system bus, and the main processor transmits a flash memory access instruction including an access instruction code, a component identification address and a flash memory access address to the system bus, wherein the flash memory module includes: a flash memory circuit; and a flash memory circuit access interface electrically connected to the system bus, including: a multiplexer electrically connected to the flash memory circuit; and an access instruction rerouting module, including: an internal bus electrically connected to the main processor and the multiplexer; An access instruction transmission circuit is electrically connected to the internal bus; a proxy processor is electrically connected to the internal bus and the access instruction transmission circuit; and a demultiplexer is electrically connected to the system bus, the multiplexer, and the internal bus. After receiving the flash memory access instruction via the system bus, the demultiplexer transmits the access instruction code and the flash memory access address to one of the multiplexer and the internal bus based on the element identification address. When the demultiplexer transmits the access instruction code and the flash memory access address to the multiplexer, the main processor accesses the flash memory access address in the flash memory circuit according to the access instruction code. When the demultiplexer transmits the access instruction code and the flash memory access address to the internal bus, the access instruction transmission circuit receives the access instruction code via the internal bus, and the proxy processor accesses the flash memory access address in the flash memory circuit according to the access instruction code.

20. An electronic device comprising: a system bus; a main processor electrically connected to the system bus, which transmits a flash memory access instruction including an access instruction code, a component identification address, and a flash memory access address to the system bus; and a flash memory module comprising: a flash memory circuit; and a flash memory circuit access interface electrically connected to the system bus, comprising: a multiplexer electrically connected to the flash memory circuit; and an access instruction rerouting module comprising: an internal bus electrically connected to the main processor and the multiplexer; An access instruction transmission circuit is electrically connected to the internal bus; a proxy processor is electrically connected to the internal bus and the access instruction transmission circuit; and a demultiplexer is electrically connected to the system bus, the multiplexer, and the internal bus. After receiving the flash memory access instruction via the system bus, the demultiplexer transmits the access instruction code and the flash memory access address to one of the multiplexer and the internal bus based on the element identification address. When the demultiplexer transmits the access instruction code and the flash memory access address, the main processor accesses the flash memory access address in the flash memory circuit according to the access instruction code. When the demultiplexer transmits the access instruction code and the flash memory access address to the internal bus... The access instruction transmission circuit receives the access instruction code via the internal bus, and the proxy processor accesses the flash memory access address in the flash memory circuit according to the access instruction code.

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