Memory management method, memory storage device and memory control circuit unit

Abstract

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a multi-stages programing on a plurality of physical units in a rewritable non-volatile memory module according to first data, wherein the multi-stages programing includes a first-stage programming and a second-stage programming; maintaining second data after the multi-stages programing is started and before the second-stage programming is finished, wherein the second data is generated by encoding the first data; and adjusting a read operation or a programming operation on at least one of the physical units according to the second data.

Description

Technical Field

[0001] This invention relates to a memory management method, a memory storage device, and a memory control circuit unit. Prior Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, to prevent the loss of incomplete data due to unexpected power outages during data writing, memory storage devices back up the data to be stored. If an unexpected power outage occurs during data writing, this backup data can be used to re-execute the write operation on the original data after the memory storage device is powered on again. However, as the amount of data written in each write operation increases, the amount of data that needs to be backed up also increases, leading to excessive consumption of system resources. Summary of the Invention

[0004] The present invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can improve the above-mentioned problems.

[0005] This invention provides a memory management method for a rewritable non-volatile memory module. The memory management method includes: performing multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; saving second data before starting the multi-stage programming and before the second-stage programming is completed, wherein the second data is generated by encoding the first data; and adjusting at least one of the read operations or programming operations of the plurality of physical units according to the second data.

[0006] In an exemplary embodiment of the present invention, the plurality of physical units belong to the same character line.

[0007] In an exemplary embodiment of the present invention, the plurality of entity units include at least an upper entity programming unit and a lower entity programming unit.

[0008] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming according to the second data.

[0009] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units according to the second data includes: after the first stage programming is completed, detecting an abnormal power failure event before the second stage programming is completed; and after the abnormal power failure event is recovered, adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage programming but have not yet completed the second stage programming according to the second data.

[0010] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of entity units in the rewritable nonvolatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming according to the grouping result.

[0011] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage programming but have not yet completed the second stage programming, according to the grouping result, includes: adjusting a first parameter for the read operation or the programming operation according to a first critical voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second critical voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0012] In an exemplary embodiment of the present invention, the step of adjusting the read operation or the programmed operation of at least one of the plurality of entity units according to the second data includes: adjusting at least one of the read voltage level, programmed voltage level and decoding parameters corresponding to at least one of the plurality of entity units according to the second data.

[0013] In an exemplary embodiment of the present invention, the memory management method further includes: generating the second data in response to an abnormal power outage event prior to the completion of the second stage programming.

[0014] In an exemplary embodiment of the present invention, the memory management method further includes: correcting, based on the second data, third data read from at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

[0015] In an exemplary embodiment of the present invention, the memory management method further includes: not saving the second data for the plurality of entity units that have completed the second stage of programming.

[0016] In an exemplary embodiment of the present invention, in the multi-stage programming performed on the plurality of entity units, the programming voltage level used for the first stage programming is different from the programming voltage level used for the second stage programming.

[0017] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; save second data before the multi-stage programming begins and the second-stage programming is completed, wherein the second data is generated by encoding the first data; and adjust a read operation or programming operation of at least one of the plurality of physical units according to the second data.

[0018] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of entity units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming according to the second data.

[0019] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: detecting an abnormal power failure event before the completion of the second stage programming after the first stage programming is completed; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage programming but have not yet completed the second stage programming according to the second data after the abnormal power failure event is recovered.

[0020] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming according to the grouping result.

[0021] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage programming but have not yet completed the second stage programming according to the grouping result includes: adjusting a first parameter for the read operation or the programming operation according to a first critical voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second critical voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0022] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the read operation or the programmed operation of at least one of the plurality of physical units according to the second data includes: adjusting at least one of the read voltage level, programmed voltage level and decoding parameters corresponding to at least one of the plurality of physical units according to the second data.

[0023] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to generate the second data in response to an abnormal power failure event prior to the completion of the second stage programming.

[0024] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: correct, based on the second data, the third data read from at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

[0025] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: not store the second data for the plurality of physical units that have completed the second stage of programming.

[0026] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to both the host interface and the memory interface. The memory management circuit is configured to: perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; save second data before the multi-stage programming begins and the second-stage programming is completed, wherein the second data is generated by encoding the first data; and adjust at least one of the read operations or programming operations of the plurality of physical units according to the second data.

[0027] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of entity units according to the second data includes: adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming according to the second data.

[0028] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: detecting an abnormal power failure event before the completion of the second stage programming after the first stage programming is completed; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage programming but have not yet completed the second stage programming according to the second data after the abnormal power failure event is recovered.

[0029] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of physical units according to the second data includes: grouping a plurality of memory cells corresponding to the plurality of physical units in the rewritable non-volatile memory module according to the second data; and adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming according to the grouping result.

[0030] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage programming but have not yet completed the second stage programming according to the grouping result includes: adjusting a first parameter for the read operation or the programming operation according to a first critical voltage distribution of a plurality of first memory cells belonging to a first group among the plurality of memory cells; and adjusting a second parameter for the read operation or the programming operation according to a second critical voltage distribution of a plurality of second memory cells belonging to a second group among the plurality of memory cells.

[0031] In an exemplary embodiment of the present invention, the operation of the memory management circuit to adjust the read operation or the programmed operation of at least one of the plurality of physical units according to the second data includes: adjusting at least one of the read voltage level, programmed voltage level and decoding parameters corresponding to at least one of the plurality of physical units according to the second data.

[0032] In an exemplary embodiment of the present invention, the memory management circuit is further configured to generate the second data in response to an abnormal power failure event prior to the completion of the second stage programming.

[0033] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: correct, based on the second data, a third data read from at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

[0034] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: not save the second data for the plurality of physical units that have completed the second stage of programming.

[0035] Based on the above, according to the first data, multi-stage programming can be performed on multiple physical units in a rewritable non-volatile memory module. Specifically, before the execution of the multi-stage programming begins and before the second stage of the multi-stage programming is completed, second data generated by encoding the first data can be saved. Subsequently, read operations or programming operations on at least one of the multiple physical units can be adjusted based on the second data. Therefore, compared to the conventional requirement of fully backing up the first data until the corresponding programming operation is completed, the present invention achieves the same or better data management and / or data recovery performance by saving the encoded second data. Simple Explanation of the Diagram

[0036] Figure 1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7A is a schematic diagram illustrating multi-stage programming of physical cells in a rewritable non-volatile memory module to store data, according to an exemplary embodiment of the present invention. Figure 7B is a schematic diagram illustrating the reading of data from a procedural entity unit according to an exemplary embodiment of the present invention. Figure 8 is a schematic diagram illustrating the encoding of first data to generate second data according to an exemplary embodiment of the present invention. Figure 9A is a schematic diagram illustrating the critical voltage distribution of a memory cell after a first-stage programming, according to an exemplary embodiment of the present invention. Figure 9B is a schematic diagram illustrating the critical voltage distribution of grouped memory cells according to an exemplary embodiment of the present invention. Figure 10 is a schematic diagram illustrating the adjustment of the reading voltage level according to an exemplary embodiment of the present invention. Figure 11 is a schematic diagram illustrating the adjustment of decoding parameters according to an exemplary embodiment of the present invention. Figure 12 is a schematic diagram illustrating the correction of erroneous bits based on second data according to an exemplary embodiment of the present invention. Figure 13 is a schematic diagram illustrating the interleaved programming of memory cells on multiple character lines according to an exemplary embodiment of the present invention. Figure 14 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Figure 15 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Implementation

[0037] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to allow the host system to write data to or read data from the memory storage device.

[0038] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention.

[0039] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0040] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0041] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0042] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0043] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0044] Figure 3 is a schematic diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0046] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0047] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0048] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0049] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0050] In one exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of lower physical programming units is greater than that of upper physical programming units, and / or the reliability of lower physical programming units is higher than that of upper physical programming units.

[0051] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0052] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to Figure 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0053] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0054] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0055] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in program code format in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0056] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit is used to issue an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0057] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0058] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0059] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0060] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0061] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0062] In one exemplary embodiment, the rewritable nonvolatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0063] Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to Figure 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0064] In one exemplary embodiment, an entity unit refers to a single entity programmable unit. In another exemplary embodiment, an entity unit may also refer to multiple entity programmable units.

[0065] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 can store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0066] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the storage area 601. In one exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logic addresses.

[0067] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0068] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0069] Figure 7A is a schematic diagram illustrating multi-stage programming of physical cells in a rewritable non-volatile memory module to store data, according to an exemplary embodiment of the present invention. Referring to Figure 7A, the horizontal axis represents the critical voltage of the memory cell, while the vertical axis represents the number of memory cells with a specific critical voltage. Furthermore, Figure 7A is illustrated using multi-stage programming based on a fourth-order memory cell (QLC) mode as an example, but the present invention is not limited thereto. In one exemplary embodiment, the multi-stage programming may also be performed based on a single-order memory cell (SLC) mode, a second-order memory cell (MLC) mode, a third-order memory cell (TLC) mode, or other modes, and the present invention is not limited thereto.

[0070] In one exemplary embodiment, it is assumed that before multi-stage programming of multiple physical units (also referred to as first physical units) located on a certain word line (also referred to as the first word line) to store data, the critical voltage distribution of the multiple memory cells belonging to the first physical unit may only include state 700. State 700 is also referred to as the erase state. For example, after performing an erase operation on the multiple memory cells belonging to the first physical unit, the critical voltage distribution of these memory cells may only include state 700.

[0071] In one exemplary embodiment, memory management circuitry 51 may send at least one write instruction sequence (also referred to as a first write instruction sequence) to rewritable non-volatile memory module 43 based on specific data (also referred to as first data). For example, the first data may be data to be stored from host system 11 and / or valid data collected from rewritable non-volatile memory module 43 through garbage collection (GC) operations. The first write instruction sequence may be used to instruct rewritable non-volatile memory module 43 to perform programmed operations on a first physical cell to store the first data.

[0072] In one exemplary embodiment, according to the first write instruction sequence, the rewritable non-volatile memory module 43 can perform a multi-stage programming operation on the first physical cell to store the first data. Taking FIG7A as an example, according to the first write instruction sequence, the rewritable non-volatile memory module 43 can first perform the first programming in the multi-stage programming of the first physical cell (also known as the first-stage programming) to roughly distribute the critical voltages of the multiple memory cells belonging to the first physical cell to the voltage range corresponding to states 701-716. It should be noted that even after the first-stage programming, the programming operation on the first physical cell (i.e., the multi-stage programming) is not yet complete (i.e., the first data has not yet been completely stored in the first physical cell).

[0073] After the first programming (i.e., the first-stage programming), the rewritable non-volatile memory module 43 can perform a second programming (also called the second-stage programming) in the multi-stage programming of the first physical cell to more precisely control the critical voltage of the multiple memory cells in states 701-716 within the voltage range corresponding to states 721-736. In particular, after the second-stage programming, the programming operation (i.e., the multi-stage programming) for the first physical cell can be considered complete (i.e., the first data has been completely stored in the first physical cell). In an exemplary embodiment, if the aforementioned programming operation (i.e., the multi-stage programming) for the first physical cell has been completed (i.e., the first data has been completely stored in the first physical cell), the first data cached in the rewritable non-volatile memory module 43 and / or buffer memory 55 can be removed.

[0074] In one exemplary embodiment, during the multi-stage programming performed on the first entity unit, the programming voltage level used for the first stage programming differs from the programming voltage level used for the second stage programming. Taking FIG7A as an example, the programming voltage level used for the first stage programming is used to raise the critical voltage of each memory cell to the voltage position corresponding to states 701-716. However, the programming voltage level used for the second stage programming is used to further raise or correct the critical voltage of each memory cell to the voltage position corresponding to states 721-736.

[0075] It should be noted that the exemplary embodiment in Figure 7A is illustrated using a 16:16 multistage programming pattern. However, in another exemplary embodiment, the aforementioned multistage programming can also employ an 8:16 or other types of multistage programming patterns, and this invention is not limited thereto.

[0076] In one exemplary embodiment, states 721-736 correspond to different bit combinations in a fourth-order memory cell (QLC) mode, namely “1111”, “1110”, “1100”, “1101”, “1001”, “0001”, “0101”, “0100”, “0110”, “0010”, “0000”, “1000”, “1010”, “1011”, “0011”, and “0111”. For example, assuming the threshold voltage of a memory cell belonging to the first entity unit is within the voltage range corresponding to state 722, it means that the data stored in this memory cell is “1110”. Or, assuming the threshold voltage of another memory cell belonging to the first entity unit is within the voltage range corresponding to state 734, it means that the data stored in this memory cell is “1011”, and so on. However, the bit combination corresponding to each of states 721-736 can also be adjusted according to practical needs, and the present invention does not limit it.

[0077] In one exemplary embodiment, among the 16 bit combinations described above, different bits in each bit combination belong to different entity units in the first entity unit. For example, in the 16 bit combinations described above, the first to fourth bits in each bit combination may belong to entity unit (L), entity unit (M), entity unit (U), and entity unit (T) in the first entity unit, respectively, as shown in FIG7A.

[0078] In one exemplary embodiment, two of entity units (L), (M), (U), and (T) can be considered as an upper and lower entity programmable unit. The names of entity units (L), (M), (U), and (T) can be determined or adjusted according to the adopted memory management specifications.

[0079] In other words, in the exemplary embodiment of Figure 7A, it is assumed that multiple memory cells located on the first character line can form the multiple first entity units (i.e., entity unit (L), entity unit (M), entity unit (U), and entity unit (T)). After performing the first-stage programming and the second-stage programming on these memory cells sequentially, the first data can be completely written into the multiple first entity units.

[0080] Figure 7B is a schematic diagram illustrating the reading of data from programmed physical units according to an exemplary embodiment of the present invention. Referring to Figure 7B, continuing from the exemplary embodiment of Figure 7A, for a first physical unit programmed in the second stage, the memory management circuit 51 can send at least one read instruction sequence (also referred to as the first read instruction sequence) to the rewritable non-volatile memory module 43. The first read instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to read data (i.e., first data) from the plurality of first physical units (i.e., physical unit (L), physical unit (M), physical unit (U), and physical unit (T)).

[0081] In one exemplary embodiment, according to a first read instruction sequence, the rewritable non-volatile memory module 43 can read data (i.e., first data) from the plurality of first physical units based on a read voltage group. For example, this read voltage group may include read voltage levels L(1)~L(3), M(1)~M(4), U(1)~U(4), and T(1)~T(4).

[0082] Read voltage levels L(1) to L(3) are used to read data belonging to entity cell (L) (also called first sub-data). For example, by applying read voltage levels L(1) to L(3) to multiple memory cells belonging to the first entity cell, the data belonging to entity cell (L) (i.e., the first sub-data) can be obtained. Read voltage levels M(1) to M(4) are used to read data belonging to entity cell (M) (also called second sub-data). For example, by applying read voltage levels M(1) to M(4) to multiple memory cells belonging to the first entity cell, the data belonging to entity cell (M) (i.e., the second sub-data) can be obtained. Read voltage levels U(1) to U(4) are used to read data belonging to entity cell (U) (also called third sub-data). For example, by applying read voltage levels U(1) to U(4) to multiple memory cells belonging to the first entity cell, the data belonging to entity cell (U) (i.e., the third sub-data) can be obtained. Furthermore, read voltage levels T(1) to T(4) are used to read data belonging to the entity cell (T) (also known as the fourth sub-data). For example, by applying read voltage levels T(1) to T(4) to multiple memory cells belonging to the first entity cell, data belonging to the entity cell (T) (i.e., the fourth sub-data) can be obtained.

[0083] In one exemplary embodiment, if the programming operation (i.e., multi-stage programming) for the first entity cell has not yet been completed (e.g., only the first stage programming is performed for the first entity cell and the second stage programming has not yet been performed), the data stored in the first entity cell (i.e., the first data) will have a high probability of not being read correctly subsequently. Taking Figure 7A as an example, if only the first stage programming has been performed, states 701 to 716 in the critical voltage distribution of multiple memory cells belonging to the first entity cell will overlap significantly with each other. In this case, if the read voltage group of Figure 7B is used directly to read these memory cells, it is easy to cause data reading failure due to reading too many erroneous bits.

[0084] In one exemplary embodiment, from the start of the aforementioned programming operation (i.e., multi-stage programming) on ​​the first physical unit until the completion of this programming operation, the memory management circuit 51 can store specific data (also referred to as second data). For example, the second data can be generated by encoding the first data. In particular, the amount of the second data can be less than the total amount of the first data. For example, the memory management circuit 51 can encode data stored in different physical units in the first data (e.g., the aforementioned first sub-data, second sub-data, third sub-data, and fourth sub-data) to generate the second data. For example, this encoding may include XOR encoding or other types of encoding algorithms, which are not limited by the present invention.

[0085] Figure 8 is a schematic diagram illustrating the encoding of first data to generate second data according to an exemplary embodiment of the present invention. Referring to Figure 8, in the first stage of programming, based on the first data, the critical voltage distribution of multiple memory cells belonging to the first entity unit is roughly distributed from state 800 to states 801-816. For example, states 801-816 may be the same as or similar to states 701-716 of Figure 7A. In this case, the critical voltage distribution of these memory cells that have only undergone the first stage of programming (i.e., states 801-816) can roughly reflect the data storage state of the corresponding multiple first entity units (i.e., entity unit (L), entity unit (M), entity unit (U), and entity unit (T)). However, before actually performing the second stage of programming on these memory cells, states 801-816 may have a large area of ​​overlap with each other.

[0086] In one exemplary embodiment, before performing the second-stage programming on memory cells in states 801-816, memory management circuit 51 can encode the first data (i.e., the aforementioned first sub-data, second sub-data, third sub-data, and fourth sub-data) stored in the first entity unit to obtain data EB (i.e., the second data). For example, if the data (i.e., bit combination) stored in a memory cell is one of "1111", "1100", "1001", "0101", "0110", "0000", "1010", and "0011", then by performing XOR encoding on the sub-data (i.e., the first sub-data, second sub-data, third sub-data, and fourth sub-data) stored in this memory cell belonging to entity unit (L), entity unit (M), entity unit (U), and entity unit (T), respectively, the data in data EB corresponding to this memory cell (also called the fifth sub-data) can be encoded as "0". Alternatively, if the data (i.e., bit combination) stored in a memory cell is one of "1110", "1101", "0001", "0100", "0010", "1000", "1011", and "0111", then by performing XOR encoding on the sub-data (i.e., the first sub-data, the second sub-data, the third sub-data, and the fourth sub-data) stored in this memory cell that belong to entity unit (L), entity unit (M), entity unit (U), and entity unit (T), respectively, the data in data EB corresponding to this memory cell can be encoded as "1".

[0087] Alternatively, from another perspective, after the first stage of programming, if the critical voltage of a memory cell falls within the voltage range corresponding to one of states 801, 803, 805, 807, 809, 811, 813, and 815, then the data corresponding to this memory cell in the data EB can be encoded as "0". Furthermore, after the first stage of programming, if the critical voltage of a memory cell falls within the voltage range corresponding to one of states 802, 804, 806, 808, 810, 812, 814, and 816, then the data corresponding to this memory cell in the data EB can be encoded as "1".

[0088] In one exemplary embodiment, based on data EB (i.e., second data), memory management circuit 51 can determine the state of each memory cell belonging to the first entity unit in states 801-816. For example, assuming that the data corresponding to a certain memory cell in data EB is "0", memory management circuit 51 can deduce that the state of this memory cell in states 801-816 is one of states 801, 803, 805, 807, 809, 811, 813, and 815. Alternatively, assuming that the data corresponding to a certain memory cell in data EB is "1", memory management circuit 51 can deduce that the state of this memory cell in states 801-816 is one of states 802, 804, 806, 808, 810, 812, 814, and 816.

[0089] In one exemplary embodiment, based on data EB (i.e., second data), memory management circuit 51 can determine the data (i.e., bit combinations) actually stored in each memory cell belonging to the first entity unit. For example, assuming that the data corresponding to a certain memory cell in data EB is "0", then memory management circuit 51 can deduce that the data stored in this memory cell is one of "1111", "1100", "1001", "0101", "0110", "0000", "1010", and "0011". Alternatively, assuming that the data corresponding to a certain memory cell in data EB is "1", then memory management circuit 51 can deduce that the data stored in this memory cell is one of "1110", "1101", "0001", "0100", "0010", "1000", "1011", and "0111".

[0090] In one exemplary embodiment, the memory management circuit 51 may store data EB (i.e., the second data) based on a single-level memory cell (SLC) mode. For example, after acquiring data EB, the memory management circuit 51 may send a write instruction sequence (also referred to as a second write instruction sequence) to the rewritable non-volatile memory module 43. The second write instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to store data EB in a specific physical cell (also referred to as a second physical cell) within the rewritable non-volatile memory module 43. According to the second write instruction sequence, the rewritable non-volatile memory module 43 may store data EB in the second physical cell based on a single-level memory cell (SLC) mode. In one exemplary embodiment, the memory management circuit 51 may also store data EB based on other operating modes, which are not limited by the present invention.

[0091] In one exemplary embodiment, before the programming operation (i.e., multi-stage programming) for the first entity unit is completed (e.g., only the first stage programming is performed for the first entity unit and the second stage programming has not yet been performed), the memory management circuit 51 may adjust subsequent reads (i.e., read operations) and / or writes (i.e., programming operations) for at least one of the plurality of first entity units based on data EB (i.e., second data). For example, the memory management circuit 51 may adjust at least one of the read voltage level, programming voltage level, and decoding parameters corresponding to at least one of the plurality of first entity units based on data EB (i.e., second data). The read voltage level is used to read data from at least one of the plurality of first entity units. The programming voltage level is used to perform a second programming or complete programming operation on the plurality of first entity units. The decoding parameters are used to decode the data read from at least one of the plurality of first entity units. Furthermore, more different operational behaviors and / or at least one parameter corresponding to a certain operational behavior can also be adjusted based on data EC (i.e., second data), and the present invention does not limit this.

[0092] In one exemplary embodiment, the decoding parameters may include the Log Likelihood Ratio (LLR). For example, the error checking and correction circuit 54 may decode the data based on a Low-density parity-check code (LDPC code) or other decoding algorithms in conjunction with this LLR. In one exemplary embodiment, the decoding parameters may include other types of decoding parameters, as long as they can improve decoding performance.

[0093] In one exemplary embodiment, the memory management circuit 51 may detect an abnormal power-down event before the completion of programming operations on the first physical unit (e.g., only the first stage of programming has been performed on the first physical unit and the second stage of programming has not yet been performed). This abnormal power-down event causes the second stage of programming on the first physical unit to be unable to be performed after the first stage of programming has been performed. For example, if this abnormal power-down event causes the memory storage device 10 to lose power after the first stage of programming has been performed on the first physical unit, the second stage of programming on the first physical unit is expected to be unable to be performed in the power-down state.

[0094] In one exemplary embodiment, after the aforementioned abnormal power outage event is resolved (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can adjust subsequent reads (i.e., read operations) and / or writes (i.e., programmed operations) for at least one of the plurality of first physical units based on the stored data EB (i.e., second data). This allows the memory storage device 10 to be quickly restored to a normal state after the abnormal power outage event is resolved.

[0095] In one exemplary embodiment, the memory management circuit 51 can group multiple memory cells belonging to the plurality of first physical units in the rewritable non-volatile memory module 43 according to the stored data EB (i.e., second data). Then, based on the grouping results, the memory management circuit 51 can adjust subsequent reads and / or writes to at least one of the plurality of first physical units.

[0096] In one exemplary embodiment, the grouping result may reflect that a portion of the memory cells (also referred to as the first memory cell) in the first entity unit belongs to a certain group (also referred to as the first group), and another portion of the memory cells (also referred to as the second memory cell) in the first entity unit belongs to another group (also referred to as the second group). Taking Figure 8 as an example, if the data corresponding to a certain memory cell in the data EB is "0", then the memory management circuit 51 can group this memory cell (i.e., the first memory cell) into the first group. Alternatively, if the data corresponding to a certain memory cell in the data EB is "1", then the memory management circuit 51 can group this memory cell (i.e., the second memory cell) into the second group.

[0097] In one exemplary embodiment, after obtaining the grouping result, the memory management circuit 51 can adjust at least one parameter (also called the first parameter) used for the aforementioned read or write operation based on the critical voltage distribution of the first memory cell (also called the first critical voltage distribution). Furthermore, the memory management circuit 51 can adjust at least one parameter (also called the second parameter) used for the aforementioned read or write operation based on the critical voltage distribution of the second memory cell (also called the second critical voltage distribution). The first parameter and the second parameter can be the same parameter or different parameters. For example, the first parameter and the second parameter may include at least one of the aforementioned read voltage level, programmable voltage level, and decoding parameter. Then, the memory management circuit 51 can access the first physical cell based on the adjusted parameters (e.g., the first parameter and / or the second parameter). For example, the memory management circuit 51 can perform a read operation or a programmable operation on the first physical cell based on the adjusted parameters (e.g., the first parameter and / or the second parameter). Alternatively, the memory management circuit 51 can also perform other management operations on the first physical cell based on the adjusted parameters (e.g., the first parameter and / or the second parameter).

[0098] Figure 9A is a schematic diagram illustrating the critical voltage distribution of memory cells after the first stage of programming according to an exemplary embodiment of the present invention. Referring to Figure 9A, continuing from the exemplary embodiment of Figure 8, it is assumed that after performing the first stage programming on a plurality of memory cells belonging to the first entity unit, the critical voltage distribution of these memory cells includes states 801 to 816. The read voltage level L(1) is between the voltage ranges corresponding to states 805 and 806, respectively. The read voltage level L(2) is between the voltage ranges corresponding to states 811 and 812, respectively. The read voltage level L(3) is between the voltage ranges corresponding to states 814 and 815, respectively.

[0099] It should be noted that in the exemplary embodiment of Figure 9A, since the second-stage programming has not yet been performed on these memory cells, there is a large overlap between adjacent states 805 and 806, states 811 and 812, and states 814 and 815. In this case, if the aforementioned abnormal power failure event occurs, after the abnormal power failure event is restored (e.g., the memory storage device 10 is powered on again), using the read voltage levels L(1) to L(3) to attempt to read the data (i.e., the first sub-data) stored in the physical unit (L) from these memory cells will have a high probability of read failure (because too many erroneous bits are read). At this time, under normal circumstances, unless there is a complete backup of the first data, the first data will be permanently lost. However, if a complete backup of the first data is stored, this backup data will occupy a lot of storage space, resulting in a reduction in the available storage space of the system.

[0100] Figure 9B is a schematic diagram illustrating the critical voltage distribution of grouped memory cells according to an exemplary embodiment of the present invention. Referring to Figure 9B, continuing from the exemplary embodiment of Figure 9A, after the abnormal power failure event is recovered (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can group multiple memory cells belonging to the first entity unit according to the data EB (i.e., the second data) saved before or at the time of the abnormal power failure event. For example, according to the data "0" in the data EB, the memory cells (i.e., the first memory cells) corresponding to states 801, 803, 805, 807, 809, 811, 813, and 815 can be grouped into a first group. For example, the critical voltage distribution (i.e., the first critical voltage distribution) of the first memory cells belonging to the first group may include states 801, 803, 805, 807, 809, 811, 813, and 815. Furthermore, according to data "1" in data EB, the memory cells corresponding to states 802, 804, 806, 808, 810, 812, 814, and 816 can be grouped into a second group. For example, the critical voltage distribution (i.e., the second critical voltage distribution) of the second memory cells belonging to the second group may include states 802, 804, 806, 808, 810, 812, 814, and 816.

[0101] In one exemplary embodiment, the memory management circuit 51 may adjust the parameters used to access the first physical cell based on a first critical voltage distribution and / or a second critical voltage distribution. This allows for a reduction in the number of erroneous bits read when accessing the first physical cell using the adjusted parameters after an abnormal power outage event is resolved (e.g., the memory storage device 10 is powered on again).

[0102] In one exemplary embodiment, the memory management circuit 51 may adjust at least one of the read voltage levels L(1) to L(3) according to a first critical voltage distribution and / or a second critical voltage distribution. The following description will use the adjustment of the read voltage level L(1) as an example.

[0103] Figure 10 is a schematic diagram illustrating the adjustment of the read voltage level according to an exemplary embodiment of the present invention. Referring to Figure 10, and continuing with Figures 9A and 9B, in an exemplary embodiment, based on a first critical voltage distribution (including states 805 and 807), the memory management circuit 51 can add an adjustment value ΔV(1) to the read voltage level L(1) to obtain the read voltage level L(1)'. For example, the voltage position of the read voltage level L(1)' can be located at the bottom of a V-shaped or U-shaped valley between states 805 and 807. How to determine the adjustment value ΔV(1) and / or how to find the bottom of a V-shaped or U-shaped valley between any two states is prior art, and can be achieved, for example, by analyzing the critical voltage distribution state of the memory cell within a specific voltage range, and will not be elaborated here.

[0104] After a power outage event is resolved (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can use the read voltage level L(1)' to read a portion of the data belonging to the physical unit (L) in the first physical unit (including determining which memory cells belong to state 805) to improve the accuracy of the read data. For example, in Figure 10, compared to the read voltage level L(1), using the read voltage level L(1)' to read a portion of the data belonging to the physical unit (L) in the first physical unit can change the classification of memory cells in state 805 located in the diagonal region to the right of the original read voltage level L(1) from belonging to state 806 to belonging to state 805. This effectively reduces the number of erroneous bits read.

[0105] On the other hand, based on the second critical voltage distribution (including states 804 and 806), the memory management circuit 51 can subtract an adjustment value ΔV(2) from the read voltage level L(1) to obtain the read voltage level L(1)''. For example, the voltage position of the read voltage level L(1)'' can be located at the bottom of a V-shaped or U-shaped valley between states 804 and 806.

[0106] After the abnormal power outage event is recovered (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can use the read voltage level L(1)'' to read a portion of the data belonging to the physical cell (L) (including determining which memory cells belong to state 806) to improve the accuracy of the read data. Taking FIG10 as an example, compared to the read voltage level L(1), using the read voltage level L(1)'' to read a portion of the data belonging to the physical cell (L) in the first physical cell can change the memory cells in state 806 located in the diagonal area to the left of the original read voltage level L(1) from belonging to state 805 to belonging to state 806, thereby effectively reducing the number of erroneous bits read. It should be noted that the read voltage level adjustment mechanism presented in the exemplary embodiment of FIG10 can be applied to the adjustment of other read voltage levels, which will not be repeated here.

[0107] In one exemplary embodiment, the memory management circuit 51 may adjust the decoding parameters (e.g., LLR) used in conjunction with at least one of the read voltage levels L(1) to L(3) according to a first critical voltage distribution and / or a second critical voltage distribution. The following description will use the adjustment of the decoding parameters used in conjunction with the read voltage level L(1) as an example.

[0108] Figure 11 is a schematic diagram illustrating the adjustment of decoding parameters according to an exemplary embodiment of the present invention. Referring to Figure 11, following the exemplary embodiments of Figures 9A, 9B, and 10, after recovery from an abnormal power outage event (e.g., the memory storage device 10 is powered on again), it is assumed that multiple voltage ranges are divided based on the original read voltage level L(1), and decoding parameters (e.g., LLR(1)~LLR(6)) corresponding to each voltage range are given. For example, these voltage ranges have the same or similar voltage gaps. In the case of a large overlap between states 805 and 806, even with the LDPC decoding algorithm based on LLR(1)~LLR(6), there is still a high probability that the read data cannot be successfully decoded.

[0109] In one exemplary embodiment, based on the first critical voltage distribution (including states 805 and 807), the memory management circuit 51 can divide multiple voltage intervals based on the adjusted read voltage level L(1)' and assign decoding parameters (e.g., LLR(1)'~LLR(6)') to each voltage interval. For example, these voltage intervals have the same or similar voltage intervals. Subsequently, the error checking and correction circuit 54 can decode the data read based on the read voltage level L(1)' using the LDPC decoding algorithm in conjunction with LLR(1)'~LLR(6)'. Compared to using the original decoding parameters (e.g., LLR(1)~LLR(6)) to decode the data read based on the read voltage level L(1), using the new decoding parameters (e.g., LLR(1)'~LLR(6)') to decode the data read based on the read voltage level L(1)' can effectively improve the decoding success rate.

[0110] On the other hand, based on the second critical voltage distribution (including states 804 and 806), the memory management circuit 51 can divide multiple voltage intervals based on the read voltage level L(1)'' and give the corresponding decoding parameters (e.g., LLR(1)''~LLR(6)'') for each voltage interval. For example, these voltage intervals have the same or similar voltage intervals. Then, the error checking and correction circuit 54 can decode the data read based on the read voltage level L(1)'' using the LDPC decoding algorithm based on LLR(1)''~LLR(6)''. Compared to using the original decoding parameters (e.g., LLR(1)~LLR(6)) to decode the data read based on the read voltage level L(1), using the new decoding parameters (e.g., LLR(1)''~LLR(6)'') to decode the data read based on the read voltage level L(1)'' can effectively improve the decoding success rate.

[0111] In one exemplary embodiment, the memory management circuit 51 may also correct the data (also referred to as the third data) read from the first entity unit (i.e., the entity unit that has performed the first stage of programming but has not yet performed the second stage of programming) that has not yet been fully programmed, based on the data EB (i.e., the second data) saved before or at the time of the abnormal power failure event.

[0112] Figure 12 is a schematic diagram illustrating the correction of erroneous bits based on second data according to an exemplary embodiment of the present invention. Referring to Figure 12, continuing from the exemplary embodiment of Figure 9A, after the abnormal power failure event is recovered (e.g., the memory storage device 10 is powered on again), when attempting to read the data (i.e., the first sub-data) stored in the physical unit (L) from these memory cells using the read voltage level L (1), it is possible that some memory cells belonging to state 805 may be mistakenly identified as belonging to state 806 because the threshold voltage of some memory cells belonging to state 805 is higher than the read voltage level L (1). Alternatively, it is also possible that some memory cells belonging to state 806 may be mistakenly identified as belonging to state 805 because the threshold voltage of some memory cells belonging to state 806 is lower than the read voltage level L (1).

[0113] In one exemplary embodiment, for a memory cell that actually belongs to state 805 but is misclassified as belonging to state 806 (also referred to as the first target memory cell), the memory management circuit 51 can update the misclassified first sub-data in the first target memory cell from "0" (belonging to state 806) to "1" (belonging to state 805) based on the data corresponding to the first target memory cell in the data EB (i.e., the fifth sub-data), combined with the remaining sub-data (e.g., the second sub-data, the third sub-data, and the fourth sub-data) read from the first target memory cell. It should be noted that this data correction process only involves logical operations (e.g., XOR operation) between multiple sub-data (i.e., the first to the fourth sub-data) read from the same memory cell (i.e., the first target memory cell) and the data corresponding to the first target memory cell in the data EB (i.e., the fifth sub-data), and may not involve the LDPC or other types of decoding algorithms used by the error checking and correction circuit 54.

[0114] Similarly, for a memory cell that actually belongs to state 806 but is misclassified as belonging to state 805 (also called the second target memory cell), the memory management circuit 51 can update the misclassified first sub-data in the second target memory cell from "1" (belonging to state 805) to "0" (belonging to state 806) based on the data corresponding to the second target memory cell in the data EB (i.e., the fifth sub-data), combined with the other sub-data read from the second target memory cell (e.g., the second sub-data, the third sub-data, and the fourth sub-data). It should be noted that this data correction process also only involves logical operations (e.g., XOR operation) between multiple sub-data (i.e., the first to the fourth sub-data) read from the same memory cell (i.e., the second target memory cell) and the data corresponding to the second target memory cell in the data EB (i.e., the fifth sub-data), and does not involve the LDPC or other types of decoding algorithms used by the error checking and correction circuit 54.

[0115] In one exemplary embodiment, after an abnormal power outage event is recovered (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can determine or adjust the programmed voltage level corresponding to each memory cell of the first entity unit based on the data actually stored therein (i.e., the first data). How to obtain the data actually stored in each memory cell of the first entity unit (i.e., the first data) has been described in detail above and will not be repeated here. Then, the memory management circuit 51 can perform incomplete programming operations (e.g., second-stage programming) on ​​the first entity unit based on the determined or adjusted programmed voltage level. Alternatively, in one exemplary embodiment, the memory management circuit 51 may also restore the first data in other entity units; this is not a limitation of the present invention.

[0116] Therefore, without the need to store backup data of the first data or retrieve the first data from the host system 11, after the abnormal power failure event is recovered (e.g., the memory storage device 10 is powered on again), the memory management circuit 51 can continue to complete the previously unfinished programmed operations, thereby improving the working performance of the memory storage device 10.

[0117] In one exemplary embodiment, the data EB (i.e., the second data) may also be automatically generated in response to a detected abnormal power failure event before the completion of the programmed operation (i.e., multi-stage programming) for the first entity unit. That is, in one exemplary embodiment, if the abnormal power failure event is not detected before the completion of the programmed operation (i.e., multi-stage programming) for the first entity unit, the data EB (i.e., the second data) may not be generated.

[0118] In one exemplary embodiment, the memory management circuit 51 only needs to complete the programmed operation (e.g., the second data) for saving the data EB to the first physical unit. Once the programmed operation (e.g., the second data) for the first physical unit is completed, the memory management circuit 51 can remove the data EB (i.e., the second data). For example, removing the data EB may mean marking the physical unit storing the data EB as storing invalid data.

[0119] In one exemplary embodiment, the memory management circuit 51 generates and stores data EC (i.e., second data) corresponding to an entity unit (or a memory cell belonging to that entity unit) only for entity units that have completed the first stage of programming but have not yet completed the second stage of programming. In another exemplary embodiment, the memory management circuit 51 does not generate and / or store data EC (i.e., second data) corresponding to an entity unit (or a memory cell belonging to that entity unit) for entity units that have completed or finished the second stage of programming.

[0120] Figure 13 is a schematic diagram illustrating the interleaved programming of memory cells on multiple character lines according to an exemplary embodiment of the present invention. Referring to Figure 13, in an exemplary embodiment, it is assumed that the rewritable non-volatile memory module 43 includes at least character lines (1) to character lines (3), and each character line contains strings (1) to strings (5). Furthermore, each string contains multiple memory cells. It should be noted that the total number of character lines included in the rewritable non-volatile memory module 43 and the total number of strings included in each character line can be adjusted according to practical needs.

[0121] In one exemplary embodiment, in the rewritable non-volatile memory module 43 that supports the aforementioned multi-stage programming, the rewritable non-volatile memory module 43 performs interleaved programming on multiple strings on multiple character lines to store data into the corresponding physical units. Taking Figure 13 as an example, when writing data, the rewritable non-volatile memory module 43 can, according to the numbers in Figure 13 (indicating the programming order), first sequentially perform the first stage programming (corresponding to numbers 1 to 5 in Figure 13) on the strings (1) to (5) on the character line (1).

[0122] After performing the first stage programming (corresponding to number 5 in Figure 13) on the string (5) on character line (1), the rewritable non-volatile memory module 43 can sequentially perform the first stage programming (corresponding to number 6 in Figure 13) on the string (1) on character line (2), the second stage programming (corresponding to number 7 in Figure 13) on the string (1) on character line (1), the first stage programming (corresponding to number 8 in Figure 13) on the string (2) on character line (2), and the second stage programming (corresponding to number 9 in Figure 13) on the string (2) on character line (1), and so on. Only after the first stage programming and the second stage programming are fully performed on a certain string will the string (or the memory cell on the string) be considered to have undergone a complete programming operation. It should be noted that the programming order in Figure 13 is only an example and is not intended to limit the present invention.

[0123] Traditionally, if an abnormal power outage occurs before the second-stage programming of certain memory cells is completed, the memory management circuit 51 may need to retrieve the previously incomplete data from the host system 11 and re-execute the write operation corresponding to this data after the abnormal power outage is recovered, resulting in wasted bandwidth between the host system 11 and the memory storage device 10. Alternatively, before the second-stage programming of certain memory cells is completed, the memory management circuit 51 can retain backup data corresponding to the data to be stored for these memory cells. If an abnormal power outage occurs, the memory management circuit 51 can re-execute the data write based on this backup data after the abnormal power outage is recovered. However, if the data write mechanism of FIG13 is adopted, the memory management circuit 51 needs to retain backup data belonging to at least 6 strings before completing the programming operation for each character line, resulting in rapid consumption of system storage resources.

[0124] However, in the aforementioned exemplary embodiments, by saving the second data instead of the traditional backup data corresponding to the first data, system storage resources can be effectively saved. Furthermore, the second data can also be used to adjust read and / or write operations for specific physical units to improve the operational performance and stability of the memory storage device 10.

[0125] Figure 14 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Referring to Figure 14, in step S1401, multi-stage programming is performed on a plurality of physical units in a rewritable non-volatile memory module based on first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming. In step S1402, before the multi-stage programming begins and the second-stage programming is completed, second data is saved, wherein the second data is generated by encoding the first data. In step S1403, based on the second data, at least one of the read operations or programming operations of the plurality of physical units is adjusted.

[0126] Figure 15 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Referring to Figure 15, in step S1501, programming operations are performed on multiple physical units in a rewritable non-volatile memory module based on first data. In step S1502, the first data is encoded to generate second data. In step S1503, the second data is saved. In step S1504, it is determined whether the programming operations for the multiple physical units have been completed. If the programming operations have been completed, in step S1505, the second data is removed.

[0127] If the programmed operation has not yet been completed, in step S1506, an abnormal power outage event is detected. If an abnormal power outage event occurs, in step S1507, after the abnormal power outage event is resolved, the read operation or programmed operation of at least one of the plurality of entity units is adjusted according to the second data. If no abnormal power outage event occurs, the process can return to step S1504.

[0128] However, the steps in Figures 14 and 15 have been described in detail above and will not be repeated here. It is worth noting that each step in Figures 14 and 15 can be implemented as multiple pieces of code or circuits, and this invention is not limited thereto. Furthermore, the methods in Figures 14 and 15 can be used in conjunction with the above exemplary embodiments, or they can be used alone, and this invention is not limited thereto.

[0129] In summary, the memory management method, memory storage device, and memory control circuit unit proposed in this invention can temporarily store corresponding encoded data (i.e., second data) before the multi-stage programming of multiple physical units is actually completed. Therefore, if an abnormal power outage occurs during the execution of the multi-stage programming, subsequent recovery operations or adjustments to relevant settings can be quickly performed based on this encoded data, thereby improving the operating efficiency of the memory storage device.

[0130] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0131] 10,30: Memory storage device 11,31: Host System 110: System Bus 111: Processor 112: Random Access Memory 113: Read-only memory 114: Data Transfer Interface 12: Input / Output (I / O) Devices 20: Motherboard 201: USB flash drive 202: Memory Card 203: Solid State Drive 204: Wireless memory storage device 205: Global Positioning System Module 206: Network Interface Card 207: Wireless transmission device 208: Keyboard 209: Screen 210: Loudspeaker 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip packaged storage device 41: Connection Interface Unit 42: Memory control circuit unit 43: Rewritable non-volatile memory modules 51: Memory Management Circuit 52: Host Interface 53: Memory Interface 54: Error checking and correction circuit 55: Buffer memory 56: Power Management Circuit 601: Storage Area 602: Idle Area 610(0)~610(B),L,M,U,T: Solid elements 612(0)~612(C): Logic Unit 700~716, 721~736, 800~816: Status L(1)~L(3),M(1)~M(4),U(1)~U(4),T(1)~T(4),L(1)',L(1)'': Read voltage level EB: Second Document LLR(1)~LLR(6),LLR(1)'~LLR(6)',LLR(1)''~LLR(6)'': Decoding parameters (log-probability ratio) S1401: Step (Based on the first data, perform multi-stage programming on multiple physical units in a rewritable non-volatile memory module, wherein the multi-stage programming includes a first-stage programming and a second-stage programming) S1402: Step (Before starting multi-stage programming and before the second stage programming is completed, save the second data, which is generated by encoding the first data) S1403: Step (Adjusting the read operation or programmed operation of at least one of the plurality of entity units according to the second data) S1501: Step (Based on the first data, perform programmed operations on multiple physical units in the rewritable non-volatile memory module) S1502: Step (Encode the first data to generate the second data) S1503: Steps (Save the second data) S1504: Steps (Procedural operation completed?) S1505: Step (Remove Second Data) S1506: Procedure (An abnormal power outage event occurred?) S1507: Step (After the abnormal power outage event is recovered, adjust the read operation or programmed operation of at least one of the plurality of entity units according to the second data)

Claims

1. A memory management method for a rewritable non-volatile memory module, the memory management method comprising: Based on the first data, multi-stage programming is performed on multiple physical units in the rewritable non-volatile memory module, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; before the execution of the multi-stage programming begins and the second-stage programming is completed, second data is saved, wherein the second data is generated by encoding the first data; and based on the second data, at least one of the read operations or programming operations of the multiple physical units that have completed the first-stage programming but have not yet completed the second-stage programming is adjusted.

2. The memory management method as described in claim 1, wherein the plurality of entity units belong to the same word line.

3. The memory management method as described in claim 2, wherein the plurality of entity units includes at least an upper entity programming unit and a lower entity programming unit.

4. The memory management method as claimed in claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: After the first stage of programming is completed, detect abnormal power outage events before the second stage of programming is completed; And after the abnormal power outage event is recovered, based on the second data, the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming is adjusted.

5. The memory management method as claimed in claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: According to the second data, the memory cells corresponding to the multiple physical units in the rewritable non-volatile memory module are grouped. And based on the grouping results, adjust the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

6. The memory management method as described in claim 5, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the grouping result, includes: Based on the first critical voltage distribution of the plurality of first memory cells belonging to the first group among the plurality of memory cells, the first parameter used for the read operation or the programmed operation is adjusted; and based on the second critical voltage distribution of the plurality of second memory cells belonging to the second group among the plurality of memory cells, the second parameter used for the read operation or the programmed operation is adjusted.

7. The memory management method as claimed in claim 1, wherein the step of adjusting the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: Based on the second data, at least one of the read voltage level, programmable voltage level, and decoding parameters corresponding to at least one of the plurality of physical units is adjusted.

8. The memory management method as described in claim 1, further comprising: The second data is generated in response to an abnormal power outage event prior to the completion of the second phase of programming.

9. The memory management method as described in claim 1, further comprising: Based on the second data, the third data read from at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming is corrected.

10. The memory management method as described in claim 1, further comprising: The second data is not saved for the multiple entity units that have completed the second phase of programming.

11. The memory management method as claimed in claim 1, wherein in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first stage programming is different from the programming voltage level for the second stage programming.

12. A memory storage device, comprising: A connection interface unit for coupling to the host system; Rewritable non-volatile memory modules; The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: perform multi-stage programming on a plurality of physical units in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; save second data before the execution of the multi-stage programming begins and the second-stage programming is completed, wherein the second data is generated by encoding the first data; and adjust the read operation or programming operation of at least one of the plurality of physical units that have completed the first-stage programming but have not yet completed the second-stage programming according to the second data.

13. The memory storage device as claimed in claim 12, wherein the plurality of physical units belong to the same word line.

14. The memory storage device as claimed in claim 13, wherein the plurality of physical units include at least an upper physical programming unit and a lower physical programming unit.

15. The memory storage device as claimed in claim 12, wherein the operation by which the memory control circuit unit adjusts the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: After the first stage of programming is completed, detect abnormal power outage events before the second stage of programming is completed; And after the abnormal power outage event is recovered, based on the second data, the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming is adjusted.

16. The memory storage device as claimed in claim 12, wherein the operation by which the memory control circuit unit adjusts the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: According to the second data, the memory cells corresponding to the multiple physical units in the rewritable non-volatile memory module are grouped. And based on the grouping results, adjust the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

17. The memory storage device as claimed in claim 16, wherein the operation of the memory control circuit unit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the grouping result, includes: Based on the first critical voltage distribution of the plurality of first memory cells belonging to the first group among the plurality of memory cells, the first parameter used for the read operation or the programmed operation is adjusted; and based on the second critical voltage distribution of the plurality of second memory cells belonging to the second group among the plurality of memory cells, the second parameter used for the read operation or the programmed operation is adjusted.

18. The memory storage device as claimed in claim 12, wherein the operation by which the memory control circuit unit adjusts the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming based on the second data includes: Based on the second data, at least one of the read voltage level, programmable voltage level, and decoding parameters corresponding to at least one of the plurality of physical units is adjusted.

19. The memory storage device as claimed in claim 12, wherein the memory control circuit unit is further configured to: generate the second data in response to an abnormal power failure event prior to the completion of the second stage programming.

20. The memory storage device as claimed in claim 12, wherein the memory control circuit unit is further configured to: correct, based on the second data, third data read from at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming.

21. The memory storage device as claimed in claim 12, wherein the memory control circuit unit is further configured to: not store the second data for the plurality of physical units that have completed the second stage of programming.

22. The memory storage device as claimed in claim 12, wherein in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first stage programming is different from the programming voltage level for the second stage programming.

23. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; The memory management circuitry is coupled to the host interface and the memory interface, wherein the memory management circuitry is configured to: perform multi-stage programming on a plurality of physical cells in the rewritable non-volatile memory module according to first data, wherein the multi-stage programming includes a first-stage programming and a second-stage programming; save second data before the execution of the multi-stage programming begins and the second-stage programming is completed, wherein the second data is generated by encoding the first data; and adjust, according to the second data, at least one of the read operations or programming operations of the plurality of physical cells that have completed the first-stage programming but have not yet completed the second-stage programming.

24. The memory control circuit unit as described in claim 23, wherein the plurality of physical units belong to the same word line.

25. The memory control circuit unit as claimed in claim 24, wherein the plurality of physical units includes at least an upper physical programming unit and a lower physical programming unit.

26. The memory control circuit unit as claimed in claim 23, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming based on the second data includes: After the first stage of programming is completed, detect abnormal power outage events before the second stage of programming is completed; And after the abnormal power outage event is recovered, based on the second data, the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming is adjusted.

27. The memory control circuit unit as claimed in claim 23, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: According to the second data, the memory cells corresponding to the multiple physical units in the rewritable non-volatile memory module are grouped. And based on the grouping results, adjust the read operation or the programming operation of at least one of the plurality of entity units that have completed the first stage of programming but have not yet completed the second stage of programming.

28. The memory control circuit unit as claimed in claim 27, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the grouping result, includes: Based on the first critical voltage distribution of the plurality of first memory cells belonging to the first group among the plurality of memory cells, the first parameter used for the read operation or the programmed operation is adjusted; and based on the second critical voltage distribution of the plurality of second memory cells belonging to the second group among the plurality of memory cells, the second parameter used for the read operation or the programmed operation is adjusted.

29. The memory control circuit unit as claimed in claim 23, wherein the operation of the memory management circuit adjusting the read operation or the programming operation of at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming, based on the second data, includes: Based on the second data, at least one of the read voltage level, programmable voltage level, and decoding parameters corresponding to at least one of the plurality of physical units is adjusted.

30. The memory control circuit unit as claimed in claim 23, wherein the memory management circuit is further configured to: generate the second data in response to an abnormal power failure event prior to the completion of the second stage programming.

31. The memory control circuit unit as claimed in claim 23, wherein the memory management circuit is further configured to: correct, based on the second data, a third data read from at least one of the plurality of physical units that have completed the first stage of programming but have not yet completed the second stage of programming.

32. The memory control circuit unit as claimed in claim 23, wherein the memory management circuit is further configured to: not store the second data for the plurality of physical units that have completed the second stage programming.

33. The memory control circuit unit as claimed in claim 23, wherein in the multi-stage programming performed on the plurality of physical units, the programming voltage level for the first stage programming is different from the programming voltage level for the second stage programming.

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