Apparatus and methods for memory page translations within die architectures

Abstract

Methods and apparatuses directed to die solutions that reduce memory access latencies are described. In one example, a die includes translation control logic, and memory address translation logic electrically coupled to the translation control logic. The translation control logic receives a virtual memory address for virtual to physical address translation from a requesting device. The translation control logic transmits an address translation request to the memory address translation logic, where the address translation request includes the virtual memory address. Based on the virtual memory address, the memory address translation logic reads one or more translation tables to perform one or more memory address translations. Based on the translations, the memory address translation logic generates a physical memory address. The memory address translation logic then transmits the physical memory address to the translation control logic. The translation control logic transmits the physical memory address to the requesting device.

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