Memory controller circuit and operation method thereof having data forwarding mechanism

Abstract

A memory controller circuit having a data forwarding mechanism is provided. A data writing circuit stores a data writing command and write data. A data reading circuit stores a data reading command. A comparison circuit compares a read address and a write address to determine a data hazard condition occurs when the data read command is later than the data write command and the read address and the write address are the same. The data reading circuit receives the write data as the read data when the data hazard condition occurs without transmitting the data reading command to the memory circuit. The data writing circuit sets a data hazard flag to be a hazard state such that a storage space corresponding to the data writing command is not allowed to be overwritten and sets the data hazard flag to be a non-hazard state after the data writing command is processed.

Description

Technical Field

[0001] This invention relates to memory control technology, and more particularly to a memory control circuit with a data forwarding mechanism and its operation method. Prior Technology

[0002] When a processor accesses memory, various data hazards can occur, which may affect the execution order of instructions or cause instruction stalls. For example, a data hazard may occur when the current instruction is writing data needed by a subsequent instruction. When a data hazard occurs, it may cause data transfer to stall, resulting in a decrease in data transfer performance. Summary of the Invention

[0003] In view of the problems of the prior art, one object of the present invention is to provide a memory control circuit with a data feedforward mechanism and a method of operation thereof, so as to improve the prior art.

[0004] This invention includes a memory control circuit with a data feedforward mechanism, configured to access a memory circuit, comprising: a data writing circuit, a data reading circuit, and a comparison circuit. The data writing circuit stores corresponding data writing instructions and write data, and sets a data hazard flag corresponding to the storage space of the data writing instruction. The data reading circuit stores data reading instructions. The comparison circuit compares the read address of the data reading instruction with the write address of the data writing instruction, and determines that a data hazard condition has occurred when the timing of the data reading instruction is later than that of the data writing instruction and the read address and write address are the same. When a data hazard condition occurs, the data reading circuit receives the write data from the data writing circuit as read data, and does not transmit the data reading instruction to the memory circuit. When a data hazard condition occurs, the data writing circuit sets the data hazard flag to a hazard state to prevent the storage space from being overwritten, and sets the data hazard flag to a non-hazard state after the data writing instruction is processed and the write data is written to the memory circuit.

[0005] The present invention further includes a memory control circuit operation method with a data feedforward mechanism, configured to access the memory circuit, comprising: storing a corresponding data write instruction and write data by a data write circuit, and setting a data fault flag corresponding to the storage space of the data write instruction; storing a data read instruction by a data read circuit; comparing the read address of the data read instruction with the write address of the data write instruction by a comparison circuit, and determining that a data fault condition has occurred when the timing of the data read instruction is later than that of the data write instruction and the read address and the write address are the same; receiving the write data as read data by the data write circuit when a data fault condition occurs by the data read circuit, and not transmitting the data read instruction to the memory circuit; and setting the data fault flag to a fault state by the data write circuit when a data fault condition occurs to prevent the storage space from being overwritten, and setting the data fault flag to a non-fault state after the data write instruction is processed and the write data is written to the memory circuit.

[0006] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0007] [Figure 1] shows a block diagram of a computer system according to one embodiment of the present invention; [Figure 2A] shows a block diagram of the memory control circuit in one embodiment of the present invention; [Figure 2B] shows a more detailed block diagram of the data writing circuit in one embodiment of the present invention; [Figure 2C] shows a more detailed block diagram of the data reading circuit in one embodiment of the present invention; [Figure 3] shows a timing diagram of signals on multiple signal paths related to the operation of the memory control circuit in one embodiment of the present invention; [Figure 4] shows a timing diagram of signals on multiple signal paths related to the operation of the memory control circuit in one embodiment of the present invention; and [Figure 5] shows a flowchart of a memory control circuit operation method with a data feedforward mechanism in one embodiment of the present invention. Implementation

[0008] One objective of this invention is to provide a memory control circuit with a data feedforward mechanism and its operation method. When a data failure occurs, the data writing circuit receives the data to be written as the data to be read, avoiding the postponement of data reading instructions and read / write turnaround in order to process data writing instructions first. This significantly reduces the latency caused by these behaviors and improves the performance of the memory control circuit in performing read and write operations.

[0009] Please refer to Figure 1. Figure 1 shows a block diagram of a computer system 100 according to one embodiment of the present invention. The computer system 100 includes a processor 110, a memory control circuit 120, and a memory circuit 130.

[0010] The memory circuit 130 may be, for example, but not limited to, dynamic random access memory (DRAM) for storing data. The memory control circuit 120 may be electrically coupled to the processor 110 via a bus so that the processor 110 can access the memory circuit 130 through the memory control circuit 120.

[0011] Access to the memory circuit 130 includes data write operations and data read operations. For a data write operation, the memory control circuit 120 receives a data write instruction WDC and write data WDA from the processor 110, processes them, and transmits them to the memory circuit 130 for data writing. The memory circuit 130 stores the write data WDA according to the write address contained in the data write instruction WDC. For a data read operation, the memory control circuit 120 receives a data read instruction RDC from the processor 110, and reads from the corresponding address of the memory circuit 130 according to the read address contained in the data read instruction RDC. The returned data TDA from the memory circuit 130 is then transmitted to the processor 110 as the read data RDA.

[0012] In some applications, the memory control circuit 120 and the memory circuit 130 can only perform one of the following operations at a time: a data write operation or a data read operation. In such a case, if the processor 110 issues a data write instruction WDC corresponding to a specific address and then issues a data read instruction RDC corresponding to the same specific address shortly thereafter, there is a certain probability that the memory control circuit 120 will process the data read instruction RDC first and read the old data instead of the new data to be written by the data write instruction WDC, thus creating a data hazard (in this example, called the read-after-write (RAW) hazard).

[0013] To avoid the efficiency degradation caused by the memory control circuit 120 pausing the processing of the data read instruction RDC and prioritizing the processing of the data write instruction WDC in the event of a data failure, the memory control circuit 120 may have the data feedforward mechanism of this invention, thereby achieving the effect of maintaining data transmission efficiency while avoiding data failure. The structure and operation of the memory control circuit 120 with the data feedforward mechanism will be described in detail below.

[0014] Please refer to Figure 2A. Figure 2A shows a block diagram of a memory control circuit 120 according to one embodiment of the present invention. The memory control circuit 120 includes: a data writing circuit 200, a data reading circuit 210, a data reading multiplexer 220, a comparison circuit 230, a physical layer circuit 240, and an instruction sorting circuit 250.

[0015] The data writing circuit 200 stores the corresponding data writing command WDC and the written data WDA, and sets the data hazard flag DHF in the storage space corresponding to the data writing command WDC.

[0016] Please also refer to Figure 2B. Figure 2B shows a more detailed block diagram of the data writing circuit 200 in one embodiment of the present invention. As shown in Figure 2B, the data writing circuit 200 includes an instruction storage circuit 202, a data storage circuit 204, and a processing circuit 206.

[0017] When processing circuit 206 receives, for example, but not limited to, a data write instruction WDC and a write data WDA from processor 110 of FIG. 1, it stores the data write instruction WDC in instruction storage circuit 202 and the write data WDA in data storage circuit 204. In one embodiment, instruction storage circuit 202 and data storage circuit 204 may be, for example, but not limited to, static random access memory (SRAM), a register, or other memory that does not require additional control circuitry to operate.

[0018] The storage space used to store the data write instruction WDC is part of the instruction storage circuit 202. More specifically, the instruction storage circuit 202 may include multiple storage units (not shown), and the storage space used to store the data write instruction WDC is one of these storage units. The processing circuit 206 sets a data hazard flag DHF corresponding to the storage space. In one embodiment, the data hazard flag DHF itself can be stored in this storage space.

[0019] The Data Failure Flag (DHF) is used to indicate whether a data failure has occurred in the write command (WDC) of the data stored in this storage space. In one embodiment, the processing circuit 206 can set the Data Failure Flag (DHF) to a failure state to indicate that a data failure has occurred, or set the Data Failure Flag (DHF) to a non-failure state to indicate that a data failure has not occurred.

[0020] The critical state and the non-critical state can be represented by one bit, either 0 or 1. For example, the processing circuit 206 can set the data critical flag DHF to 1 to indicate a critical state, and the processing circuit 206 can set the data critical flag DHF to 0 to indicate a non-critical state. However, the present invention is not limited thereto.

[0021] It should be noted that Figure 2B only shows a set of corresponding data write instructions WDC and write data WDA as an example. In practice, the instruction storage circuit 202 and the data storage circuit 204 can store multiple corresponding data write instructions WDC and write data WDA simultaneously.

[0022] On the other hand, the data reading circuit 210 stores the data reading instruction RDC.

[0023] Please also refer to Figure 2C. Figure 2C shows a more detailed block diagram of the data reading circuit 210 in one embodiment of the present invention. As shown in Figure 2C, the data reading circuit 210 includes an instruction storage circuit 212, a data storage circuit 214, and a processing circuit 216.

[0024] When processing circuit 216 receives a data read instruction RDC, it stores the data read instruction RDC in instruction storage circuit 212, and when it receives a read data RDA, it stores the read data RDA in data storage circuit 214 for retrieval by processor 110 of FIG1, for example, but not limited to. In one embodiment, instruction storage circuit 212 and data storage circuit 214 may be, for example, but not limited to, static random access memory, temporary registers, or other memory that does not require additional control circuitry to operate.

[0025] The data read multiplexer 220 is electrically coupled to the data write circuit 200, the instruction sorting circuit 250 and the data read circuit 210, so as to select one of the data write circuit 200 and the instruction sorting circuit 250 as the source of the read data RDA according to the operation of the comparison circuit 230, and transmit it to the data read circuit 210.

[0026] It should be noted that Figure 2C only shows one data read instruction RDC and one read data RDA as an example. In practice, the instruction storage circuit 212 can store multiple data read instructions RDC simultaneously, and the data storage circuit 204 can also store multiple read data RDA simultaneously.

[0027] The comparison circuit 230 is electrically coupled to the data writing circuit 200 and the data reading circuit 210 to capture and compare the read address of the data read instruction RDC with the write address of the data write instruction WDC. If the timing of the data read instruction RDC is later than that of the data write instruction WDC, and the read address and write address are the same, the comparison circuit 230 determines that a data failure has occurred. Conversely, if the timing of the data read instruction RDC is not later than that of the data write instruction WDC, or if the read address and write address are different, the comparison circuit 230 determines that no data failure has occurred. The data writing circuit 200 and the data reading circuit 210 will operate based on the comparison result of the comparison circuit 230.

[0028] In one embodiment, the comparison circuit 230 may be a standalone circuit or may be directly the processing circuit 206 of the data writing circuit 200. Whenever the data reading circuit 210 receives a data reading instruction RDC, the comparison circuit 230 will retrieve the data reading instruction RDC and compare it with the data writing instruction WDC stored in the data writing circuit 200.

[0029] The physical layer circuit 240 is electrically coupled to the memory circuit 130. The instruction sequencing circuit 250 is configured to perform data write operations and data read operations on the memory circuit 130 through the physical layer circuit 240.

[0030] Since the data write operation is independent of whether a data failure occurs, when the instruction sequencing circuit 250 performs a data write operation, the processing circuit 206 of the data write circuit 200 retrieves and transmits the data write instruction WDC and the write data WDA from the instruction storage circuit 202 and the data storage circuit 204 to the instruction sequencing circuit 250. The instruction sequencing circuit 250 then writes data to the memory circuit 130 through the physical layer circuit 240 according to the data write instruction WDC and the write data WDA, so as to write the write data WDA into the memory circuit 130 at the position corresponding to the write address in the data write instruction WDC.

[0031] Conversely, the performance of data read operations is dependent on whether a data failure occurs. When the instruction sequencing circuit 250 performs a read operation and no data failure occurs, the processing circuit 216 of the data read circuit 210 retrieves and transmits the data read instruction RDC from the instruction storage circuit 212 to the instruction sequencing circuit 250. The instruction sequencing circuit 250 then reads data from the memory circuit 130 through the physical layer circuit 240 based on the data read instruction RDC indicating that no data failure has occurred in the data read circuit 210.

[0032] The instruction sequencing circuit 250 further transmits the return data TDA received from the memory circuit 130 via the physical layer circuit 240 to the data read circuit 210 based on the data read from the memory circuit 130. The transmission of the return data TDA can be performed through the data read multiplexer 220. More specifically, when no data failure occurs, the data read multiplexer 220 selects the instruction sequencing circuit 250 to receive the return data TDA from the memory circuit 130 as the read data RDA, which is then received by the data read circuit 210 and stored in the data storage circuit 214.

[0033] In the event of a data failure, the data read circuit 210 receives the written data WDA from the data write circuit 200 as the read data RDA, and does not transmit the data read instruction RDC to the memory circuit 130. More specifically, the processing circuit 216 of the data read circuit 210 may, based on the comparison result of the comparison circuit 230, not transmit the data read instruction RDC to the memory circuit 130, while the data read multiplexer 220 selects the data write circuit 200 to receive the written data WDA as the read data RDA when a data failure occurs, and the data read circuit 210 receives it for storage in the data storage circuit 214.

[0034] On the other hand, the processing circuit 206 of the data writing circuit 200 can set the data fault flag DHF to a fault state when a data fault occurs, so as to prevent the storage space of the data writing instruction WDC from being overwritten, based on the comparison result of the comparison circuit 230. After the data writing instruction WDC is processed and the write data WDA is written to the memory circuit 130, the data fault flag DHF is set to a non-fault state.

[0035] Because the data read circuit 210 receives the data WDA from the data write circuit 200 directly before the data WDA is actually written to the memory circuit 130, according to the aforementioned data feedforward mechanism, when a data failure occurs, the data failure flag DHF set to the failure state can prevent the data write circuit 200 from overwriting the data write command that caused the data failure when it receives a new data write command, ensuring that the data WDA is actually written to the memory circuit 130, and maintaining the consistency between data writing and data reading.

[0036] Please refer to Figure 3. Figure 3 shows a timing diagram of signals on multiple signal paths related to the operation of the memory control circuit 120 in one embodiment of the present invention.

[0037] In Figure 3, apart from the operating clock CLK used for timing reference, the following are drawn in sequence: the instruction path COM located between the instruction sorting circuit 250 and the memory circuit 130 and including the physical layer circuit 240 and connecting traces; the data path DAT located between the instruction sorting circuit 250 and the memory circuit 130 and including the physical layer circuit 240 and connecting traces; and the data path DAP located between the processor 110 and the data read circuit 210 and including connecting traces.

[0038] Figure 3 illustrates the data failure situation that occurs when the instruction sequencing circuit 250 performs a data write operation. At this time, the instruction sequencing circuit 250 continues to control the physical layer circuit 240 to write data to the memory circuit 130, unaffected by the data failure situation. Therefore, the data write instruction 300 can be continuously transmitted on the instruction path COM, and the write data 310 can be continuously transmitted on the data path DAT.

[0039] Simultaneously, corresponding to the occurrence of the data failure situation determined by the first data write instruction 300 in Figure 3, the data path DAP can have the read data 320 transmitted according to the operation of the aforementioned data feedforward mechanism. Therefore, even if the instruction sequencing circuit 250 is performing a data write operation, the data read circuit 210 can still immediately obtain the required data from another path by the data write circuit 200 when a data failure situation occurs, without affecting the data write operation.

[0040] Please refer to Figure 4. Figure 4 shows a timing diagram of signals on multiple signal paths related to the operation of the memory control circuit 120 in one embodiment of the present invention.

[0041] In Figure 4, apart from the operating clock CLK used for timing reference, the following are drawn in sequence: the instruction path COM located between the instruction sorting circuit 250 and the memory circuit 130 and including the physical layer circuit 240 and connecting traces; the data path DAT located between the instruction sorting circuit 250 and the memory circuit 130 and including the physical layer circuit 240 and connecting traces; the data path DRT located between the data write circuit 200 and the data read circuit 210 and including connecting traces; and the data path DAP located between the processor 110 and the data read circuit 210 and including connecting traces.

[0042] Figure 4 illustrates the situation where a data failure occurs during a data read operation in the instruction sequencing circuit 250. At this time, the instruction sequencing circuit 250 controls the physical layer circuit 240 to write data to the memory circuit 130. However, at the moment when the corresponding data read circuit 210 receives the written data from the data write circuit 200, the physical layer circuit 240 deselects the memory circuit 130 to prevent the data read instruction indicating a data failure from being transmitted to the memory circuit 130.

[0043] Therefore, the instruction sequencing circuit 250 includes a deselection 410, acting as a "bubble," between the transmission of multiple data read instructions 400 on the instruction path COM, reserving a blank segment from which no instructions are sent. The data path DAT includes a corresponding gap between the reception of return data 420 from the memory circuit 130 and the data path DRT, which then performs the transmission of write data 430 from the data write circuit 200 to the data read circuit 210 during this gap, thereby avoiding resource conflicts. Therefore, the data path DAP has continuous data read 440 and does not need to pause data read operations due to data failure.

[0044] Please refer to Table 1. Table 1 shows a list of performance parameters accessed by the memory control circuit 120 to the memory circuit 130 in one embodiment of the present invention, with and without the data feedforward mechanism.

[0045] Table 1 Not adopted use Not adopted use Data loss rate 20% 20% 50% 50% Data bandwidth (megabits per second) 2004.20 2936.01 (+31.7%) 1936.49 3088.65 (+37.3%) Data path Usage rate (%) 41.79 55.26 (+13.47%) 40.38 49.07 (+8.69%) Average read latency (nanoseconds) 279.82 205.00 (-26.7%) 287.42 158.04 (-45.0%) Read / write inversion count 786 316 884 350

[0046] The data failure rate in the second column of the table represents the proportion of read and write instructions that experienced data failures out of all instructions. The data bandwidth in the third column shows that the higher the data failure rate, the greater the increase in data transmission bandwidth when using a data feedforward mechanism compared to when not using one. However, the data path utilization rate (the proportion of data transmission time to total system operation time) in the fourth column, located between the instruction sequencing circuit and the memory circuit, did not increase synchronously because data feedforward did not utilize this data path; instead, it decreased due to the increase in the data failure rate.

[0047] Conversely, the average read latency and read reversal count in columns 5 and 6 of the table above are reduced due to the use of the data feedforward mechanism, and the reduction is greater when the data failure rate is higher.

[0048] Therefore, the memory control circuit with data feedforward mechanism of the present invention can receive the written data as read data by the data writing circuit when a data failure occurs, avoiding the postponement of data read instructions and read-write reversal in order to process data write instructions first, greatly reducing the latency caused by these behaviors, and improving the performance of the memory control circuit in performing read and write operations.

[0049] Please refer to Figure 5. Figure 5 shows a flowchart of a memory control circuit operation method 500 with a data feedforward mechanism according to one embodiment of the present invention.

[0050] In addition to the aforementioned device, the present invention also discloses a memory control circuit operation method 500, which is applied to, for example, but not limited to, the memory control circuit 120 of FIG. 2A. One embodiment of the memory control circuit operation method 500 is shown in FIG. 5, and includes the following steps.

[0051] In step S510, the data writing circuit 200 stores the corresponding data writing instruction WDC and the write data WDA, and sets the data fault flag DHF in the storage space corresponding to the data writing instruction WDC.

[0052] In step S520, the data read instruction RDC is stored by the data read circuit 210.

[0053] In step S530, the comparison circuit 230 compares the read address of the data read instruction with the write address of the data write instruction. If the timing of the data read instruction RDC is later than that of the data write instruction WDC and the read address and write address are the same, it is determined that a data failure has occurred.

[0054] In step S540, when a data failure occurs, the data reading circuit 210 receives the write data WDA from the data writing circuit 200 as read data, and does not transmit the data read instruction RDC to the memory circuit 130.

[0055] In step S550, when a data fault occurs, the data writing circuit 200 sets the data fault flag to a fault state to prevent the storage space from being overwritten, and after the data write instruction WDC is processed and the write data WDA is written to the memory circuit 130, the data fault flag DHF is set to a non-fault state.

[0056] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0057] In summary, the memory control circuit and its operation method with a data feedforward mechanism in this invention, when a data failure occurs, allows the data writing circuit to receive the data to be read as data, avoiding the postponement of data reading instructions and read-write reversal in order to process data writing instructions first, greatly reducing the latency caused by these behaviors, and improving the efficiency of the memory control circuit in performing read and write operations.

[0058] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0059] 100: Computer System 110: Processor 120: Memory control circuit 130: Memory Circuit 200: Data writing circuit 202: Instruction storage circuit 204: Data storage circuit 206: Processing Circuit 210: Data Reading Circuit 212: Instruction storage circuit 214: Data storage circuit 216: Processing Circuit 220: Data Reading Multiplexer 230: Comparison Circuit 240: Physical layer circuit 250: Instruction Sequencing Circuit 300: Data Write Command 310: Write data 320: Read data 400: Data read command 410: Cancel selection 420: Return Data 430: Write data 440: Read data 500: Memory Control Circuit Operation Method S510~S550: Steps CLK: Working clock COM: Command Path DAP, DAT, DRT: Data Path DHF: Data Hazard Flag RDA: Read Data RDC: Data Read Command TDA: Data Return WDA: Write Data WDC: Data Write Command

Claims

1. A memory control circuit with a data forwarding mechanism, configured to access a memory circuit, comprising: a data write circuit storing a corresponding data write instruction and a write data, and setting a data hazard flag for a storage space corresponding to the data write instruction; a data read circuit storing a data read instruction; and a comparison circuit comparing a read address of the data read instruction with a write address of the data write instruction, to determine that a data hazard condition has occurred when the timing of the data read instruction is later than the timing of the data write instruction and the read address is the same as the write address; wherein when the data hazard condition occurs, the data read circuit receives the write data as read data from the data write circuit, and does not transmit the data read instruction to the memory circuit; When a data failure occurs, the data writing circuit sets the data failure flag to a failure state to prevent the storage space from being overwritten, and sets the data failure flag to a non-failure state after the data writing instruction is processed and the data is written to the memory circuit.

2. The memory control circuit as described in claim 1 further comprises: a physical layer circuit electrically coupled to the memory circuit; and an instruction sequencing circuit configured to: during a data write operation, write data to the memory circuit through the physical layer circuit according to the data write instruction of the data write circuit and the write data; and during a data read operation, read data from the memory circuit through the physical layer circuit according to the data read instruction indicating that no data failure has occurred in the data read circuit, and transmit a feedback data received from the memory circuit through the physical layer circuit to the data read circuit accordingly.

3. The memory control circuit as described in claim 2 further comprises: a data read multiplexer electrically coupled to the data write circuit, the instruction sorting circuit, and the data read circuit, for selecting the data write circuit to receive the written data as the read data when the data failure occurs, and selecting the instruction sorting circuit to receive the feedback data from the memory circuit as the read data when the data failure does not occur.

4. The memory control circuit as described in claim 2, wherein the data writing circuit further comprises: an instruction storage circuit; a data storage circuit; and a processing circuit, which, upon receiving the data writing instruction and the write data, stores the data writing instruction in the instruction storage circuit and the write data in the data storage circuit, wherein the storage space is a part of the instruction storage circuit; wherein the processing circuit sets a data hazard flag corresponding to the storage space, and transmits the data writing instruction and the write data to the instruction sorting circuit when the instruction sorting circuit performs the data writing operation.

5. The memory control circuit as described in claim 4, wherein the comparison circuit is the processing circuit of the data writing circuit.

6. The memory control circuit as described in claim 2, wherein the data read circuit further comprises: an instruction storage circuit; a data storage circuit; and a processing circuit, which, upon receiving the data read instruction, stores the data read instruction in the instruction storage circuit, so as to transmit the data read instruction to the instruction sorting circuit when the instruction sorting circuit performs the data write operation and the data failure condition does not occur, and not transmit the data read instruction to the memory circuit when the data failure condition occurs; wherein the processing circuit stores the read data in the data storage circuit upon receiving the read data.

7. The memory control circuit as described in claim 2, wherein when a data failure occurs and the data read operation is performed, the instruction sequencing circuit controls the physical layer circuit to deselect the memory circuit at a point in time when the data read circuit receives the written data from the data write circuit, so as not to transmit the data read instruction to the memory circuit.

8. The memory control circuit as described in claim 2, wherein the instruction sequencing circuit continuously controls the physical layer circuit to write data to the memory circuit when the data failure occurs and the data write operation is performed.

9. A method for operating a memory control circuit with a data feedforward mechanism, configured to access a memory circuit, comprising: storing a corresponding data write instruction and write data by a data write circuit, and setting a data failure flag for a storage space corresponding to the data write instruction; storing a data read instruction by a data read circuit; and comparing a read address of the data read instruction with a write address of the data write instruction by a comparison circuit, to determine that a data failure condition has occurred when the timing of the data read instruction is later than the timing of the data write instruction and the read address is the same as the write address; When a data failure occurs, the data read circuit receives the write data as read data from the data write circuit and does not transmit the data read command to the memory circuit; and when a data failure occurs, the data write circuit sets the data failure flag to a failure state to prevent the storage space from being overwritten, and sets the data failure flag to a non-failure state after the data write command is processed and the write data is written to the memory circuit.

10. The memory control circuit operation method as described in claim 9 further comprises: when an instruction sequencing circuit performs a data write operation, writing data to the memory circuit according to the data write instruction of the data write circuit and the write data through a physical layer circuit electrically coupled to the memory circuit; and when the instruction sequencing circuit performs a data read operation, reading data from the memory circuit through the physical layer circuit according to the data read instruction indicating that no data failure has occurred in the data read circuit, and transmitting feedback data received from the memory circuit through the physical layer circuit to the data read circuit accordingly.

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