Chip data transfer interface and semiconductor device

Abstract

A chip data transfer interface and a semiconductor device are described herein. The chip data transfer interface includes a data receiving circuit, a data transfer circuit, a clock supply circuit and a phase modulation circuit. The data receiving circuit is configured to receive a parallel input data according to a first operation clock and send a parallel output data. The data transfer circuit is coupled to the data receiving circuit and is configured to receive parallel output data according to a second operation clock and send out a serial data. The clock supply circuit is coupled to the data receiving circuit and the data transfer circuit. The clock supply circuit is configured to generate a system clock and a second operation clock according to a source clock. The phase modulation circuit is coupled to the data receiving circuit and the clock supply circuit. The phase modulation circuit is configured to receive the system clock and the first operation clock, and make a phase of the first operation clock and a phase of the system clock are in phase. When the phase of the first operation clock and the phase the system clock are in phase, the clock supply circuit is configured to output a second operation clock, and the second operation clock is synchronized with the first operation clock.

Description

[Technical Field]

[0001] The present invention relates to a chip data transmission interface, and more particularly to a chip data transmission interface for providing digital data transmission and a semiconductor device having the chip data transmission interface. [Previous Technology]

[0002] Dynamic Voltage / Frequency Scaling is an intelligent load management technology that dynamically adjusts the voltage and operating frequency supplied to the chip based on its current workload. For example, when the chip is idle or under low load, Dynamic Voltage / Frequency Scaling reduces the voltage and operates the chip at a lower frequency, thereby reducing power consumption. On the other hand, when the chip needs to perform high-intensity operations or is in operation, Dynamic Voltage / Frequency Scaling increases the voltage and operates the chip at a higher frequency to meet performance requirements. [Summary of the Invention]

[0003] The present invention provides a chip data transmission interface and a semiconductor device for correcting signal delay caused by dynamic voltage / frequency regulation to ensure that digital data transmission can be performed correctly.

[0004] The chip data transmission interface of the present invention includes a data receiving circuit, a data transmission circuit, a clock supply circuit, and a phase modulation circuit. The data receiving circuit is configured to receive parallel input data and output parallel output data according to a first operating clock. The data transmission circuit is coupled to the data receiving circuit and configured to receive parallel output data and output sequence data according to a second operating clock. The clock supply circuit is coupled to the data receiving circuit and the data transmission circuit. The clock supply circuit is configured to generate a system clock and a second operating clock according to a source clock. The phase modulation circuit is coupled to the data receiving circuit and the clock supply circuit. The phase modulation circuit is configured to receive the system clock and the first operating clock and to make the phase of the first operating clock coincide with the phase of the system clock. Wherein, when the phase of the first operating clock coincides with the phase of the system clock, the clock supply circuit is configured to output a second operating clock, and the second operating clock is synchronized with the first operating clock.

[0005] The semiconductor device of the present invention includes a first wafer and a second wafer. The first wafer has a wafer data transmission interface. The second wafer is coupled to the wafer data transmission interface. The wafer data transmission interface includes: a data receiving circuit, a data transmission circuit, a clock supply circuit, and a phase modulation circuit. The data receiving circuit is configured to receive parallel input data and output parallel output data according to a first operating clock. The data transmission circuit is coupled to the data receiving circuit and configured to receive parallel output data and output sequence data according to a second operating clock. The clock supply circuit is coupled to the data receiving circuit and the data transmission circuit. The clock supply circuit is configured to generate a system clock and a second operating clock according to a source clock. The phase modulation circuit is coupled to the data receiving circuit and the clock supply circuit. The phase modulation circuit is configured to receive the system clock and the first operating clock and to synchronize the phase of the first operating clock with the phase of the system clock. When the first operating clock is in phase with the system clock, the clock supply circuit is configured to output a second operating clock, and the second operating clock is synchronized with the first operating clock.

[0006] Based on the above, the chip data transmission interface and semiconductor device of the present invention can keep the phase of the system clock and the first operating clock locked. Therefore, data can be transmitted normally through the chip data transmission interface. In other words, the chip data transmission interface can ensure that the setup / holding timing margin of the chip data transmission interface is not affected while reducing power consumption by using dynamic voltage / frequency regulation, thereby enabling correct digital data transmission.

[0007] To make the foregoing easier to understand, several embodiments are described in detail below with reference to the figures.

Implementation Method

[0008] The following description will refer to the embodiments of this disclosure shown in the accompanying drawings to assist the reader in fully understanding the methods, apparatus, and / or systems described herein. Therefore, those skilled in the art may suggest various changes, modifications, or equivalent substitutions to the systems, apparatus, and / or methods described herein. Additionally, for clarity and conciseness, descriptions of well-known functions and constructions may be omitted. Furthermore, where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0009] Dynamic voltage / frequency regulation is an intelligent load management technology that dynamically adjusts the voltage supplied to the chip and the chip's operating frequency according to the chip's current workload. It is worth noting that when dynamic voltage / frequency regulation is in operation, the temperature of the chip's silicon junction also changes. For the chip's data interface, dynamic voltage / frequency regulation often causes additional digital latency, which affects the setup / hold timing margin of the data interface, potentially leading to incorrect data transmission.

[0010] This disclosure involves placing a phase modulation circuit within the data transmission interface of the chip to adjust the clock phase in the data transmission interface, ensuring that the data transmission interface is not affected by digital delay. In this way, during dynamic voltage / frequency regulation operation, the chip can ensure that the setup / hold timing margin of the data transmission interface is not affected, thereby enabling correct digital data transmission.

[0011] FIG1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 1 includes a first chip 10 and a second chip 12, wherein the first chip 10 has a first chip data transmission interface 200 (or chip data transmission interface) and is coupled to the second chip 12 through the first chip data transmission interface 200. Thus, the first chip 10 can transmit a first output data signal D_OUT1 to the second chip 12 through the chip data transmission interface 200. Alternatively, the second chip 12 may also be provided with a second chip data transmission interface 202 (or chip data transmission interface) and is coupled to the first chip 10 through the second chip data transmission interface 202. Thus, the second chip 12 can transmit a second output data signal D_OUT2 to the first chip 10 through the second chip data transmission interface 202.

[0012] FIG2 is a schematic diagram of a chip data transmission interface according to an embodiment of the present invention.

[0013] In Figure 2, the chip data transmission interface 200 includes a data receiving circuit 210, a data transmission circuit 240, a clock supply circuit 250, and a phase modulation circuit 230. The data receiving circuit 210 receives parallel input data PD_IN and outputs parallel output data PD_OUT according to a first operating clock CLK1. The data transmission circuit 240 is coupled to the data receiving circuit 210 and receives parallel output data PD_OUT and outputs sequence data SD_OUT according to a second operating clock CLK2. The clock supply circuit 250 is coupled to the data receiving circuit 210 and the data transmission circuit 240, and generates a system clock CLK_S1 and a second operating clock CLK2 according to a source clock CLK_SRC. Phase modulation circuit 230 is coupled to data receiving circuit 210 and clock supply circuit 250. Phase modulation circuit 230 is configured to receive system clock CLK_S1 and first operating clock CLK1, and to make the first operating clock CLK1 in phase with system clock CLK_S1. When the first operating clock CLK1 and system clock CLK_S1 are in phase, clock supply circuit 250 outputs second operating clock CLK2 to data transmission circuit 240, and second operating clock CLK2 is synchronized with first operating clock CLK1.

[0014] Referring again to Figure 2. When the clock supply circuit 250 receives a reset signal TX_RESET, it immediately generates a system clock CLK_S1 based on the source clock CLK_SRC. The system clock CLK_S1 is then converted into a first operating clock CLK1 by the phase modulation circuit 230 and a digital delay 220 for use by the data receiving circuit 210. At this time, there is a slight phase difference between the first operating clock CLK1 and the system clock CLK_S1. In addition, the first operating clock CLK1 is also sent to the clock supply circuit 250 to drive the clock supply circuit 250, causing the clock supply circuit 250 to output a second operating clock CLK2 synchronized with the first operating clock CLK1 for use by the data transmission circuit 240. In this way, the data transmission circuit 240 can successfully receive the parallel output data PD_OUT sent from the data receiving circuit 210 based on the second operating clock CLK2.

[0015] However, in the aforementioned operation, the chip data transmission interface 200 may experience excessive digital delay 220 due to the operation of dynamic voltage / frequency regulation. Excessive digital delay 220 will amplify the phase difference between the first operating clock CLK1 and the system clock CLK_S1, which will prevent the data transmission circuit 240 from successfully receiving the parallel output data PD_OUT sent from the data receiving circuit 210 based on the second operating clock CLK2. The excessive digital delay 220 mentioned above may be due to the delay generated by the chip data transmission interface 200 during dynamic voltage / frequency regulation operation. However, this is not the only possibility; other factors may also cause excessive digital delay 220 between the first operating clock CLK1 and the system clock CLK_S1.

[0016] Referring again to Figure 2. The phase modulation circuit 230 provided in the chip data transmission interface 200 can be used to solve the data transmission problem caused by the excessive digital delay 220 mentioned above. The phase modulation circuit 230 adjusts the received system clock CLK_S1 and the first operating clock CLK1 according to calculations so that the phase of the first operating clock CLK1 and the system clock CLK_S1 can be synchronized, that is, in phase. At this time, the clock supply circuit 250 outputs a second operating clock CLK2, which is synchronized with the first operating clock CLK1, to the data transmission circuit 240 according to the first operating clock CLK1. In this way, the data transmission circuit 240 can correctly receive the parallel output data PD_OUT sent from the data receiving circuit 210 based on the second operating clock CLK2.

[0017] Furthermore, when an excessive digital delay 220 occurs, the operation of the phase modulation circuit 230 can maintain the first operating clock CLK1 and the system clock CLK_S1 in phase without being affected, allowing the data transmission circuit 240 to continue and correctly receive the parallel output data PD_OUT sent from the data receiving circuit 210 based on the second operating clock CLK2. In other words, the chip data transmission interface 200 can ensure that the setup / hold timing margin is not affected while reducing power consumption by using dynamic voltage / frequency regulation, thereby enabling correct digital data transmission.

[0018] Referring again to Figure 2. The clock supply circuit 250 includes a first frequency divider 256, a second frequency divider 252, and a reset and synchronization circuit 254. The first frequency divider 256 generates a system clock CLK_S1 based on the source clock CLK_SRC. The second frequency divider 252 generates a second operating clock CLK2 based on the source clock CLK_SRC. The reset and synchronization circuit 254 is coupled to the first frequency divider 256 and the second frequency divider 252. The reset and synchronization circuit 254 enables the first frequency divider 256 based on the reset signal TX_RESET, causing the first frequency divider 256 to output the system clock CLK_S1. In addition, the reset and synchronization circuit 254 can enable the second frequency divider 252 when the system clock CLK_S1 and the first operating clock CLK1 are in phase, causing the second frequency divider 252 to output the second operating clock CLK2.

[0019] Referring again to Figure 2. The phase modulation circuit 230 includes a phase detector 232, a phase adjustment controller 234, and a phase adjuster 236. The phase detector 232 detects the phase difference between the system clock CLK_S1 and the first operating clock CLK1, and outputs a detection signal DET based on the phase difference. Further, the detection signal DET can be configured to indicate the phase relationship between the system clock CLK_S1 and the first operating clock CLK1, for example, leading or lagging. In other words, the phase detector 232 can be configured to output the detection signal DET in response to the phase of the system clock CLK_S1 leading or lagging the phase of the first operating clock CLK1.

[0020] The phase adjustment controller 234 is coupled to the phase detector 232 and outputs a control signal CTRL according to the detection signal DET. The phase adjuster 236 is coupled to the phase adjustment controller 234 and the clock supply circuit 250, and receives the system clock CLK_S1 from the clock supply circuit 250. It adjusts the phase of the system clock CLK_S1 according to the control signal CTRL, and then outputs an adjusted system clock CLK_S2. The adjusted system clock CLK_S2 is digitally delayed by 220 to form the first operating clock CLK1.

[0021] In other words, in order to maintain the phase consistency between the system clock CLK_S1 and the first operating clock CLK1, when the digital delay 220 occurs and causes the phase of the first operating clock CLK1 to shift, the phase modulation circuit 230 will adjust the first operating clock CLK1 accordingly based on the change in the digital delay 220, so that the phase of the first operating clock CLK1 and the system clock CLK_S1 can be restored to consistency.

[0022] It should be noted that the phase detector 232, the phase adjustment controller 234 and the phase adjuster 236 can be implemented by circuits, but this disclosure does not limit the detailed circuit structure.

[0023] Referring again to Figure 2. The data transmission circuit 240 includes a parallel-to-serial converter 242 and a transmission driver 244. The parallel-to-serial converter 242 is coupled to the data receiving circuit 210 to convert parallel output data PD_OUT into sequential data SD_OUT. The transmission driver 244 is coupled to the parallel-to-serial converter 242 to receive the sequential data SD_OUT and send an output data signal D_OUT.

[0024] Refer to FIG. 2. The system clock CLK_S1 passes through the phase adjuster 236, and the system clock CLK_S1 may initially carry an initial code. The initial code can be configured to indicate the phase of the system clock CLK_S1. For example, when the phase adjuster 236 is a phase interpolator, the initial code may include a quadrant code qrt[1:0] and a phase code phase_code (not shown). In one embodiment, the quadrant code qrt[1:0] may be configured to indicate the phase quadrant of the signal, and the phase code phase_code may be configured to indicate the phase angle of the signal. Alternatively, when the phase adjuster 236 is a delay line, the initial code may include the number of buffers enabled by the delay line for delaying. However, this disclosure is not limited thereto. Furthermore, after the system clock CLK_S1 passes through the phase adjuster 236, the phase adjuster 236 applies an initial delay T_ini (not shown) (e.g., analog delay) to the system clock CLK_S1 to generate the adjusted system clock CLK_S2.

[0025] Then, the adjusted system clock CLK_S2, after a digital delay of 220, becomes the first operating clock CLK1. It should be noted that the digital delay 220 may be caused by the delay due to dynamic voltage / frequency regulation of the digital circuit. Furthermore, the digital delay 220 may also be caused by the delay caused by the buffer required to transmit the system clock CLK_S1 to the data receiving circuit 210. However, this disclosure is not limited to this.

[0026] Next, the first operating clock CLK1 is transmitted back to the phase modulation circuit 230 and the clock supply circuit 250. More specifically, the first operating clock CLK1 is provided to the phase detector 232 and the reset and synchronization circuit 254. The phase detector 232 can be configured to compare the phase relationship between the first operating clock CLK1 and the system clock CLK_S1 to generate a detection signal DET.

[0027] In one embodiment, the detection signal DET may include a phase-leading signal P_LEAD and a phase-lag signal P_LATE (not shown). For example, in response to the first operating clock CLK1 leading the system clock CLK_S1, the detection signal DET may be configured to indicate the phase-leading signal P_LEAD. On the other hand, in response to the first operating clock CLK1 lagging the system clock CLK_S1, the detection signal DET indicates the phase-lag signal P_LATE. That is, when the first operating clock CLK1 leads, the phase-leading signal P_LEAD is enabled, while the phase-lag signal P_LATE is disabled. Conversely, when the first operating clock CLK1 lags, the phase-lag signal P_LATE is enabled, while the phase-leading signal P_LEAD is disabled.

[0028] The detection signal DET is provided to the phase adjustment controller 234. In one embodiment, the phase adjustment controller 234 may be configured to output a control signal CTRL based on the detection signal DET. Furthermore, the control signal CTRL is configured to control the phase adjuster 236 to adjust the phase of the system clock CLK_S1, thereby changing the phases of the adjusted system clock CLK_S2 and the first operating clock CLK1 so that the phase of the first operating clock CLK1 can be aligned with the system clock CLK_S1. For example, the control signal CTRL may include the target phase to be adjusted to or the expected phase difference. And, when the phase adjuster 236 is a phase interpolator, the control signal CTRL may include the quadrant code qrt[1:0] (i.e., the phase quadrant) and the phase code phase_code (i.e., the phase angle) (not shown). Alternatively, when the phase adjuster 236 is a delay line, the control signal CTRL may include the number of buffers enabled by the delay line for delay purposes.

[0029] Regardless of whether a delay line or a phase interpolator is used for analog delay, the delay applied to the system clock CLK_S1 by the phase adjuster 236 aims to align the phase of the first operating clock CLK1 with that of the system clock CLK_S1. Using the comparison result (i.e., leading or lagging) from the phase detector 232, the phase adjustment controller 234 can adjust the phase output of the phase adjuster 236 until the phases of the first operating clock CLK1 and the system clock CLK_S1 are phase-locked. Furthermore, the phase adjustment controller 234 has a voting decision-making mechanism and overflow judgment processing to avoid misjudgments caused by high-frequency data jitter and unequal sampling intervals.

[0030] After phase locking, the reset and synchronization circuit 254 enables the second frequency divider 252 according to the first operating clock CLK1, causing the second frequency divider 252 to divide the source clock CLK_SRC, thereby generating a second operating clock CLK2 synchronized with the first operating clock CLK1. That is, the first operating clock CLK1 and the second operating clock CLK2 will be synchronized and maintain a fixed phase relationship at this time. Therefore, the chip data transmission interface 200 can have a safe setup / hold timing margin, thereby enabling correct digital data transmission.

[0031] When the chip data transmission interface 200 needs to reduce power consumption by performing dynamic voltage / frequency adjustment, the system timing will inevitably be changed (i.e., digital delay 220). At this time, the phase detector 232 will detect that the phase lock between the first operating clock CLK1 and the system clock CLK_S1 is lost. The phase adjustment controller 234 will use the comparison result of the phase detector 232 to control the phase adjuster 236 to continuously adjust the phase of the first operating clock CLK1 until the phase lock between the first operating clock CLK1 and the system clock CLK_S1 is regained. In this way, by using this offset correction method, the first operating clock CLK1 and the second operating clock CLK2 will be synchronized and maintain a fixed phase relationship, and will not be affected by the digital delay 220, thereby ensuring that the setup / hold time margin on the chip data transmission interface 200 is not affected, and thus digital data transmission can be performed correctly.

[0032] Figure 3 is a schematic diagram of the operation scenario of a phase adjustment circuit according to an embodiment of the present invention. When the phase interpolator is used as an embodiment of the phase adjuster 236, the operation scenario 300 of Figure 3 presents the relationship between the phase of the adjusted system clock CLK_S2 and the control signal CTRL in Figure 2, wherein the phase of the adjusted system clock CLK_S2 can be divided into four quadrants. In the first quadrant, the phase of the adjusted system clock CLK_S2 can be 0 degrees to 90 degrees; in the second quadrant, the phase of the adjusted system clock CLK_S2 can be 90 degrees to 180 degrees; in the third quadrant, the phase of the adjusted system clock CLK_S2 can be 180 degrees to 270 degrees; and in the fourth quadrant, the phase of the adjusted system clock CLK_S2 can be 270 degrees to 0 degrees. It is worth mentioning that the relationship between the phase of the adjusted system clock CLK_S2 and the control signal CTRL can be different depending on the design.

[0033] Refer to Figures 2 and 3. The control signal CTRL includes quadrant codes qrt[1:0] and phase codes phase_code. By changing the quadrant codes qrt[1:0] and phase codes phase_code, the control signal CTRL can control the phase of the adjusted system clock CLK_S2. More specifically, the quadrant codes qrt[1:0] are used to switch the quadrant corresponding to the phase of the adjusted system clock CLK_S2, while the phase codes phase_code are used to control the phase of the adjusted system clock CLK_S2. For example, when the quadrant code qrt[1:0] is 00, the phase of the adjusted system clock CLK_S2 is set in the first quadrant, and the phase range can be from 0 degrees to 90 degrees. When the phase code phase_code is 31, the phase of the adjusted system clock CLK_S2 is 0 degrees; when the phase code phase_code is 0, the phase of the adjusted system clock CLK_S2 is 90 degrees. In other words, as the phase code phase_code gradually decreases from 31 to 0, the phase of the adjusted system clock CLK_S2 gradually increases from 0 degrees to 90 degrees.

[0034] FIG4A is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention. FIG4B is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention. Referring to FIG2, the operation timing 400A of FIG4A illustrates the case where the first operation clock CLK1 leads the system clock CLK_S1, and the operation timing 400B of FIG4B illustrates the case where the first operation clock CLK1 lags the system clock CLK_S1.

[0035] Please refer to Figure 4A. After the initial delay T_ini applied by the phase adjuster 236, the system clock CLK_S1 becomes the adjusted system clock CLK_S2. Furthermore, after the digital delay 220, the adjusted system clock CLK_S2 becomes the first operating clock CLK1. At this time, since the first rising edge of the first operating clock CLK1 leads the second rising edge of the system clock CLK_S1, it means that the first operating clock CLK1 leads the system clock CLK_S1.

[0036] Therefore, the phase lead signal P_LEAD is enabled. Furthermore, the phase decrease pulse Decrement_Pulse is triggered to decrease the phase of the adjusted system clock CLK_S2, thereby decreasing the phase of the first operating clock CLK1. Further, the phase adjuster 236 is controlled by the quadrant code qrt[1:0] and the phase code phase_code to gradually decrease the phases of the adjusted system clock CLK_S2 and the first operating clock CLK1 until the phases of the first operating clock CLK1 and the system clock CLK_S1 are synchronized.

[0037] Please refer to Figure 4B. After the initial delay T_ini applied by the phase adjuster 236, the system clock CLK_S1 becomes the adjusted system clock CLK_S2. Furthermore, after the digital delay 220, the adjusted system clock CLK_S2 becomes the first operating clock CLK1. At this time, since the first rising edge of the first operating clock CLK1 lags behind the second rising edge of the system clock CLK_S1, it means that the first operating clock CLK1 lags behind the system clock CLK_S1.

[0038] Therefore, the phase lag signal P_LATE is enabled. Furthermore, the phase increase pulse Increment_Pulse is triggered to increment the phase of the adjusted system clock CLK_S2, thereby incrementing the phase of the first operating clock CLK1. Further, the phase adjuster 236 is controlled by the quadrant code qrt[1:0] and the phase code phase_code to progressively increment the phases of the adjusted system clock CLK_S2 and the first operating clock CLK1 until the phases of the first operating clock CLK1 and the system clock CLK_S1 are synchronized.

[0039] Figure 5 is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention. Referring to Figure 2, the operation timing 500 of Figure 5 illustrates the case where the two phases of the first operation clock CLK1 and the system clock CLK_S1 are locked.

[0040] As shown in Figure 5, when the first operating clock CLK1 is unlocked from the system clock CLK_S1, the phase of the first operating clock CLK1 will be incremented or decremented so that the two phases of the first operating clock CLK1 and the system clock CLK_S1 remain locked.

[0041] In this way, the first operating clock CLK1 and the second operating clock CLK2 will be synchronized and maintain a fixed phase relationship, and will not be affected by the digital delay 220, thereby ensuring that the setup / hold time margin on the chip data transmission interface 200 will not be affected, so that digital data transmission can be performed correctly.

[0042] In summary, the chip data transmission interface and semiconductor device of the present invention can keep the phase of the system clock and the first operating clock locked. Therefore, data can be transmitted normally through the chip data transmission interface. That is, the chip data transmission interface can ensure that the setup / holding timing margin of the chip data transmission interface is not affected while reducing power consumption by using dynamic voltage / frequency regulation, thereby enabling correct digital data transmission.

[0043] For those skilled in the art, changes can be made to the above embodiments without departing from the broad inventive concept of this disclosure. Therefore, it should be understood that the invention disclosed herein is not limited to the specific embodiments disclosed, and is intended to cover modifications within the spirit and scope of the invention. [Simplified Explanation of the Diagram]

[0044] FIG1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. FIG2 is a schematic diagram of a chip data transmission interface according to an embodiment of the present invention. FIG3 is a schematic diagram of the operation scenario of a phase modulation circuit according to an embodiment of the present invention. FIG4A is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention. FIG4B is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention. FIG5 is a schematic diagram of the operation timing of a phase modulation circuit according to an embodiment of the present invention.

Claims

1. A chip data transmission interface, comprising: A data receiving circuit is configured to receive a parallel input data and output a parallel output data according to a first operating clock. A data transmission circuit, coupled to the data receiving circuit, is configured to receive the parallel output data according to a second operating clock, and to send out a sequence of data. A clock supply circuit, coupled to the data receiving circuit and the data transmitting circuit, is configured to generate a system clock and a second operating clock based on a source clock; and a phase modulation circuit, coupled to the data receiving circuit and the clock supply circuit, is configured to receive the system clock and the first operating clock and to make the first operating clock phase-synchronized with the system clock; wherein, when the first operating clock and the system clock are phase-synchronized, the clock supply circuit is configured to output the second operating clock, and the second operating clock is synchronized with the first operating clock.

2. The chip data transmission interface as claimed in claim 1, wherein the system clock is formed by the phase modulation circuit and a digital delay to form the first operating clock.

3. The chip data transmission interface as claimed in claim 1, wherein the clock supply circuit includes: A first frequency divider is configured to generate the system clock based on the source clock. A second frequency divider is configured to generate the second operating clock based on the source clock; and a reset and synchronization circuit is coupled to the first frequency divider and the second frequency divider, the reset and synchronization circuit being configured to enable the first frequency divider based on a reset signal, and to enable the second frequency divider when the system clock is in phase with the first operating clock.

4. The chip data transmission interface as claimed in claim 1, wherein the phase modulation circuit includes: A phase detector is configured to detect the phase difference between the system clock and the first operating clock, and output a detection signal based on the phase difference; A phase adjustment controller coupled to the phase detector, the phase adjustment controller being configured to output a control signal based on the detection signal; and a phase adjuster coupled to the phase adjustment controller and the clock supply circuit, the phase adjuster being configured to receive the system clock and adjust the phase of the system clock based on the control signal to output an adjusted system clock.

5. The chip data transmission interface as claimed in claim 4, wherein the adjusted system clock is digitally delayed to form the first operating clock.

6. The chip data transmission interface as claimed in claim 1, wherein the data transmission circuitry includes: A parallel-to-sequence conversion circuit is coupled to the data receiving circuit and configured to convert the parallel output data into the sequence data; and a transmission driver coupled to the parallel-to-sequence circuit, the transmission driver being configured to receive the sequence data and send an output data signal.

7. A semiconductor device, comprising: A first chip has a chip data transmission interface; and a second chip coupled to the chip data transmission interface; wherein the chip data transmission interface includes: a data receiving circuit configured to receive a parallel input data and output a parallel output data according to a first operating clock; a data transmission circuit coupled to the data receiving circuit configured to receive the parallel output data and output a sequence of data according to a second operating clock; a clock supply circuit coupled to the data receiving circuit and the data transmission circuit, the clock supply circuit being configured to generate a system clock and the second operating clock according to a source clock; and a phase modulation circuit coupled to the data receiving circuit and the clock supply circuit, the phase modulation circuit being configured to receive the system clock and the first operating clock and to make the phase of the system clock and the phase of the first operating clock synchronized; wherein, when the phase of the system clock and the phase of the first operating clock are synchronized, the clock supply circuit is configured to output the second operating clock, and the second operating clock is synchronized with the first operating clock.

8. The semiconductor device of claim 7, wherein the system clock is formed by the phase modulation circuit and a digital delay to form the first operating clock.

9. The semiconductor device of claim 7, wherein the clock supply circuit comprises: A first frequency divider is configured to generate the system clock based on the source clock. A second frequency divider is configured to generate the second operating clock based on the source clock; and a reset and synchronization circuit is coupled to the first frequency divider and the second frequency divider, the reset and synchronization circuit being configured to enable the first frequency divider based on a reset signal, and to enable the second frequency divider when the system clock is in phase with the first operating clock.

10. The semiconductor device of claim 7, wherein the phase modulation circuit comprises: A phase detector is configured to detect the phase difference between the system clock and the first operating clock, and output a detection signal based on the phase difference; A phase adjustment controller coupled to the phase detector, the phase adjustment controller being configured to output a control signal based on the detection signal; and a phase adjuster coupled to the phase adjustment controller and the clock supply circuit, the phase adjuster being configured to receive the system clock and adjust the phase of the system clock based on the control signal to output an adjusted system clock.

11. The semiconductor device of claim 10, wherein the adjusted system clock is digitally delayed to form the first operating clock.

12. The semiconductor device of claim 7, wherein the data transmission circuitry comprises: A parallel-to-sequence conversion circuit is coupled to the data receiving circuit and configured to convert the parallel output data into the sequence data; A transmission driver is coupled to the parallel-to-sequence circuit and the second chip. The transmission driver is configured to receive the sequence data and send an output data signal to the second chip.

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