Multiple-chip system and timing synchronization method

Abstract

A multiple-chip system and a timing synchronization method. The multiple-chip system includes a plurality of chips. The plurality of chips includes a first chip and at least one second chip. The plurality of chips connects to each other through same input output bus (I / O bus). The timing synchronization method includes: sequentially transmitting a plurality of detection patterns to the I / O bus through the plurality of chips, wherein sequentially transmitting the detection pattern through each of the at least one second chip, and then transmitting the detection pattern through the first chip; transmitting a synchronization pattern to the I / O bus through the first chip; monitoring the synchronization pattern from I / O bus through each of the at least one second chip; and performing a given function based on the synchronization pattern through each of the plurality of chips.

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