Vector processing circuit and vector processing method

Abstract

The present disclosure proposes a vector processing circuit and a vector processing method. The circuit includes a vector register, a two-dimensional register, and an arithmetic circuit. The vector register is configured to store first data. The two-dimensional register is configured to store second data. The arithmetic circuit is configured to perform a first matrix multiplication operation on the first data and the second data. After executing the first matrix multiplication operation, the vector register is configured to store third data to replace the first data, and the arithmetic circuit is configured to perform a second matrix multiplication operation on the third data and the second data.

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