Analog matrix-matrix multiplier for mixed signal matrix multiplications

Abstract

A compute device architecture includes an array of resistive devices equipped with capacitors holding a charge that stores intermediate results. The array includes signal rows and signal columns that meet at intersections. Signal generators are coupled to the signal rows and signal columns. A read-out circuit is coupled to outputs of the signal rows and signal columns. A controller module is coupled to the signal generators and to the read-out circuit. A set of pulse signals of voltage or resistance are sent through the signal rows and signal columns. Coincidences of pulse signals are detected at intersections of the signal rows and the signal columns. A resultant voltage or resistance is measured at the detected coincidences of pulse signals. A resultant matrix output of the array is updated using the measured resultant voltage or resistance.

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