Tiled electronic device

Abstract

A tiled electronic device is provided and includes a first electronic module and a second electronic module adjacent to the first electronic module. The first electronic module is separated from the second electronic module by a gap along a direction. The tiled electronic device has a first region and a second region, wherein the first region has a first optical performance P1, and the second region has a second optical performance P2. The first optical performance P1 and the second optical performance P2 satisfy following relation: |(P1-P2) / P2|≤5%.

Description

Technical Field

[0001] This disclosure relates to a splicing electronic device, and more particularly to a splicing electronic device having uniform optical performance. Prior Technology

[0002] With the advancement of display technology, when multiple display devices are spliced ​​together to form a large-area display device, the structure in the splicing gap between two adjacent display devices is different from the structure of the display devices. Therefore, the optical performance of the splicing gap will be significantly different from that of the display devices, resulting in uneven optical performance of the entire spliced ​​display device. This makes it easy for users to notice the existence of the splicing gap, thus affecting the visual effect. Summary of the Invention

[0003] One of the purposes of this disclosure is to provide a splicing electronic device to solve the above-mentioned problems.

[0004] One embodiment of this disclosure provides a splicing electronic device, including a first electronic module and a second electronic module. The second electronic module is disposed adjacent to the first electronic module, and the first electronic module and the second electronic module are separated by a gap along a first direction. The splicing electronic device has a first region and a second region. The first region includes a portion of the gap, a first portion of the gap adjacent to the first electronic module, and a second portion of the gap adjacent to the second electronic module. The second region and the first region are arranged along the first direction, wherein the second region includes a third portion of the first portion of the gap adjacent to the first electronic module. The first region has a first optical performance index P1, and the second region has a second optical performance index P2. The first optical performance index P1 and the second optical performance index P2 satisfy the following relationship: |(P1-P2) / P2|≤5%.

[0005] In the splicing electronic device disclosed herein, since the optical performance of the portion corresponding to the center of the electronic module, the portion corresponding to the gap, and the portion corresponding to the portion located between the center of the electronic module and the gap can satisfy the above relationship, the uniformity of the optical performance of the splicing electronic device can be improved, thereby improving the visual effect of the splicing electronic device. Simple Explanation of the Diagram

[0006] Figure 1 is a top view schematic diagram of a splicing electronic device according to a first embodiment of the present disclosure. Figure 2 shows a cross-sectional structural schematic diagram of a region of a spliced ​​electronic device for measuring optical performance according to an embodiment of the present disclosure. Figure 3 shows a cross-sectional view of the splicing electronic device according to the first embodiment of the present disclosure along the section line A-A' of Figure 1. Figure 4 shows a top view schematic diagram of an optical structure according to some embodiments of the present disclosure. Figure 5 shows a cross-sectional schematic diagram of a splicing electronic device according to a first variation of the first embodiment of the present disclosure. Figure 6 shows a cross-sectional schematic diagram of a splicing electronic device according to a second variation of the first embodiment of the present disclosure. Figure 7 shows a cross-sectional schematic diagram of a splicing electronic device according to a third variation of the first embodiment of the present disclosure. Figure 8 shows a cross-sectional schematic diagram of a splicing electronic device according to a fourth variation of the first embodiment of the present disclosure. Figure 9 shows a cross-sectional schematic diagram of a splicing electronic device according to a fifth variation of the first embodiment of the present disclosure. Figure 10 shows a cross-sectional schematic diagram of a splicing electronic device according to a second embodiment of the present disclosure. Figure 11 shows a cross-sectional schematic diagram of a splicing electronic device according to a third embodiment of the present disclosure. Figure 12 shows a cross-sectional view of the splicing electronic device according to the third embodiment of the present disclosure along section line B-B' of Figure 11. Figure 13 shows a top view of a splicing electronic device according to a fourth embodiment of the present disclosure. Figure 14 shows a cross-sectional view of the splicing electronic device according to the fourth embodiment of the present disclosure along the section line C-C' of Figure 13. Implementation

[0007] The present disclosure will be described in detail below with reference to specific embodiments and accompanying drawings. In order to make the disclosure clearer and easier to understand, the accompanying drawings are simplified schematic diagrams, and the components therein may not be drawn to scale. Furthermore, the number and size of the components in the drawings are only illustrative and are not intended to limit the scope of the disclosure.

[0008] Throughout this specification and the accompanying claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components, and this document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "contains" and "including" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0009] The ordinal numbers used in the specification and the request, such as "first" and "second", to modify the elements of the request, do not in themselves imply or represent any prior ordinal number of the requested element, nor do they represent the order of one requested element with another, or the order of manufacturing process. The use of the ordinal numbers is only to enable a request element with a certain name to be clearly distinguished from another request element with the same name.

[0010] Furthermore, when an element or membrane is referred to as being connected to another element or membrane, it should be understood that the element or membrane is directly physically or electrically connected to the other element or membrane, or that the two are physically or electrically connected through other elements or membranes (indirectly). Conversely, when an element or membrane is referred to as being "directly connected" to another element or membrane, it should be understood that the two are not physically or electrically connected through other elements or membranes. The term "connection" can include means of "direct contact" or "indirect contact." Furthermore, the terms "electrical connection" or "coupling" include any direct and indirect electrical connection means.

[0011] In this text, the terms "approximately," "substantially," or "roughly" typically indicate a range within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. The given quantity is approximate; that is, even without specific mention of "approximately," "substantially," or "roughly," the meaning of "approximately," "substantially," or "roughly" can still be implied.

[0012] The term "between value A and value B" is interpreted as including value A and value B, or at least one of value A and value B, as well as other values ​​between value A and value B.

[0013] In this disclosure, the depth, thickness, length, width and aperture can be measured by optical microscope (OM), electron microscope (e.g., scanning electron microscope (SEM)) or other methods, but are not limited thereto.

[0014] In this disclosure, roughness is defined by SEM observation, where the peaks and valleys of surface undulations on an uneven surface have a distance difference of 0.15 micrometers (μm) to 1 μm. Roughness measurement can involve using SEM, transmission electron microscopy (TEM), etc., to observe the surface undulations at an appropriate magnification, and comparing the undulations by taking a sample of unit length (e.g., 10 μm) to determine its roughness range. Here, "appropriate magnification" means that at least one surface can show at least 10 undulation peaks in the field of view at this magnification, indicating a roughness (Rz) or average roughness (Ra).

[0015] It should be understood that the following embodiments can be implemented by substituting, recombining, or mixing features from multiple different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features from different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0017] The splicing electronic devices disclosed herein may include, for example, display devices, light-emitting devices, sensing devices, antenna devices, touch devices, packaging devices, or other suitable electronic devices, but are not limited thereto. The splicing electronic devices may be, for example, bendable, stretchable, foldable, rollable, and / or flexible electronic devices, but are not limited thereto. Display devices may be used, for example, in notebook computers, public displays, splicing displays, automotive displays, touch displays, televisions, monitors, smartphones, tablets, light source modules, lighting equipment, military equipment, or electronic devices used in the aforementioned products, but are not limited thereto. Sensing devices may be, for example, sensing devices for detecting changes in capacitance, light, heat, or ultrasound, but are not limited thereto. Sensing devices may include, for example, biosensors, touch sensors, fingerprint sensors, other suitable sensors, or combinations of sensors of the above types. Display devices may include, for example, liquid crystal molecules, light-emitting diodes (LEDs), fluorescent materials, phosphorescent materials, other suitable display media, or combinations thereof, but are not limited thereto. LEDs may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs (QDs, such as QLEDs and QDLEDs), or other suitable materials, or any arrangement or combination of the above materials, but are not limited thereto. Antenna devices may be, for example, liquid crystal antennas, varactor diode antennas, or other types of antennas, but are not limited thereto. Splicing devices may include, for example, splicing display devices or splicing antenna devices, but are not limited thereto. Furthermore, the shape of the splicing electronic device may be, for example, rectangular, circular, polygonal, with curved edges, curved, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, control system, light source system, and shelving system. It should be noted that the splicing electronic device disclosed herein can be any combination of the above-mentioned devices, but is not limited thereto.

[0018] The following figures illustrate directions D1, D2, and D3. Direction D3 can be the normal direction or the top view direction of the assembled electronic device, as shown in Figure 3. Direction D3 can be perpendicular to an upper surface of a substrate SB1. Directions D1 and D2 can be horizontal and perpendicular to direction D3, as shown in Figure 3. Directions D1 and D2 can be parallel to the upper surface of substrate SB1. The following figures can be used to describe the spatial relationships of the structure based on directions D1, D2, and D3.

[0019] Please refer to Figure 1, which is a top view of a splicing electronic device according to a first embodiment of the present disclosure, wherein the right side of Figure 1 is an enlarged view of a portion of the left side of Figure 1. The splicing electronic device 1 may include a first electronic module 12a and a second electronic module 12b, and the second electronic module 12b may be disposed adjacent to the first electronic module 12a. The first electronic module 12a and the second electronic module 12b may be separated by a gap G1 along a first direction (e.g., direction D1 or direction D2). Furthermore, the splicing electronic device 1 has a first region R1 and a second region R2, wherein the first region R1 includes a portion of the gap G1, a first portion PA1 of the first electronic module 12a adjacent to the gap G1, and a second portion PA2 of the second electronic module 12b adjacent to the gap; the second region R2 is arranged along the first direction with the first region R1, and the second region R2 includes a third portion PA3 of the first electronic module 12a adjacent to the first portion PA1. The first region R1 has a first optical performance P1, and the second region R2 has a second optical performance P2. The first optical performance P1 and the second optical performance P2 can satisfy the relationship (1): |(P1-P2) / P2|≤5%, which can improve the uniformity of the optical performance of the splicing electronic device 1. Therefore, the user is not likely to perceive the visual difference between the first region R1 containing the gap G1 and the second region R2 without the gap G1, thereby improving the visual effect of the splicing electronic device 1. The first direction can be the direction perpendicular to the extension direction of the gap G1 in the top view. The first part PA1 can be the part of the first electronic module 12a outside the gap G1 in the first region R1, the second part PA2 can be the part of the second electronic module 12b outside the gap G1 in the first region R1, and the third part PA3 can be the part of the first electronic module 12a in the second region R2. Furthermore, the diameter of the first region R1 can range from 2 millimeters (mm) to 20 millimeters, that is, the area of ​​the first region R1 can range from 3.142 square millimeters (mm2) to 314.159 square millimeters. In some embodiments, the area (diameter) of the first region R1 and the second region R2 can be the same.

[0020] Specifically, the splicing electronic device 1 may include multiple electronic modules 12 spliced ​​together, with a gap (e.g., gap G1, gap G2, gap G3, or gap G4) separating two adjacent electronic modules 12. In Figure 1, four electronic modules 12 are shown as an example, arranged in an array, but this is not a limitation. The first electronic module 12a and the second electronic module 12b may be, for example, any two adjacent electronic modules 12. The first electronic module 12a and the second electronic module 12b in Figure 1 are shown as arranged in direction D1, but this is not a limitation. In some embodiments, the electronic module 12 may be a transparent electronic module, such as a transparent display device or a transparent display panel, and may be able to present a transparent state, but this is not a limitation. "Transparent" as used herein may refer to the transmittance of the electronic module 12 being greater than 25%. In some embodiments, the electronic module 12 may also be an electronic device with controllable transparency or transmittance, but this is not a limitation.

[0021] The splicing electronic device 1 may further include an optical structure 22, disposed corresponding to the gap (e.g., gap G1), and the optical structure 22 may enable the first optical performance P1 of the first region R1 and the second optical performance P2 of the second region R2 to satisfy the above-mentioned relationship (1), thereby improving the visual effect. In the embodiment of FIG1, the optical structure 22 may be disposed in the gap G1, for example, in the top view of the splicing electronic device 1, but is not limited thereto. In some embodiments, the optical structure 22 may also be disposed in the region adjacent to the gap G1 of each electronic module 12, but is not limited thereto.

[0022] According to this embodiment, the electronic module 12 may further include, for example, a third electronic module 12c and a fourth electronic module 12d, arranged adjacent to each other. The first electronic module 12a and the third electronic module 12c may be adjacent to each other and arranged in a second direction, the second electronic module 12b and the fourth electronic module 12d may be adjacent to each other and arranged in the second direction, and the third electronic module 12c and the fourth electronic module 12d may be separated by another gap G2 along a first direction. The first electronic module 12a and the third electronic module 12c may be separated by another gap G3 along a second direction, and the second electronic module 12b and the fourth electronic module 12d may be separated by another gap G4 along a second direction. In FIG1, the first direction and the second direction may be, for example, direction D1 and direction D2, but are not limited thereto and may be interchanged. Any one of the gaps G1, G2, G3, and G4 may be, for example, the gap G shown in FIG4 to FIG12. In some embodiments, the first electronic module 12a, the second electronic module 12b, the third electronic module 12c, and the fourth electronic module 12d may be, for example, transparent electronic modules, but are not limited thereto. In some embodiments, the transmittance of the first electronic module 12a, the second electronic module 12b, the third electronic module 12c, and the fourth electronic module 12d is greater than 25%.

[0023] It should be noted that, for ease of comparison of the first optical performance of the first region R1 and the second optical performance of the second region R2, the top-view area of ​​the first region R1 can be the same as the top-view area of ​​the second region R2. The top-view shape of the first region R1 can also be, for example, the same as the top-view shape of the second region R2. In Figure 1, the first region R1 and the second region R2 can be circular, but are not limited to this, and can also be other suitable shapes. Different regions mentioned below can also have the same top-view area and the same top-view shape, but are not limited to this.

[0024] As shown in Figure 1, the center of the first region R1 may overlap with the gap G1 in the top view of the splicing electronic device 1, for example, and the second region R2 does not overlap with the first region R1. The position of the second region R2 may be, for example, a position where the first region R1 is moved a distance along direction D1 toward the center of the first electronic module 12a. The distance between the center of the second region R2 and the center of the first region R1 may be, for example, greater than the diameter of the first region R1 and less than or equal to twice the diameter.

[0025] The splicing electronic device 1 may also have a third region R3, wherein the third region R3 includes a fourth portion PA4 adjacent to the center of the first electronic module 12a. Furthermore, the third region R3 does not overlap with the second region R2 in a top view of the splicing electronic device 1. The center of the third region R3 may, for example, be located within a range where the distance from the center of the first electronic module 12a is less than or equal to 1.5 times the diameter of the third region R3. In FIG1, the third region R3, the second region R2, and the first region R1 may, for example, be arranged in direction D1, and the second region R2 may, for example, be located within the range between the first region R1 and the third region R3, but is not limited thereto. The aforementioned fourth portion PA4 may be a portion of the first electronic module 12a within the third region R3. In some embodiments, the areas (diameters) of the first region R1, the second region R2, and the third region R3 may be the same.

[0026] The third region R3 may have a third optical performance rate P3, and the second optical performance rate P2 and the third optical performance rate P3 may satisfy the relationship (2): |(P2-P3) / P3|≤10%, thereby improving the uniformity of the optical performance rate of the portion of the splicing electronic device 1 corresponding to the first electronic module 12a. In some embodiments, |(P1-P2) / P2| may be a first difference, and |(P2-P3) / P3| may be a second difference, and the first difference may be less than or equal to the second difference, so as to improve the uniformity of the optical performance rate of the portion of the splicing electronic device 1 corresponding to the first electronic module 12a and the portion corresponding to the gap. In some embodiments, the first optical performance rate P1 and the third optical performance rate P3 may also satisfy the relationship (3): |(P1-P3) / P3|≤10%, so as to improve the uniformity of the optical performance rate of the portion of the splicing electronic device 1 corresponding to the center of the first electronic module 12a and the portion of the gap. In some embodiments, |(P1-P3) / P3| may be a third difference, and the first difference may be less than or equal to the third difference, so as to improve the uniformity of the optical performance of the portion corresponding to the center of the first electronic module 12a and the portion corresponding to the gap in the splicing electronic device 1.

[0027] The splicing electronic device 1 may also have a fourth region R4, wherein the fourth region R4 may include a portion of the gap G3, a portion of the gap G3 adjacent to the first electronic module 12a, and a portion of the gap G3 adjacent to the third electronic module 12c. The relationship between the optical performance of the fourth region R4 and the optical performance of the third region R3 may be similar to or the same as the relationship between the first optical performance P1 and the third optical performance P3, thus satisfying relation (3), wherein P3 can be replaced by the optical performance of the fourth region R4. In some embodiments, the optical performance of the region located between the fourth region R4 and the third region R3 may also satisfy the above relations (1) and (2), wherein P3 can be replaced by the optical performance of the fourth region R4, and P2 can be replaced by the optical performance of the region located between the fourth region R4 and the third region R3. In some embodiments, the areas (diameters) of the first region R1, the second region R2, the third region R3, and the fourth region R4 may be the same.

[0028] Similarly, the splicing electronic device 1 may also have a fifth region R5, a sixth region R6, a seventh region R7, an eighth region R8, and a ninth region R9. The fifth region R5 includes a portion of the second electronic module 12b near the center of the second electronic module 12b; the sixth region R6 includes a portion of the gap G4, a portion of the second electronic module 12b near the gap G4, and a portion of the fourth electronic module 12d near the gap G4; the seventh region R7 includes a portion of the third electronic module 12c near the center of the third electronic module 12c; the eighth region R8 includes a portion of the gap G2, a portion of the third electronic module 12c near the gap G2, and a portion of the fourth electronic module 12d near the gap G2; and the ninth region R9 includes a portion of the fourth electronic module 12d near the center of the fourth electronic module 12d. The relationships between the optical performance of Zone 5 R5, Zone 1 R1, and the zone between Zone 5 R5 and Zone 1 R1; the relationships between the optical performance of Zone 5 R5, Zone 6 R6, and the zone between Zone 5 R5 and Zone 6 R6; the relationships between the optical performance of Zone 7 R7, Zone 4 R4, and the zone between Zone 7 R7 and Zone 4 R4; the relationships between the optical performance of Zone 7 R7, Zone 8 R8, and the zone between Zone 7 R7 and Zone 8 R8; the relationships between the optical performance of Zone 9 R9, Zone 6 R6, and the zone between Zone 9 R9 and Zone 6 R6; and the relationships between the optical performance of Zone 9 R9, Zone 8 R8, and the zone between Zone 9 R9 and Zone 8 R8. The relationship between the first optical performance rate P1, the second optical performance rate P2, and the third optical performance rate P3 can be similar or identical, thus satisfying the above-mentioned relationships (1), (2), and (3). Among them, P3 can be replaced by the optical performance rate of the fifth region R5, the seventh region R7, or the ninth region R9. P2 can be replaced by the optical performance rate of the region located between the fifth region R5 and the first region R1, the region located between the fifth region R5 and the sixth region R6, the region located between the seventh region R7 and the fourth region R4, the region located between the seventh region R7 and the eighth region R8, the region located between the ninth region R9 and the sixth region R6, or the region located between the ninth region R9 and the eighth region R8. P1 can be replaced by the optical performance rate of the fourth region R4, the sixth region R6, or the eighth region R8.

[0029] According to this embodiment, the optical structure 22 can also be configured corresponding to gaps G2, G3, and G4, so that the optical performance of the fifth region R5, the sixth region R6, the seventh region R7, the eighth region R8, and the ninth region R9 can satisfy the above-mentioned relationships (1), (2), and (3), thereby improving the visual effect. In the embodiment of FIG1, the optical structure 22 can be configured in gaps G2, G3, and G4, for example, in the top view of the splicing electronic device 1. In some embodiments, the optical structure 22 can also be configured in the region adjacent to gaps G2, G3, and G4 of each electronic module 12, but is not limited thereto. In some embodiments, the area (diameter) of the first region R1 to the ninth region R9 can be the same.

[0030] The splicing electronic device 1 may also have a tenth region R10, an eleventh region R11, and a twelfth region R12. The tenth region R10 may include a portion of gap G2, a portion of gap G2 adjacent to the third electronic module 12c, and a portion of gap G2 adjacent to the fourth electronic module 12d. The eleventh region R11 may be located at the junction of gaps G1, G2, G3, and G4, and includes a portion of gap G1, a portion of gaps G1 and G3 adjacent to the first electronic module 12a, a portion of gaps G1 and G4 adjacent to the second electronic module 12b, a portion of gap G2, a portion of gap G2 adjacent to the third electronic module 12c, a portion of gaps G2 and G3 adjacent to the fourth electronic module 12d, a portion of gap G3, and a portion of gap G4. The twelfth region R12 may include a portion of gap G1, a portion of gap G1 adjacent to the first electronic module 12a, and a portion of gap G1 adjacent to the second electronic module 12b, and is different from the first region R1. In Figure 1, the twelfth region R12, the first region R1, the eleventh region R11, the eighth region R8, and the tenth region R10 are arranged sequentially along a second direction (e.g., direction D2). Along direction D2, the maximum value Pmax1, minimum value Pmin1, and average value Pave1 of the optical performance of the twelfth region R12, the first region R1, the eleventh region R11, the eighth region R8, and the tenth region R10 satisfy the relationship (4): |(Pmax1-Pmin1) / Pave1|≤5%. In other words, the uniformity of the optical performance of the splicing electronic device 1 corresponding to the portions of gaps G1 and G2 extending along direction D2 can be improved. In some embodiments, the areas (diameters) of the first region R1 to the twelfth region R12 may be the same.

[0031] The splicing electronic device 1 may also have a thirteenth region R13 and a fourteenth region R14, wherein the thirteenth region R13 may include a portion of gap G3, a portion of gap G3 adjacent to the first electronic module 12a, and a portion of gap G3 adjacent to the third electronic module 12c, and the fourteenth region R14 may include a portion of gap G4, a portion of gap G4 adjacent to the second electronic module 12b, and a portion of gap G4 adjacent to the fourth electronic module 12d. In Figure 1, the thirteenth region R13, the fourth region R4, the eleventh region R11, the sixth region R6, and the fourteenth region R14 are arranged sequentially along a first direction (e.g., direction D1). In direction D1, the maximum value Pmax2, the minimum value Pmin2, and the average value Pave2 of the optical performance of the thirteenth region R13, the fourth region R4, the eleventh region R11, the sixth region R6, and the fourteenth region R14 can satisfy the relationship (5): |(Pmax2-Pmin2) / Pave2|≤5%. Therefore, the uniformity of the optical performance of the splicing electronics 1 corresponding to the portions of gaps G3 and G4 extending along direction D1 can be improved. In some embodiments, the areas (diameters) of the first region R1 to the fourteenth region R14 may be the same.

[0032] In some embodiments, the maximum value Pmax3, minimum value Pmin3, and average value Pave3 of the optical performance of the corresponding gaps in the twelfth zone R12, the first zone R1, the eleventh zone R11, the eighth zone R8, the tenth zone R10, the thirteenth zone R13, the fourth zone R4, the eleventh zone R11, the sixth zone R6, and the fourteenth zone R14 can satisfy the relationship (5): |(Pmax3-Pmin3) / Pave3|≤5%. In other words, the uniformity of the optical performance of the splicing electronic device 1 corresponding to the portions of gaps G3 and G4 extending along direction D1 and gaps G1 and G2 extending along direction D2 can be improved. In some embodiments, the average value Pave1 in direction D2, the average value Pave2 in direction D1, and the average value Pave3 can satisfy the relationship (6): |(Pave1-Pave2) / Pave3|≤5%.

[0033] In some embodiments, the first optical performance rate P1 of the first region R1, the third optical performance rate P3 of the third region R3, and the optical performance rate P5 of the fifth region R5 can satisfy the following relationship (7): 95%≤|P3-P1| / |P5-P1|≤105%. Similarly, the relationship between the optical performance rates of the seventh region R7, the eighth region R8, and the ninth region R9, the relationship between the optical performance rates of the third region R3, the fourth region R4, and the seventh region R7, and the relationship between the optical performance rates of the fifth region R5, the sixth region R6, and the ninth region R9 can be similar to or the same as the relationship between the optical performance rates of the first region R1, the third region R3, and the fifth region R5, and can satisfy the relationship (7), wherein P1 can be replaced by the optical performance rate of the fourth region R4, the sixth region R6, or the eighth region R8, P3 can be replaced by the optical performance rate of the seventh region R7 or the fifth region R5, and P5 can be replaced by the optical performance rate of the seventh region R7 or the ninth region R9.

[0034] In some embodiments, the maximum value Pmax4, minimum value Pmin4, and average value Pave4 of the optical performance of the first region R1, the third region R3, the fifth region R5, the eleventh region R11, the seventh region R7, the eighth region R8, and the ninth region R9 can satisfy the relationship (8): |(Pmax4-Pmin4) / Pave4|≤5%. Similarly, the optical performance of the fourth region R4, the third region R3, the seventh region R7, the eleventh region R11, the sixth region R6, the fifth region R5, and the ninth region R9 can also satisfy the relationship (8).

[0035] It should be noted that, since the optical structure 22 can be configured to correspond to gaps G1, G2, G3, and G4, the optical performance of the first zone R1 to the fourteenth zone R14 can satisfy the above relationship, thereby improving the visual effect. The optical performance will be further described below.

[0036] In some embodiments, the optical performance of regions R1 to R14 can all be transmittance, all be reflectance, a combination of transmittance and reflectance, chromaticity, or other visual perception characteristics. Please refer to Figure 2, which shows a cross-sectional structural schematic diagram of measuring the optical performance of a region of a splicing electronic device according to an embodiment of this disclosure. As shown in Figure 2, the splicing electronic device 1 can be disposed in a detection device 14. In Figure 2, the optical performance is exemplified by a combination of transmittance and reflectance. The detection device 14 may include, for example, a light source 16a, a light source 16b, and a photosensor 18. During detection, the light source 16a and the photosensor 18 can be disposed on the upper and lower sides of the splicing electronic device 1, respectively, and the light source 16b and the photosensor 18 can be disposed on the same side of the splicing electronic device 1. The light beam L1 generated by the light source 16a can pass through the region to be detected by the splicing electronic device 1 and be received by the photosensor 18. The light beam L2 generated by the light source 16b can be received by the photosensor 18 via reflection from the region to be detected by the splicing electronic device 1. Therefore, the photosensor 18 can simultaneously receive the light beam L1 passing through the splicing electronics 1 and the light beam L2 reflected by the splicing electronics 1. In this case, the light intensity received by the photosensor 18 can represent the optical performance of the area to be detected by the splicing electronics 1, but is not limited thereto. In some embodiments, when the optical performance is both transmittance, the light source 16b can be turned off, so that the light intensity of the light beam L1 emitted from the light source 16a and passing through the area to be detected by the splicing electronics 1, received by the photosensor 18, can represent the optical performance. In some embodiments, when the optical performance is both reflectance, the light source 16a can be turned off, so that the light intensity of the light beam L2 emitted from the light source 16b and reflected by the area to be detected by the splicing electronics 1, received by the photosensor 18, can represent the optical performance. The optical performance referred to below is transmittance, but is not limited thereto.

[0037] The cross-sectional shapes of beams L1 and L2 can be, for example, circular or other suitable shapes. When the cross-sectional shape of beams L1 and L2 is circular, their spot diameter can, for example, fall within the range of 2 millimeters (mm) to 20 millimeters, such as 3 millimeters, 5 millimeters, 10 millimeters, 15 millimeters, or 20 millimeters. The color of beam L1 can, for example, be the same as the color of beam L2, and can be adjusted to the desired color as needed. For example, the optical performance in any of the above relationships can be the light intensity measured when beams L1 and L2 are white light. The wavelength range of white light can, for example, fall within the range of 400 nanometers to 800 nanometers.

[0038] In some embodiments, as shown in FIG1, beams L1 and L2 can be green light, wherein the wavelength range of green light can be, for example, between 535 nanometers and 575 nanometers. In this case, the first optical performance P1 and the second optical performance P2 can satisfy the following relationship (9): |(P1-P2) / P2|≤3%. Since the human eye is more sensitive to (or able to distinguish) green light in bright environments than other colors of light, the structure that satisfies the relationship (9) can reduce the probability that the user will perceive the difference between the first region R1 and the second region R2. Similarly, the relationships between the optical performance of region R1 and region R5 (between R1 and R1), region R6 and region R6 (between R5 and R6), region R4 and region R7 and R4 (between R4 and R4), region R8 and region R8 (between R7 and R8), region R6 and region R9 and R6 (between R6 and R6), and region R8 and region R9 and R4 (between R1 and R4), are also related. The relationship between the optical performance of the area between zone 9 R9 and zone 8 R8 can also satisfy relation (9), where P2 can be replaced by the optical performance of the area between zone 5 R5 and zone 1 R1, the area between zone 5 R5 and zone 6 R6, the area between zone 7 R7 and zone 4 R4, the area between zone 7 R7 and zone 8 R8, the area between zone 9 R9 and zone 6 R6, or the area between zone 9 R9 and zone 8 R8, and P1 can be replaced by the optical performance of zone 4 R4, zone 6 R6, or zone 8 R8.

[0039] In some embodiments, when beams L1 and L2 are green light, the second optical performance P2 and the third optical performance P3 satisfy the following relationship (10): |(P2-P3) / P3|≤6%. Similarly, the relationships between the optical performance of the fifth region R5 and the region located between the fifth region R5 and the first region R1, the relationships between the optical performance of the fifth region R5 and the region located between the fifth region R5 and the sixth region R6, the relationships between the optical performance of the seventh region R7 and the region located between the seventh region R7 and the fourth region R4, the relationships between the optical performance of the seventh region R7 and the region located between the seventh region R7 and the eighth region R8, the relationships between the optical performance of the ninth region R9 and the region located between the ninth region R9 and the sixth region R6, and the relationships between the optical performance of the ninth region R9 and the region located between the ninth region R9 and the sixth region R6, are also related. The relationship between the optical performance of the region between R9 and the eighth region R8 can also satisfy the above relationship (10), where P3 can be replaced by the optical performance of the fifth region R5, the seventh region R7 or the ninth region R9, and P2 can be replaced by the optical performance of the region between the fifth region R5 and the first region R1, the region between the fifth region R5 and the sixth region R6, the region between the seventh region R7 and the fourth region R4, the region between the seventh region R7 and the eighth region R8, the region between the ninth region R9 and the sixth region R6, or the region between the ninth region R9 and the eighth region R8.

[0040] In some embodiments, the light beam may be blue light, wherein the wavelength range of blue light may be, for example, between 420 nanometers and 440 nanometers. In this case, the first optical performance P1 and the second optical performance P2 may satisfy the following relationship (11): |(P1-P2) / P2|≤4%. Since the human eye is less sensitive (or able to distinguish) to blue light in bright environments than to other colors of light, a structure that satisfies relationship (11) can still reduce the probability that the user will perceive the difference between the first region R1 and the second region R2. Similarly, the relationships between the optical performance of the first region R1 and the region located between the fifth region R5 and the first region R1, the relationships between the optical performance of the sixth region R6 and the region located between the fifth region R5 and the sixth region R6, the relationships between the optical performance of the fourth region R4 and the region located between the seventh region R7 and the fourth region R4, the relationships between the optical performance of the eighth region R8 and the region located between the seventh region R7 and the eighth region R8, the relationships between the optical performance of the sixth region R6 and the region located between the ninth region R9 and the sixth region R6, and the relationships between the optical performance of the eighth region R8 and the region located between the ninth region R7 and the ninth region R8, are also related. The relationship between the optical performance of the regions between region R9 and region R8 can also satisfy the relation (11), where P2 can be replaced by the optical performance of the region between region R5 and region R1, region between region R5 and region R6, region between region R7 and region R4, region between region R7 and region R8, region between region R9 and region R6, or region between region R9 and region R8, and P1 can be replaced by the optical performance of region R4, region R6, or region R8.

[0041] In some embodiments, when the light beam can be blue light, the second optical performance P2 and the third optical performance P3 satisfy the following relationship (12): |(P2-P3) / P3|≤8%. Similarly, the relationships between the optical performance of the fifth region R5 and the region located between the fifth region R5 and the first region R1, the relationships between the optical performance of the fifth region R5 and the region located between the fifth region R5 and the sixth region R6, the relationships between the optical performance of the seventh region R7 and the region located between the seventh region R7 and the fourth region R4, the relationships between the optical performance of the seventh region R7 and the region located between the seventh region R7 and the eighth region R8, the relationships between the optical performance of the ninth region R9 and the region located between the ninth region R9 and the sixth region R6, and the relationships between the optical performance of the ninth region R9 and the region located between the ninth region R9 and the sixth region R6, are also related. The relationship between the optical performance of the region between R9 and the eighth region R8 can also satisfy the above relationship (12), where P3 can be replaced by the optical performance of the fifth region R5, the seventh region R7 or the ninth region R9, and P2 can be replaced by the optical performance of the region between the fifth region R5 and the first region R1, the region between the fifth region R5 and the sixth region R6, the region between the seventh region R7 and the fourth region R4, the region between the seventh region R7 and the eighth region R8, the region between the ninth region R9 and the sixth region R6, or the region between the ninth region R9 and the eighth region R8.

[0042] Specifically, as shown in the enlarged schematic diagram on the right side of Figure 1, each electronic module 12 may include multiple light-emitting units 20, wherein the light-emitting units 20 may include, for example, light-emitting units 20a, 20b, and 20c, which are used to generate light of different colors respectively. Furthermore, each electronic module 12 may include multiple transparent areas TR1, and the light-emitting units 20 are separated from the transparent areas TR1 in the top view, so that the electronic module 12 can appear transparent. According to this embodiment, one light-emitting unit 20a, one light-emitting unit 20b, and one light-emitting unit 20c can each serve as a different sub-pixel of the same pixel PX, so that each electronic module 12 can display an image. Therefore, the splicing electronic device 1 can display a spliced ​​large-size image, but is not limited thereto. In each electronic module 12, the pixels PX can be arranged in an array, and the transparent areas TR1 are also arranged in an array, wherein the pixels PX and the transparent areas TR1 are arranged in a staggered manner, but is not limited thereto. As shown in Figure 1, in two adjacent electronic modules 12 arranged in direction D1, each column of transparent area TR1 of one electronic module 12 can be arranged in the same column as a corresponding column of transparent area TR1 of the other electronic module 12, and each column of pixels PX of one electronic module 12 can be arranged in the same column as a corresponding column of pixels PX of the other electronic module 12. In two adjacent electronic modules 12 arranged in direction D2, each row of transparent area TR1 of one electronic module 12 can be arranged in the same row as a corresponding row of transparent area TR1 of the other electronic module 12, and each row of pixels PX of one electronic module 12 can be arranged in the same row as a corresponding row of pixels PX of the other electronic module 12. The aforementioned transparent area TR1 can be an area without a light-shielding layer, wherein the transmittance of the light-shielding layer is less than 25%, and the light-shielding layer can be, for example, metal, black resin, black pigment, black dye, or other suitable materials, but is not limited thereto.

[0043] The light-emitting unit 20 may include, for example, a light-emitting diode, but is not limited thereto. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a quantum dot diode (QLED or QDLED), an inorganic light-emitting diode (LED), any other suitable light-emitting element, or a combination thereof. The inorganic light-emitting diode may include, for example, a sub-millimeter light-emitting diode (mini LED) or a micro light-emitting diode (micro LED), but is not limited thereto. For example, in this embodiment, the light-emitting unit 20 may include an inorganic light-emitting diode (e.g., a micro LED), and may include two semiconductor layers, an active layer located between the semiconductor layers, an electrode connected to one of the semiconductor layers, and an electrode connected to the other of the semiconductor layers, but is not limited thereto. In some embodiments, the light-emitting unit 20 may include other suitable light-emitting materials.

[0044] In some embodiments, as shown in FIG1, the first region R1 to the fourteenth region R14 may each have a chromaticity value, and any two of these chromaticity values ​​may satisfy the following relationship (13): Δ(Wx, Wy) ≤ 0.020. For example, when the first region R1 has a chromaticity value (Wx1, Wy1) ​​in the CIE 1931 chromaticity space, and the second region R2 has a chromaticity value (Wx2, Wy2) in the CIE 1931 chromaticity space, the Δ(Wx, Wy) between the first region R1 and the second region R2 may be: And less than or equal to 0.020. In some embodiments, Δ(Wx, Wy) may also be less than or equal to 0.010, or less than or equal to 0.005. In this case, the splicing electronic device 1 may also include a color adjustment layer disposed on the light-emitting surface of each light-emitting unit (e.g., light-emitting unit 20a, light-emitting unit 20b and light-emitting unit 20c shown in FIG. 1), such that when the splicing electronic device 1 is in a display state, for example, when the image is displayed at 50% luminous brightness or at half of the maximum gray level value, the chromaticity values ​​of different areas can satisfy the relationship (13). The color adjustment layer may include, for example, color filter materials, pigments, multilayer films, other suitable materials or structures or combinations thereof. In some embodiments, the optical structure 22 may include color filter materials, pigments, multilayer films, other structures that affect the above optical performance, other suitable materials or structures or combinations thereof, or the color adjustment layer may also be disposed in the transparent area TR1. In this case, when the splicing electronic device 1 is in a non-display state, that is, when the light-emitting units (e.g., the light-emitting units 20a, 20b and 20c shown in Figure 1) do not produce light, the chromaticity values ​​of different areas can satisfy the relation (13).

[0045] The stacked structure of the splicing electronic device will be further described in detail below. Please refer to FIG3, which is a cross-sectional view of the splicing electronic device according to the first embodiment of the present disclosure along section line A-A' of FIG1. ​​The splicing electronic device 1 may further include a first optical layer 24a and a second optical layer 24b, wherein the first electronic module 12a and the second electronic module 12b are disposed between the first optical layer 24a and the second optical layer 24b. The first optical layer 24a and the second optical layer 24b may include a transparent filler material, such as silicone glue or other suitable adhesive material. The first optical layer 24a and the second optical layer 24b may, for example, be made of the same material to facilitate the matching of the optical properties of the first optical layer 24a and the second optical layer 24b.

[0046] Furthermore, the splicing electronic device 1 may also include a substrate SB1 for supporting the electronic module 12. In this embodiment, the optical structure 22 may be disposed on the substrate SB1, but is not limited thereto. The substrate SB1 may be a transparent substrate, such as a rigid substrate or a flexible substrate. Rigid substrates include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof, while flexible substrates include, for example, polyimide (PI) substrates, polycarbonate (PC) substrates, polyethylene terephthalate (PET) substrates, other suitable materials, or combinations thereof, but are not limited thereto.

[0047] In the embodiment of FIG3, the optical structure 22 may include materials that affect optical performance, such as materials that reduce transmittance. The optical structure 22 may include, for example, black pigment and resin, photoresist, color filter materials, or other suitable materials, wherein the black pigment is disposed in the resin, and the black pigment may, for example, account for 5% to 70% of the overall optical structure 22, or preferably 20% to 50% of the optical structure 22. Although the optical structure 22 can adjust the optical performance of the portion of the splicing electronic device 1 corresponding to the gap, the portion of the splicing electronic device 1 corresponding to the optical structure 22 can still have a transmittance of over 40%. Therefore, by setting the optical structure 22 at the position corresponding to the gap, the optical performance of the portion of the splicing electronic device 1 corresponding to the gap can be matched with the optical performance of the portion of the splicing electronic device 1 corresponding to the electronic module 12, thereby reducing the visibility of the gap and improving the visual effect of the splicing electronic device 1. When the optical structure 22 includes color filter materials, the optical structure 22 may include a stack of different colored color filter materials, but is not limited thereto. In some embodiments, the optical structure 22 may also include a color filter material of a specific color to reduce or avoid chromatic aberration of light after it passes through the splicing electronics 1.

[0048] According to this embodiment, the splicing electronic device 1 further includes a third optical layer 26 disposed on the second optical layer 24b. In other words, the first optical layer 24a and the second optical layer 24b are disposed between the substrate SB1 and the third optical layer 26. The third optical layer 26 may, for example, be used to protect the second optical layer 24b and / or provide optical effects. For example, the third optical layer 26 may be a cover plate, an anti-reflective film, or other suitable optical film. The cover plate may, for example, include a glass substrate or other suitable substrate.

[0049] In Figure 3, each electronic module 12 may include a transparent substrate SB2 and a display layer DL, and the display layer DL may be disposed on the transparent substrate SB2. The display layer DL may include, for example, a plurality of light-emitting units 20 as shown in Figure 1 for displaying images, but is not limited thereto. The transparent substrate SB2 may include, for example, a rigid substrate or a flexible substrate. The rigid substrate may include, for example, glass, quartz, sapphire, ceramic, other suitable materials or combinations of the above materials, while the flexible substrate may include, for example, a polyimide (PI) substrate, a polycarbonate (PC) substrate, a polyethylene terephthalate (PET) substrate, other suitable materials or combinations of the above materials, but is not limited thereto.

[0050] The display layer DL may also include, for example, a buffer layer 28, multiple transistors T, multiple insulating layers, and multiple conductive layers. The buffer layer 28 may be disposed on the transparent substrate SB2, the transistors T may be disposed on the buffer layer 28, and the multiple conductive layers may include or form multiple traces TL that pass through portions of the insulating layer, respectively used to electrically connect the corresponding light-emitting unit 20 to the corresponding transistor T. In Figure 3, the insulating layer may include, for example, insulating layers IL1, IL2, IL3, IL4, IL5, and IL6, and the display layer DL may include a semiconductor layer SL disposed on the buffer layer 28. The semiconductor layer SL may form the source region SR, drain region DR, and channel region CR of the transistor T, wherein the source region SR may be electrically connected to the traces TL, and thus electrically connected to the corresponding light-emitting unit 20. The insulating layer IL1 may be disposed on the semiconductor layer SL and the buffer layer 28, and serves as the gate insulating layer of the transistor T. The transistor T may include a gate GE disposed on the insulating layer IL1. The gate GE can be formed, for example, from one of the conductive layers. An insulating layer IL2 can be disposed on the gate GE and the insulating layer IL1, and insulating layers IL3 and IL4 are sequentially disposed on the insulating layer IL2. Each of the insulating layers IL4, IL3, IL2, and IL1 may have vias, allowing the trace TL to pass through these layers and contact the source region SR, but this is not limited to this. An insulating layer IL5 can be disposed on the trace TL and the insulating layer IL4, and the display layer DL may further include multiple electrode pairs disposed on the insulating layer IL5, each electrode pair including electrode E1 and electrode E2. The insulating layer IL5 may have vias, allowing electrode E1 to pass through the insulating layer IL5 and electrically connect to the trace TL. Electrodes E1 and E2 can be formed, for example, from another conductive layer. The insulating layer IL6 may have multiple openings OP1, and each opening OP1 can expose a corresponding electrode pair. The light-emitting units 20 can be respectively disposed in the corresponding openings OP1 and bonded to the electrodes E1 and E2 of the corresponding electrode pairs, thereby being electrically connected to the corresponding transistors T. In other words, the insulating layer IL6 can, for example, serve as a pixel definition layer. In Figure 3, the display layer DL may optionally also include a filling layer FL disposed in the openings OP1 to enhance the bonding force between the light-emitting units 20 and the electrode pairs.

[0051] It should be noted that the buffer layer 28, insulating layers IL1, IL2, and IL3 may, for example, include inorganic insulating materials to reduce the influence of water vapor or oxygen on the operation of the transistor T. Inorganic insulating materials may, for example, include silicon oxide, silicon nitride, aluminum oxide, other suitable materials, or combinations thereof. The buffer layer 28 may, for example, include a single-layer or multi-layer structure. The multi-layer structure of the buffer layer 28 may, for example, include a sequential stacking of silicon nitride, silicon oxide, and silicon nitride, but is not limited thereto. The insulating layers IL4 and IL5 may, for example, include organic insulating materials, which have a better planarization effect than inorganic insulating materials. Therefore, the insulating layers IL4 and IL5 may have flat upper surfaces to facilitate the formation of flat electrodes E1 and E2, thereby improving the bonding strength between the light-emitting unit 20 and the electrode pair. The insulating layer IL6 may, for example, include organic or inorganic insulating materials. However, the materials of the insulating layers disclosed herein are not limited to the above.

[0052] In Figure 3, insulating layers IL4, IL5, and IL6, which include organic insulating materials, may have multiple openings OP21, such that openings OP21 can serve as transparent areas TR1. However, the openings OP21 disclosed herein are not limited to being formed by insulating layers IL4, IL5, and IL6, and can be adjusted as needed. The transparent area TR1 may also be, for example, the area surrounded by the bottom surface of the lowest insulating layer IL4 containing organic insulating material, corresponding to the side of the opening OP21. Buffer layer 28, insulating layers IL1, IL2, and IL3 may have multiple openings OP22, each corresponding to an opening OP21. Since the buffer layer 28, insulating layers IL1, IL2, and IL3 comprising inorganic insulating materials, and the insulating layers IL4, IL5, and IL6 comprising organic insulating materials are stacked separately, it facilitates the formation of openings OP21 with relatively flat sidewalls in insulating layers IL4, IL5, and IL6, and openings OP22 with relatively flat sidewalls in the buffer layer 28, insulating layers IL1, IL2, and IL3, but is not limited thereto. In some embodiments, at least one of the insulating layers IL1, IL2, IL3, and buffer layer 28 may also overlap with the transparent region TR1 or opening OP21 in direction D3.

[0053] According to this embodiment, the electronic module 12 may further include an encapsulation layer PL disposed on the display layer DL and the transparent substrate SB2 to protect the display layer DL, but is not limited thereto. The encapsulation layer PL may include a transparent encapsulation material, such as resin, epoxy resin, epoxy molding compound (EMC), other suitable materials, or combinations thereof.

[0054] The manufacturing method of the splicing electronic device 1 according to this embodiment will be further described below. As shown in FIG3, the manufacturing method of the splicing electronic device 1 may include providing a substrate SB1, forming a first optical layer 24a on the substrate SB1, disposing a plurality of electronic modules 12 on the first optical layer 24a, forming a second optical layer 24b on the electronic modules 12, and forming a third optical layer 26 on the second optical layer 24b. The manufacturing method disclosed herein is not limited to the above steps, and other steps may be performed before, after, or during any of the steps shown.

[0055] In Figure 3, between the steps of providing the substrate SB1 and forming the first optical layer 24a, an optical structure 22 can be formed on the substrate SB1. It is worth noting that in the step of setting the electronic module 12, the optical structure 22 can serve as an alignment mark to aid in positioning the electronic module 12. In this embodiment, the electronic module 12 may not overlap with the optical structure 22 in direction D3, but is not limited to this. Furthermore, the step of setting the electronic module 12 may optionally include pressing the electronic module 12 down so that there is no air gap between the electronic module 12 and the first optical layer 24a.

[0056] When the third optical layer 26 includes a rigid substrate, the step of forming the third optical layer 26 may include pressing the rigid substrate down so that there are no air gaps between the first optical layer 24a and the second optical layer 24b, between the second optical layer 24b and the electronic module 12, and between the third optical layer 26 and the second optical layer 24b.

[0057] It is worth noting that since the optical structure 22 has characteristics that affect optical performance, by setting the gap between the optical structure 22 and the electronic module 12, the uniformity of the optical performance of the splicing electronic device 1 can be improved. Therefore, users are not likely to notice the difference in optical performance between the area containing the gap and the area without the gap, thereby improving the uniformity of the optical performance of the splicing electronic device 1.

[0058] It should be noted that the components and / or films included in the splicing electronic device 1 of this embodiment are not limited to those described above, and may also include other components and / or films applicable to the splicing electronic device 1. Other embodiments or variations of this disclosure will be described below. For the sake of simplicity, the same film or components in the following embodiments will be referred to by the same designations, and their features will not be repeated. The differences between the above embodiments and other embodiments or variations will be described in detail below.

[0059] Please refer to Figure 4, which is a top view schematic diagram of an optical structure according to some embodiments of the present disclosure. As shown in part (I) of Figure 4, the optical structure 22 corresponding to the gap G may include a plurality of light adjustment strips 22a, and a slit 22S is provided between any two light adjustment strips 22a. As shown in part (II) of Figure 4, the optical structure 22 corresponding to the gap G may include a plurality of openings OP3, wherein the top view shape of the openings OP3 may be, for example, circular or other suitable shapes. The optical structure 22 shown in Figure 4 can also be applied to splicing electronic devices of any of the embodiments described above or below.

[0060] Please refer to Figure 5, which is a cross-sectional schematic diagram of a splicing electronic device according to a first variation of the first embodiment of the present disclosure. In the splicing electronic device 1a of this variation, the optical structure 22 may include a plurality of light adjustment strips 22a, wherein at least one light adjustment strip 22a overlaps the gap G, and at least another light adjustment strip 22a may be disposed in the electronic module 12 and located on the upper surface TS1 of the transparent substrate SB2 adjacent to the gap G. For example, the light adjustment strips 22a located in two adjacent electronic modules 12 may be disposed adjacent to the corresponding gap G, such that the light adjustment strips 22a can form a plurality of light-shielding stripes corresponding to the gap G to adjust the optical performance of the portion of the splicing electronic device 1a corresponding to the gap G. In Figure 5, the light adjustment strip 22a may be located between the transparent substrate SB2 and the encapsulation layer PL, but is not limited thereto. The optical structure 22 shown in Figure 5 may also be applied to the splicing electronic device of any of the embodiments described above or below.

[0061] Please refer to Figure 6, which is a cross-sectional schematic diagram of a splicing electronic device according to a second variation of the first embodiment of the present disclosure. In the splicing electronic device 1b of this variation, the electronic module 12 may further include a light adjustment structure 32 disposed on the upper surface TS1 of the transparent substrate SB2 adjacent to the gap G and the side surface SW1 facing the gap G. For example, the light adjustment structure 32 may include a first sub-part 32a and a second sub-part 32b, wherein the first sub-part 32a is disposed on the upper surface TS1 of the transparent substrate SB2, and the second sub-part 32b is disposed on the side surface SW1 of the transparent substrate SB2. Through the light adjustment structure 32, the optical performance of the splicing electronic device 1b corresponding to the gap G can be adjusted, for example, adjusting the wavelength or transmittance of the portion of the light passing through the splicing electronic device 1b corresponding to the gap G. The material of the light adjustment structure 32 may be the same as or similar to the optical structure 22 of Figure 1, as described above, and will not be repeated here. In some embodiments, the light adjustment structure 32 may optionally exclude the first sub-part 32a. The light adjustment structure 32 shown in Figure 6 can also be applied to the splicing electronic device in any of the above or below embodiments.

[0062] Please refer to Figure 7, which is a cross-sectional schematic diagram of a splicing electronic device according to a third variation of the first embodiment of the present disclosure. In the splicing electronic device 1c of this variation, the corners CA1 and / or CA2 of the transparent substrate SB2 of at least one electronic module 12 (e.g., the left-side electronic module 12) adjacent to the gap G may have rounded corners, so that the optical performance of the portion of the splicing electronic device 1 corresponding to the electronic module 12 and the portion corresponding to the gap G does not have a significant difference, thereby reducing the visibility of the gap G. In Figure 7, corners CA1 and CA2 may, for example, be the corner formed by the lower surface BS of the transparent substrate SB2 facing the substrate SB1 and the side surface SW1 facing the gap G, and the corner formed by the upper surface TS1 of the transparent substrate SB2 facing the display layer DL and the side surface SW1 facing the gap G, respectively. In some embodiments, the corners CA3 and / or CA4 of the transparent substrate SB2 relative to corner CA1 and corner CA2 may also have rounded corners, but are not limited thereto.

[0063] In the splicing electronic device 1c of this variant embodiment, the corner CA5 of the transparent substrate SB2 of at least another electronic module 12 (e.g., the electronic module 12 on the right) adjacent to the gap G may have a chamfer, so that the thickness of the transparent substrate SB2 gradually increases from the gap G towards the center of the electronic module 12. Therefore, the optical performance of the portion of the splicing electronic device 1 corresponding to the electronic module 12 and the portion corresponding to the gap G does not have a significant difference. For example, the optical performance of the splicing electronic device 1 may have a linear change along the horizontal direction (e.g., direction D1), thereby reducing the visibility of the gap G. In FIG7, the corner CA5 may, for example, be the corner formed by the lower surface BS of the transparent substrate SB2 facing the substrate SB1 and the side surface SW1 facing the gap G, to avoid the chamfer affecting the formation quality of the display layer DL and the encapsulation layer PL. In some embodiments, the splicing electronic device 1c may selectively have only rounded corners (e.g., corners CA1 and / or corners CA2) or chamfered corners CA5. The corner CA1 and / or corner CA2 or corner CA5 shown in Figure 7 can also be applied to the splicing electronic device in any of the above or below embodiments.

[0064] Please refer to Figure 8, which is a cross-sectional schematic diagram of a splicing electronic device according to a fourth variation of the first embodiment of this disclosure. In the splicing electronic device 1d of this variation, the side surface SW1 of the transparent substrate SB2 of the electronic module 12 facing the gap G may also have a rough surface, so that light is subjected to destructive interference when passing through the rough surface, thereby adjusting the optical performance (e.g., transmittance) of the portion of the splicing electronic device 1d corresponding to the gap G. For example, the roughness of the side surface SW1 may be greater than the roughness of the upper surface TS1 of the transparent substrate SB2.

[0065] In Figure 8, the portion TP of the upper surface TS2 of substrate SB1 corresponding to gap G may also have a rough surface to adjust the optical performance (e.g., transmittance) of the portion of the splicing electronic device 1d corresponding to gap G. In some embodiments, the splicing electronic device 1d may selectively have only a rough side surface SW1 or a rough portion TP of the upper surface TS2 corresponding to gap G. The rough side surface SW1 and / or the rough portion TP of the upper surface TS2 shown in Figure 8 may also be applied to the splicing electronic device in any of the above or hereinafter embodiments.

[0066] Please refer to FIG9, which is a cross-sectional schematic diagram of a splicing electronic device according to a fifth variation of the first embodiment of the present disclosure. In the splicing electronic device 1e of this variation, the substrate SB1 may have a width W1 in the horizontal direction, the first optical layer 24a may have a width W2 in the horizontal direction, and the electronic module 12 may have a distribution width W3 in the horizontal direction. The distribution width W3 may refer to the distance between the outer side surface SW2 of the transparent substrate SB2 of the outermost electronic module 12 (e.g., the first electronic module 12a in FIG3) adjacent to the edge of the substrate SB1 and the outer side surface SW2 of the transparent substrate SB2 of the other outermost electronic module 12 (e.g., the second electronic module 12b in FIG3) adjacent to the other edge of the substrate SB1 in the horizontal direction. The horizontal direction in FIG9 is exemplified by direction D1, but is not limited thereto. In some embodiments, the horizontal direction may also be direction D2.

[0067] According to this modified embodiment, the width W1 can be greater than or equal to the width W2, so that the first optical layer 24a can be located on the substrate SB1. Furthermore, the distribution width W3 can be less than or equal to the width W2, so that each electronic module 12 can be disposed on and overlap with the first optical layer 24a, thereby improving the uniformity of the optical performance of the portion of the spliced ​​electronic device 1 corresponding to each electronic module 12.

[0068] In some embodiments, each electronic module 12 may further include a conductive element 34 disposed on the transparent substrate SB2 and adjacent to the outer side surface SW2. The conductive element 34 may be, for example, a chip-on-film (COF) film or other types of conductive structures, but is not limited thereto. A COF film may be, for example, a flexible circuit board on which a wafer is disposed. It should be noted that the second optical layer 24b has a width W4 in the horizontal direction, and the distribution width W3 may be greater than or equal to the width W4, allowing the conductive element 34 to be exposed. This facilitates heat dissipation of the conductive element 34, or, in the event of malfunction of the conductive element 34, facilitates replacement of the conductive element 34 or the wafer on it.

[0069] In some embodiments, the display layer DL of the electronic module 12 may have another distribution width W5 in the horizontal direction, and the third optical layer 26 may have a width W6 in the horizontal direction, wherein the width W6 is greater than or equal to the distribution width W5, so as to uniformize the effect of the image displayed by each display layer DL. The relationships between width W1, width W2 and distribution width W3, the relationship between distribution width W3 and width W4 and / or the relationship between distribution width W5 and width W6 shown in FIG9 can also be applied to the splicing electronic device of any of the above or below embodiments. In some embodiments, the widths W1 to W6 may be the maximum width of the corresponding element in the top view, or the maximum width in the direction parallel to the substrate SB1 in the cross-sectional view.

[0070] In some embodiments, substrate SB1 has a first refractive index n1, transparent substrate SB2 has a second refractive index n2, first optical layer 24a has a third refractive index n3, and second optical layer 24b has a fourth refractive index n4. The third refractive index n3 and the fourth refractive index n4 can be adjusted according to the first refractive index n1 and the second refractive index n2 to improve the transparency of the splicing electronic device 1. The deflection angle of light passing through the splicing electronic device 1 can be, for example, less than or equal to 5 degrees. For example, the first refractive index n1, the second refractive index n2, and the third refractive index n3 satisfy the relationship (14): [(n1+n2) / 2]-0.05≤n3≤ [(n1+n2) / 2]+0.05. The third refractive index n3 and the fourth refractive index n4 satisfy the relationship (15): n3-0.05≤n4≤n3+0.05. When substrate SB1 and transparent substrate SB2 comprise glass, the first refractive index n1 and the second refractive index n2 may be, for example, 1.48 to 1.52, and the third refractive index n3 and the fourth refractive index n4 may be, for example, approximately 1.5. The relationship between the first refractive index n1, the second refractive index n2, the third refractive index n3, and the fourth refractive index n4 described above can also be applied to the splicing electronic device in any of the embodiments described above or below.

[0071] Please refer to Figure 10, which is a cross-sectional schematic diagram of a splicing electronic device according to a second embodiment of the present disclosure. One difference between the splicing electronic device 2 provided in this embodiment and the splicing electronic device 1 of Figure 3 is that the second optical layer 24b can serve as an encapsulation layer. Therefore, the splicing electronic device 2 may not include the encapsulation layer PL shown in Figure 3, and the second optical layer 24b can contact the display layer DL and the transparent substrate SB2. The second optical layer 24b may, for example, include optically clear adhesive (OCA), optically clear resin (OCR), other suitable materials, or combinations thereof.

[0072] In the fabrication method of the splicing electronic device 2 in this embodiment, the electronic module 12 disposed on the first optical layer 24a may not include an encapsulation layer, and the second optical layer 24b may cover the display layer DL and the transparent substrate SB2. Other parts of the splicing electronic device 2 and its fabrication method in this embodiment are the same as those of the splicing electronic device 1 and its fabrication method in FIG3, and therefore can be referred to above, and will not be repeated here. The second optical layer 24b shown in FIG10 can also be applied to the splicing electronic device in any of the above or hereinafter embodiments.

[0073] Please refer to Figures 11 and 12. Figure 11 is a cross-sectional view of the splicing electronic device according to the third embodiment of this disclosure, and Figure 12 is a cross-sectional view of the splicing electronic device according to the third embodiment of this disclosure along section line B-B' in Figure 11. As shown in Figures 11 and 12, one difference between the splicing electronic device 3 provided in this embodiment and the splicing electronic device 1 in Figure 3 is that the splicing electronic device 3 may further include a circuit layer CRL disposed between the substrate SB1 and the electronic module 12. In this case, the electronic module 12 may include at least one through-hole structure 36 penetrating the transparent substrate SB2 and electrically connected to the circuit layer CRL, so that the electronic components (e.g., light-emitting units 20) in the electronic module 12 can be electrically connected to the circuit layer CRL through the through-hole structure 36, which can help to uniformly reduce the impedance of the electronic components of each electronic module 12 electrically connected to the pads 48 or external components located in the peripheral area PR.

[0074] Specifically, the circuit layer CRL may include multiple conductive layers and multiple insulating layers. In Figure 11, the circuit layer CRL may include, for example, conductive layer CL1, conductive layer CL2, insulating layer IL7, insulating layer IL8, and insulating layer IL9, but is not limited thereto. According to this embodiment, insulating layer IL7 may be disposed on substrate SB1, conductive layer CL1 may be disposed on insulating layer IL7, insulating layers IL8 and IL9 are sequentially disposed on conductive layer CL1 and insulating layer IL7, and conductive layer CL2 is disposed on insulating layer IL9. Conductive layer CL1 may include multiple wires 38, wherein the wires 38 may extend, for example, from below electronic module 12 to the peripheral area PR of splicing electronic device 3. Conductive layer CL4 may include multiple pads 40 disposed on insulating layer IL9, and insulating layers IL8 and IL9 may have through holes TH1, such that the pads 40 can be electrically connected to the wires 38 through the through holes TH1.

[0075] The electronic module 12 may include a conductive layer CL3 and a conductive layer CL4, respectively disposed on the upper surface TS1 and lower surface BS of the transparent substrate SB2, and the transparent substrate SB2 may also have a through-hole TH2. According to this embodiment, the conductive layer CL3 may include a plurality of through-hole structures 36, and the conductive layer CL2 may include a plurality of pads 42, wherein the through-hole structures 36 may further extend into the through-hole TH1 for electrical connection with the corresponding pads 42. The pads 42 may be bonded to the corresponding pads 40 during the step of disposing the electronic module 12 on the substrate SB1, so that components in the electronic module 12 (e.g., light-emitting unit 20) can be electrically connected to the corresponding wires 38 through the through-hole structures 36, pads 42, and pads 40. The pads 42 may be bonded to the corresponding pads 40, for example, through bonding pads 44. The bonding pads 44 may include, for example, solder balls or other suitable materials. In some embodiments, the through-hole TH1 may overlap with the through-hole TH2, but is not limited thereto.

[0076] It should be noted that insulating layers IL7, IL8, and IL9 may have multiple openings OP4, wherein the openings OP4 may overlap with the corresponding openings OP21 in direction D3, thereby improving the transmittance of the portion of the transparent area TR1 corresponding to the splicing electronic device 3. Furthermore, the first optical layer 24a may be disposed within the openings OP4. In some embodiments, the openings OP4 may also overlap with the gap G, but are not limited thereto. As shown in FIG12, the splicing electronic device 3 may also optionally include a light adjustment structure 46 disposed on the sidewall of the opening OP4, but is not limited thereto. The material of the light adjustment structure 46 may be the same as or similar to the optical structure 22 of FIG1, as described above, and will not be repeated here.

[0077] According to this embodiment, the splicing electronic device 3 may include a display area AR and a peripheral area PR, and the splicing electronic device 3 may include multiple pads 48. Conductors 38 may, for example, electrically connect to the pads 48 of the peripheral area PR, allowing electronic components (e.g., light-emitting units 20 or transistors T) in the electronic module 12 to be electrically connected to external components (e.g., control components or chips) through the pads 48. Through the arrangement of the circuit layer CRL and the via structure 36, electrical connection paths can be provided for the electronic components of each electronic module 12 to be electrically connected to the pads 48 of the peripheral area PR, thereby uniformizing the impedance between the electronic components of each electronic module 12 and the pads 48. For example, the conductors 38 may be power lines, allowing the light-emitting units 20 or transistors T of each electronic module 12 to receive uniform voltage or current. Furthermore, since the conductors 38 may overlap with the electronic module 12, for example, with the traces TL and / or light-emitting units 20 of the electronic module 12, the arrangement of the conductors 38 may not affect the optical performance of the splicing electronic device 3.

[0078] In this embodiment, as shown in FIG12, at least one transistor T electrically connected to the light-emitting unit 20 can be selectively replaced with an integrated circuit unit TC, that is, at least one light-emitting unit 20 can be electrically connected to the integrated circuit unit TC, but is not limited thereto. In some embodiments, the light-emitting units 20 may also be electrically connected to either the integrated circuit unit TC or the transistor T, but is not limited thereto. In the direction D3 of the splicing electronic device 3, the integrated circuit unit TC may be located below the light-emitting unit 20, but is not limited thereto. The integrated circuit unit TC may include, for example, a chip, but is not limited thereto. Other parts of the splicing electronic device 3 in this embodiment are the same as those of the splicing electronic device 1 in FIG3, and therefore can be referred to above, and will not be repeated here. The pad 48 shown in FIG11 and / or the circuit layer CRL shown in FIG12 can also be applied to the splicing electronic device of any of the above or below embodiments.

[0079] Please refer to Figures 13 and 14. Figure 13 is a top view of the splicing electronic device according to the fourth embodiment of this disclosure, and Figure 14 is a cross-sectional view of the splicing electronic device according to the fourth embodiment of this disclosure along section line C-C' in Figure 13. As shown in Figures 13 and 14, one difference between the splicing electronic device 4 provided in this embodiment and the splicing electronic device 1 shown in Figure 1 is that the splicing electronic device 4 may further include multiple transparent areas TR2, which are set corresponding to the gap between any two electronic modules 12. According to this embodiment, the transparent areas TR2 and the transparent areas TR1 of all electronic modules 12 can be arranged in an array, so that the structure of the portion of the splicing electronic device 1 corresponding to the gap (e.g., the first area R1 in Figure 1) can be similar to the structure of the portion of the corresponding electronic module 12 (e.g., the second area R2 or the third area R3 in Figure 1). Therefore, the optical performance of the portion of the splicing electronic device 4 corresponding to the gap can be close to or the same as the optical performance of the portion of the corresponding electronic module 12, so as to homogenize the optical performance of the splicing electronic device 4. The top view shape of the transparent area TR2 may be the same as that of the transparent area TR1. The transparent areas TR1 and TR2 may be areas without a light-shielding layer, wherein the light-shielding layer has a transmittance of less than 25%, and the light-shielding layer may be, for example, metal, black resin, black pigment, black dye or other suitable materials, but is not limited thereto.

[0080] For example, the transparent area TR2 may include multiple transparent areas TR21, multiple transparent areas TR22, multiple transparent areas TR23, multiple transparent areas TR24, and one transparent area TR25. Transparent areas TR21, TR22, TR23, and TR24 may overlap with gaps G1, G2, G3, and G4 respectively, and transparent area TR25 may simultaneously overlap with gaps G1, G2, G3, and G4. In Figure 13, transparent areas TR21, TR25, and TR22 may be arranged along direction D2, while transparent areas TR23, TR25, and TR24 may be arranged along direction D1. Furthermore, each transparent area TR21 may be arranged in the same column as a corresponding column of transparent areas TR1 in the first electronic module 12a and the second electronic module 12b, and each transparent area TR22 may be arranged in the same column as a corresponding column of transparent areas TR1 in the third electronic module 12c and the fourth electronic module 12d. Each transparent area TR23 can be arranged in the same row as the transparent area TR1 in the corresponding row of the first electronic module 12a and the third electronic module 12c, and each transparent area TR24 can be arranged in the same row as the transparent area TR1 in the corresponding row of the second electronic module 12b and the fourth electronic module 12d.

[0081] Since the portion of the splicing electronic device 4 corresponding to the gap does not have the insulating layer and transparent substrate SB2 of the electronic module 12, its transmittance is greater than that of the portion of the splicing electronic device 4 adjacent to the transparent area TR1. In this embodiment, the top view area of ​​one of the plurality of second transparent areas TR2 corresponding to the gap may be smaller than the top view area of ​​one of the plurality of first transparent areas TR1. Alternatively, for portions of transparent areas TR1 and transparent areas TR2 having the same top view shape corresponding to each other, the width W8 of a portion of transparent area TR2 in direction D1 or direction D2 may be smaller than the width W7 of the portion of transparent area TR1 corresponding to said portion in direction D1 or direction D2. For example, the maximum width W21 of transparent area TR21 in direction D1 and the maximum width W21 of transparent area TR22 in direction D1 may be smaller than the maximum width W11 of transparent area TR1 in direction D1. The maximum width W22 of transparent area TR23 in direction D2 and the maximum width W22 of transparent area TR24 in direction D2 may be smaller than the maximum width W12 of transparent area TR1 in direction D1. In some embodiments, the maximum width W23 of transparent area TR21 in direction D2 may be the same as or less than the maximum width W12 of transparent area TR1 in direction D2, and the maximum width W24 of transparent area TR23 in direction D1 may be the same as or less than the maximum width W24 of transparent area TR24 in direction D1, and the maximum width W11 of transparent area TR1 in direction D1 may be the same as or less than the maximum width W11 of transparent area TR1. In some embodiments, since transparent area TR25 overlaps with gaps G1, G2, G3 and G4 simultaneously, the maximum width W25 of transparent area TR25 in direction D1 may be less than the maximum width W11 of transparent area TR1 in direction D1, and the maximum width W26 of transparent area TR25 in direction D2 may be less than the maximum width W12 of transparent area TR1 in direction D2. For example, the maximum width W25 of the transparent area TR25 in direction D1 can be the same as or smaller than the maximum width W21 of the transparent area TR21 in direction D1 and the maximum width W21 of the transparent area TR22 in direction D1, and the maximum width W26 of the transparent area TR25 in direction D2 can be the same as or smaller than the maximum width W22 of the transparent area TR23 in direction D2 and the maximum width W22 of the transparent area TR24 in direction D2. Through the structure with the above-mentioned width difference, the transmittance of the transparent area TR2 of the corresponding gap can be matched with the transmittance of the transparent area TR1, thereby homogenizing the transmittance of the spliced ​​electronic device 4.

[0082] Furthermore, the transparent area TR1 may be, for example, the area surrounded by the bottom surface of the bottom insulating layer IL4 containing organic insulating material corresponding to the side of the opening OP21, while the transparent area TR2 may be, for example, the area formed by the bottom surface of the bottom insulating layer IL4 containing organic insulating material corresponding to a portion of the side of the gap.

[0083] As shown in Figures 13 and 14, the transparent area TR1 of the electronic module 12 may have a pitch in a horizontal direction. For example, in each electronic module 12, the transparent area TR1 may have a pitch PT1 in direction D1 and a pitch PT2 in direction D2. In the cross-sectional view of the spliced ​​electronic device 4, each electronic module 12 may include multiple island-shaped portions IS, and a transparent area TR1 may be present between two adjacent island-shaped portions IS. Since the transparent area TR1 is formed by the side of the bottom surface of the bottom insulating layer IL4 containing organic insulating material, the bottom surfaces of the insulating layer IL4 of two adjacent island-shaped portions IS in the same electronic module 12 may have sides S1 facing adjacent transparent areas TR1 respectively, and the pitch PT1 or pitch PT2 of the transparent area TR1 may be, for example, the distance between the two sides S1. Furthermore, the transparent area TR2 is also formed by a portion of the side S2 of the bottom surface of the bottom insulating layer IL4 containing organic insulating material. Therefore, the transparent area TR2 and the nearest transparent area TR1 in the adjacent electronic module 12 can also have a perimeter distance. For example, the transparent area TR21 and the nearest transparent area TR1 in the second electronic module 12b (or the first electronic module 12a) have a perimeter distance PT3 in the direction D1, but are not limited thereto. In other words, the bottom surface of the insulating layer IL4 of the island-shaped portion IS of the first electronic module 12a that is closest to the second electronic module 12b can have a side S2 facing the gap G1, and the bottom surface of the insulating layer IL4 of the island-shaped portion IS of the second electronic module 12b that is closest to the first electronic module 12a can have a side S1 away from the gap G1, and the perimeter distance PT3 between the transparent area TR2 and the transparent area TR1 can be, for example, the distance between the side S1 and the side S2. Perimeter spacing PT1 and / or PT2 may, for example, fall within the range of 0.8 to 1.2 times PT3 (that is, 0.8 × PT3 ≤ PT1 (or PT2) ≤ 1.2 × PT3). In some embodiments, the transparent area TR23 of FIG13 and the nearest transparent area TR1 in the third electronic module 12c (or the first electronic module 12a) may also have another perimeter spacing in direction D2, wherein the other perimeter spacing may be similar to or the same as the perimeter spacing PT3, and may satisfy the above relationship with perimeter spacing PT1 and / or PT2. It should be noted that by adjusting the size of the perimeter spacing PT3, the difference in optical performance between the portion of the splicing electronic device 4 corresponding to the gap G1 and the portion not containing the gap can be reduced, thereby homogenizing the visual effect of the splicing electronic device 4.

[0084] In some embodiments, in the island-shaped portion IS of the nearest adjacent gap (e.g., gap G1), at least one of the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 containing inorganic insulating material may be closer to the gap in cross-sectional view than the insulating layer IL4 located thereon, in order to adjust the optical performance of the portion of the splicing electronic device 4 corresponding to the gap. That is, at least one of the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 may partially overlap the transparent area TR2.

[0085] In some embodiments, at least one of the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 may overlap the transparent region TR1. For example, as shown in FIG14, the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 may overlap the transparent region TR1. In this case, in the island-shaped portion IS of the nearest gap, the side S1 of the bottom surface of the insulating layer IL4 facing the transparent region TR1 and the side S3 of the bottom surface of the buffer layer 28 facing the transparent region TR1 have a distance DS1 in the top view, and the side S2 of the bottom surface of the insulating layer IL4 facing the gap and the side S4 of the bottom surface of the buffer layer 28 facing the gap have a distance DS2 in the top view, wherein the distance DS1 may be smaller than the distance DS2. In other words, the width of the portion of the film layer containing inorganic insulating material (e.g., buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3) adjacent to the gap and not overlapping with the insulating layer IL4 containing organic insulating material can be greater than the width of the portion of the film layer overlapping the transparent area TR1 (or opening OP21). Therefore, at least one of the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 containing inorganic insulating material can be used to adjust the optical performance of the portion of the splicing electronic device 4 corresponding to the gap G1, thereby homogenizing the visual effect of the splicing electronic device 4. In some embodiments, in the island-shaped portion IS of the nearest gap (e.g., gap G1), the buffer layer 28 may selectively not overlap with the transparent area TR1 and / or the transparent area TR2.

[0086] In some embodiments, when any one of the buffer layer 28, insulating layer IL1, insulating layer IL2, and insulating layer IL3 comprises a material whose refractive index does not match the first refractive index of substrate SB1 and the second refractive index of transparent substrate SB2, the insulating layer may selectively not overlap with transparent region TR1 and / or transparent region TR2. For example, when insulating layer IL1 and insulating layer IL3 comprise a material whose refractive index is close to or matches the first refractive index of substrate SB1 and the second refractive index of transparent substrate SB2, in a top view of the splicing electronic device 4, a portion of insulating layer IL1 and a portion of insulating layer IL3 may be located between the side edge S2 of the bottom surface of insulating layer IL4 and the gap, for example, overlapping transparent region TR2 or transparent region TR1. When the refractive index of the materials contained in the buffer layer 28 and the insulating layer IL2 differs significantly from the first refractive index of the substrate SB1 and the second refractive index of the transparent substrate SB2, the buffer layer 28 and the insulating layer IL2 may not be located between the side edge S2 of the bottom surface of the insulating layer IL4 and the gap, or the portion of the buffer layer 28 and the insulating layer IL2 overlapping the transparent region TR2 may be smaller than the portion of the insulating layers IL1 and IL3 overlapping the transparent region TR2. The buffer layer 28 and the insulating layer IL2 may also not overlap the transparent region TR1, or the portion of the buffer layer 28 and the insulating layer IL2 overlapping the transparent region TR1 may be smaller than the portion of the insulating layers IL1 and IL3 overlapping the transparent region TR1. In this case, the insulating layers IL1 and IL3 may, for example, comprise silicon oxide or aluminum oxide, and the substrate SB1 and the transparent substrate SB2 may, for example, comprise glass, wherein the refractive index of silicon oxide is 1.56, the refractive index of aluminum oxide is 1.77, and the refractive index of glass is 1.48 to 1.52. In some embodiments, when the insulating layer between the side S2 on the bottom surface of the insulating layer IL4 and the gap is a multilayer stack, the insulating layer may be formed, for example, by alternating stacks of high refractive index material and low refractive index material to have a better reflective effect.

[0087] In some embodiments, in the island-shaped portion IS of the outer side SW2 closest to the electronic module 12, the bottom surface of the insulating layer IL4 adjacent to the side edge S5 of the outer side SW2 and the bottom surface of the buffer layer 28 adjacent to the side edge S6 of the outer side SW2 have a spacing DS3 in a top view, and the spacing DS1 may be smaller than the spacing DS3. Therefore, the optical performance of the portion of the spliced ​​electronic device 4 adjacent to the outer side SW2 is improved, thereby homogenizing the visual effect of the spliced ​​electronic device 4. In some embodiments, the spacing DS3 may be, for example, the same as the spacing DS2.

[0088] As shown in Figure 14, the splicing electronic device 4 may optionally include a sealing layer 50 disposed on the outside of the electronic module 12 to reduce or prevent the intrusion of moisture and oxygen. The sealing layer 50 may, for example, surround all of the electronic modules 12. The sealing layer 50 may include a sealing material, such as a light-cured resin, other suitable adhesives, or a combination thereof.

[0089] The other parts of the splicing electronic device 4 in this embodiment are the same as those of the splicing electronic device 1 in FIG3, and therefore can be referred to the above description, and will not be repeated here. The transparent area TR2 shown in FIG13 and / or the buffer layer 28, insulating layer IL1, insulating layer IL2, insulating layer IL3 or sealing layer 50 shown in FIG14 can also be applied to the splicing electronic device of any of the above or below embodiments.

[0090] In summary, in the splicing electronic device disclosed herein, since the optical performance of the portion corresponding to the center of the electronic module, the portion corresponding to the gap, and the portion located between the center of the electronic module and the gap can satisfy the aforementioned relationship, the uniformity of the optical performance of the splicing electronic device can be improved, thereby enhancing the visual effect of the splicing electronic device. Furthermore, through optical structures or light adjustment strips of the electronic module, light adjustment structures, rounded or chamfered corners or roughened sides of the transparent substrate, roughened upper surfaces of the substrate corresponding to the gap, or insulating layers containing inorganic materials, the optical performance of the portion of the splicing electronic device corresponding to the gap can be adjusted to match the optical performance of the portion corresponding to the electronic module, achieving the effect of improving the uniformity of the optical performance of the splicing electronic device.

[0091] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

[0092] 1,1a,1b,1c,1d,1e,2,3,4: Segmented electronic devices

[0093] 12: Electronic Module

[0094] 12a: First electronic module

[0095] 12b: Second electronic module

[0096] 12c: Third Electronic Module

[0097] 12d: Fourth Electronic Module

[0098] 14: Detection device

[0099] 16a, 16b: Light source

[0100] 18: Light sensor

[0101] 20, 20a, 20b, 20c: Light-emitting units

[0102] 22: Optical Structure

[0103] 22a: Light Adjustment Bar

[0104] 22S: Slit

[0105] 24a: First optical layer

[0106] 24b: Second optical layer

[0107] 26: Third optical layer

[0108] 28: Buffer layer

[0109] 32,46: Light Adjustment Structure

[0110] 32a: First Subsection

[0111] 32b: Second subsection

[0112] 34: Conductive components

[0113] 36: Through-hole structure

[0114] 38: Conductor

[0115] 40, 42, 48: Sealing pads

[0116] 44: Joint Pad

[0117] 50: Sealing layer

[0118] AR: Display Area

[0119] BS: Lower surface

[0120] CA1, CA2, CA3, CA4, CA5: Corner

[0121] CL1, CL2, CL3, CL4: Conductive layers

[0122] CR: Channel Area

[0123] CRL: Circuit Layer

[0124] D1, D2, D3: Direction

[0125] DL: Display Layer

[0126] DR: Drainage Zone

[0127] DS1, DS2, DS3: Spacing

[0128] E1, E2: Electrodes

[0129] FL: Fill layer

[0130] G1, G2, G3, G4, G: Gap

[0131] GE: Gate

[0132] IL1, IL2, IL3, IL4, IL5, IL6, IL7, IL8, IL9: Insulating layers

[0133] IS: Island-shaped portion

[0134] L1, L2: Beams

[0135] OP1, OP21, OP22, OP3, OP4: Openings

[0136] PL: Encapsulation layer

[0137] PA1: Part One

[0138] PA2: Part Two

[0139] PA3: Part Three

[0140] PA4: Part Four

[0141] PR: Surrounding Area

[0142] PT1, PT2, PT3: Perimeter distance

[0143] PX: pixel

[0144] R1: Zone 1

[0145] R2: Second Zone

[0146] R3: Third District

[0147] R4: Fourth District

[0148] R5: Fifth District

[0149] R6: District Six

[0150] R7: District Seven

[0151] R8: District 8

[0152] R9: District 9

[0153] R10: District 10

[0154] R11: District 11

[0155] R12: District Twelf

[0156] R13: District Thirteen

[0157] R14: District Fourteen

[0158] S2, S1, S3, S4, S5, S6: Side

[0159] SB1:Substrate

[0160] SB2: Transparent substrate

[0161] SL: Semiconductor layer

[0162] SR: Source Region

[0163] SW1: Side View

[0164] SW2: Outer side

[0165] T: Transistor

[0166] TC: Integrated Circuit Unit

[0167] TH1, TH2: Perforation

[0168] TL: routing

[0169] TP: Part

[0170] TR1, TR2, TR21, TR22, TR23, TR24, TR25: Transparent areas

[0171] TS1, TS2: Upper surface

[0172] W1, W2, W4, W6, W8, W7: Width

[0173] W21, W11, W22, W12, W23, W24, W25, W26: Maximum width

[0174] W3, W5: Distribution width

Claims

1. A splicing electronic device, comprising: First electronic module; The device includes a second electronic module disposed adjacent to the first electronic module, and the first electronic module and the second electronic module are separated by a gap along a first direction. The splicing electronic device has a first region and a second region. The first region includes a portion of the gap, a first portion of the first electronic module adjacent to the gap, and a second portion of the second electronic module adjacent to the gap. The second region and the first region are arranged along the first direction. The second region includes a third portion of the first electronic module adjacent to the first portion. The first region has a first optical performance ratio P1, and the second region has a second optical performance ratio P2. The first optical performance ratio P1 and the second optical performance ratio P2 satisfy the following relationship: |(P1-P2) / P2|≤5%, where both the first optical performance ratio and the second optical performance ratio are transmittance.

2. The splicing electronic device as claimed in claim 1, wherein the splicing electronic device has a third region, the third region including a fourth portion adjacent to the center of the first electronic module, the third region having a third optical performance P3, the second optical performance P2 and the third optical performance P3 satisfying the following relationship: |(P2-P3) / P3|≤10%.

3. The splicing electronic device as claimed in claim 2, wherein the first optical performance P1 and the third optical performance P3 satisfy the following relationship: |(P1-P3) / P3|≤10%.

4. The splicing electronic device as claimed in claim 3, wherein the third optical performance is transmittance.

5. The splicing electronic device as claimed in claim 1 further includes an optical structure configured corresponding to the gap.

6. The splicing electronic device as claimed in claim 5, wherein the optical structure includes a plurality of light adjustment strips or a plurality of openings.

7. The splicing electronic device as claimed in claim 5, wherein the optical structure comprises a black pigment and a resin, and the black pigment is disposed in the resin, wherein the black pigment accounts for 5% to 70% of the optical structure.

8. The splicing electronic device as claimed in claim 1 further includes a first optical layer and a second optical layer, wherein the first electronic module and the second electronic module are disposed between the first optical layer and the second optical layer.

9. The splicing electronic device as claimed in claim 8 further includes a substrate and a third optical layer, wherein the first optical layer and the second optical layer are disposed between the substrate and the third optical layer.

10. The splicing electronic device as described in claim 9 may further include a circuit layer disposed between the substrate and the first electronic module.

11. The splicing electronic device as claimed in claim 10, wherein the first electronic module includes a transparent substrate and a through-hole structure, and the through-hole structure penetrates the transparent substrate and is electrically connected to the circuit layer.

12. The splicing electronic device as claimed in claim 9, wherein the first electronic module includes a transparent substrate having a first refractive index n1, the transparent substrate having a second refractive index n2, the first optical layer having a third refractive index n3, and the first refractive index n1, the second refractive index n2 and the third refractive index n3 satisfy the relationship: [(n1+n2) / 2]-0.05≤n3≤[(n1+n2) / 2]+0.

05.

13. The splicing electronic device as claimed in claim 12, wherein the second optical layer has a fourth refractive index n4, and the third refractive index n3 and the fourth refractive index n4 satisfy the relationship: n3-0.05≤n4≤n3+0.

05.

14. The splicing electronic device as claimed in claim 8, wherein the first optical layer has a width in the first direction, the first electronic module and the second electronic module have a distribution width in the first direction, and the distribution width is less than or equal to the width.

15. The splicing electronic device as claimed in claim 8, wherein the second optical layer has a width in the first direction, the first electronic module and the second electronic module have a distribution width in the first direction, and the distribution width is greater than or equal to the width.

16. The splicing electronic device as claimed in claim 1, wherein the first electronic module includes a plurality of light-emitting units and a plurality of first transparent areas, and the plurality of light-emitting units are separated from the plurality of first transparent areas in a top view of the splicing electronic device.

17. The splicing electronic device as claimed in claim 16, wherein the splicing electronic device may further include a plurality of second transparent areas disposed corresponding to the gap, and the top view area of ​​one of the plurality of second transparent areas is smaller than the top view area of ​​one of the plurality of first transparent areas.

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