Clock phase control circuit and clock phase control method

Abstract

A clock phase control circuit includes a sampling circuit and a phase monitoring circuit. In response to a read command, the sampling circuit samples data read from a memory device at different clock edges of reference clock signals to obtain sampling results. The phase monitoring circuit includes a comparison circuit, a register circuit, and a determination circuit. The comparison circuit compares sampling results corresponding to different candidate phases with a sampling result corresponding to a current sampling phase of a base clock signal, in order to generate comparison results. The register circuit performs a logical operation upon comparison results corresponding to the same candidate phase and stores an operation result, in order to obtain an intersection of margins derived based on different clock edges. The determination circuit locates a first edge and a second edge of the intersection for determining an optimal phase.

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