Method for forming semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor device, which includes following steps. A substrate including a cell region, a peripheral region, and a dummy region therebetween is provided, wherein the substrate includes an isolation structure defining active regions in the cell region and the dummy region. Word lines, disposed in the substrate, extending in a first direction across the active regions and arranged in a second direction different from the first direction, are provided. Bit lines, disposed on the substrate, extending in the second direction across the active regions and arranged in the first direction, are provided. Spacers, extending in the second direction and arranged in the first direction, are formed on opposite sidewalls of each bit line. Portions of the substrate exposed by the spacers and word lines are removed to form at least one recess in each active region.

Description

[Technical Field]

[0001] The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor memory device. [Previous Technology]

[0002] As the size of electronic devices continues to shrink and users' demands for performance increase, one of the goals that those skilled in the art are striving to achieve is to enable electronic devices to include more components while maintaining the existing horizontal area, or to maintain the existing number of components while having a smaller horizontal area. However, both of these situations will make the process conditions more stringent, making it difficult to meet current or future needs in terms of process stability and process margin. [Summary of the Invention]

[0003] The present invention provides a method for forming a semiconductor device, which involves forming at least one groove in each active region of a substrate before forming a separation nitride for defining an opening of a storage node contact (SNC). This allows the groove to have the desired profile and area without being affected by the separation nitride during the groove formation process, thereby increasing the process stability and process margin of forming the storage node contact and avoiding the groove having an undesirable profile and area, which would cause the resistance between the storage node contact subsequently formed thereon and the active region to increase, thereby affecting the device's startup current (Ion).

[0004] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, wherein the substrate includes a cell region, a peripheral region, and a dummy region between the cell region and the peripheral region, and the substrate includes an isolation structure formed in the cell region and the dummy region to define a plurality of active regions; providing a plurality of word lines, wherein the plurality of word lines are disposed in the substrate and extend in a first direction to cross the plurality of active regions and are arranged in a second direction different from the first direction; providing a plurality of bit lines, wherein the plurality of bit lines are disposed on the substrate and extend in the second direction to cross the plurality of said active regions and are arranged in the first direction; forming spacer walls on opposite sidewalls of each bit line, wherein the plurality of spacer walls extend in the second direction and are arranged in the first direction; and removing a portion of the substrate exposed by the plurality of spacer walls and the plurality of word lines to form at least one groove in each active region.

[0005] In some embodiments, at least one groove includes a first groove and a second groove formed at opposite ends of each active region.

[0006] In some embodiments, the method of forming a semiconductor device further includes: forming a plurality of first conductive layers between a plurality of bit lines, wherein the plurality of first conductive layers extend in a second direction and are arranged in a first direction, and each first conductive layer is formed on a substrate and between spacer walls and includes a portion filled in at least one groove.

[0007] In some embodiments, the top surface of the first conductive layer is lower than the top surface of the bit line.

[0008] In some embodiments, the method of forming a semiconductor device further includes: forming a first insulating layer on each of the first conductive layers, wherein the material of the first insulating layer is different from the material of the spacer wall, and the top surface of the first insulating layer is coplanar with the top surface of the bit line.

[0009] In some embodiments, the method of forming a semiconductor device further includes: forming a plurality of trenches exposing a plurality of word lines in a first insulating layer, a first conductive layer and a substrate, wherein the plurality of trenches extend in a first direction and are arranged in a second direction; and forming a second insulating layer in each trench.

[0010] In some embodiments, the bottom surface of each ditch is lower than the bottom surface of at least one groove.

[0011] In some embodiments, the method of forming a semiconductor device further includes: removing a first insulating layer in a cell region to form a plurality of openings in the cell region that expose a first conductive layer, wherein the plurality of openings are defined by a plurality of second insulating layers and a plurality of spacer walls; and forming a second conductive layer in each opening.

[0012] In some embodiments, in the dummy region, there is a dummy structure between two adjacent bit lines, consisting of a first conductive layer and a first insulating layer formed on the first conductive layer.

[0013] In some embodiments, the bottom surface of the dummy structure includes a surface defined by at least one groove, wherein the surface is lower than the top surface of the base in the peripheral region.

[0014] Based on the above, in the above method of forming a semiconductor device, before forming the separating nitride (i.e., the second insulating layer) used to define the opening of the storage node contact (i.e., the first conductive layer and the second conductive layer formed in the cell region), at least one groove is formed in each active region of the substrate. This allows the groove to have the desired profile and area without being affected by the second insulating layer during the process of forming the groove, thereby increasing the process stability and process margin of forming the storage node contact, and avoiding the groove having an undesirable profile and area, which would cause the resistance between the storage node contact subsequently formed thereon and the active region to increase and affect the start-up current (Ion) of the device.

Implementation Method

[0015] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0016] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element. As used herein, "connection" may refer to a physical and / or electrical connection, and "electrical connection" or "coupling" may mean that there are other elements between two elements. As used herein, "electrical connection" may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0017] As used herein, “about,” “approximately,” or “substantially” includes the value mentioned and the average value within an acceptable range of deviations that can be determined by one of ordinary skill in the art, taking into account the measurement under discussion and the specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” or “substantially” may be chosen based on optical, etched, or other properties, and a single standard deviation may not be applied to all properties.

[0018] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0019] Figures 1A to 7 are schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention. Figures 1A, 2A, 3A, 4A, 5, 6, and 7 are cross-sectional schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention. In this embodiment, Figures 1B, 2B, 3B, and 4B are, for example, cross-sectional schematic diagrams taken by the cross-sections extending along the second direction D2 between bit lines BL in Figures 1A, 2A, 3A, and 4A. For ease of explanation, Figures 1B, 2B, 3B, and 4B omit components such as the isolation structure STI, active region AA, word line WL, and spacer SP shown in Figures 1A, 2A, 3A, and 4A.

[0020] First, referring to Figures 1A and 1B, a substrate 100 is provided. In this embodiment, the substrate 100 may include a cell region CR, a peripheral region PR, and a dummy region DR between the cell region CR and the peripheral region PR. In this embodiment, the substrate 100 may include an isolation structure STI formed in the cell region CR and the dummy region DR to define a plurality of active regions AA.

[0021] The substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be P-type, and the second conductivity type can be N-type. The isolation structure STI can be a shallow trench isolation structure. In some embodiments, the isolation structure STI may include silicon oxide.

[0022] Next, as shown in FIG1B, a plurality of character lines WL are provided. In some embodiments, the plurality of character lines WL may be disposed in the substrate 100 and extend in a first direction D1 to cross a plurality of active regions AA and arranged in a second direction D2 different from the first direction D1. In some embodiments, the first direction D1 may be perpendicular to the second direction D2. In some embodiments, the character lines WL may be provided, for example, in cell regions CR and dummy regions DR. The character lines WL may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or alloys thereof.

[0023] Then, as shown in FIG1B, a plurality of bit lines BL and a plurality of bit line contacts BLC are provided. In this embodiment, the plurality of bit line contacts BLC may be respectively disposed on a plurality of active regions AA and electrically connected to the plurality of active regions AA. The plurality of bit lines BL may be disposed on the substrate 100 and electrically connected to the plurality of bit line contacts BLC. In this embodiment, the plurality of bit lines BL may extend in a second direction D2 to cross the plurality of active regions AA and be arranged in a first direction D1. In some embodiments, the bit lines BL may be provided, for example, in cell regions CR and dummy regions DR. The bit line contacts BLC and the bit lines BL may each comprise a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or alloys thereof.

[0024] Subsequently, as shown in FIG1B, spacer walls SP are formed on the opposite sidewalls of each element line BL, wherein multiple spacer walls SP may extend in the second direction D2 and be arranged in the first direction D1. The spacer walls SP may include nitrides such as silicon nitride.

[0025] In some embodiments, a first material layer 110 may be provided on the cell region CR, dummy region DR, and peripheral region PR of the substrate 100. The first material layer 110 may include nitrides such as silicon nitride. In some embodiments, a second material layer 120 may be provided on the first material layer 110 in the peripheral region PR. The second material layer 120 may include a spin-on dielectric (SOD) material such as oxide. In some embodiments, a third material layer 130 may be provided on the second material layer 120 in the peripheral region PR. The third material layer 130 may include nitrides such as silicon nitride.

[0026] Next, referring to Figures 2A and 2B, a portion of the substrate 100 exposed by the plurality of spacer walls SP and the plurality of character lines WL is removed to form at least one groove r1 in each active region AA. In some embodiments, the groove r1 may be formed, for example, by a wet etching process having a high selectivity for the material of the substrate 100. In this embodiment, the at least one groove r1 may include grooves r1 (i.e., a first groove and a second groove) formed at opposite ends of each active region AA.

[0027] Next, referring to Figures 3A and 3B, a plurality of first conductive layers 140 are formed between the plurality of bit lines BL. The plurality of first conductive layers 140 extend in a second direction D2 and are arranged in a first direction D1, and each first conductive layer 140 is formed on the substrate 102 and between the spacer walls SP and includes a portion filled in at least one groove r1. The first conductive layer 140 may include a conductive material such as polysilicon. In some embodiments, the first conductive layer 140 may be formed by the following steps: First, conductive material is filled into a plurality of trenches TR1 defined by the substrate 102 and the spacer walls SP. In this embodiment, the plurality of trenches TR1 extend in the second direction D2 and are arranged in the first direction D1. Next, a process such as etch back is performed on the conductive material to form the first conductive layer 140. The top surface of the first conductive layer 140 may be lower than the top surface of the bit line BL.

[0028] Subsequently, a first insulating layer 150 is formed on each of the first conductive layers 140. The material of the first insulating layer 150 is different from the material of the spacer wall SP. In this embodiment, the spacer wall SP may include nitrides such as silicon nitride, and the first insulating layer 150 may include spin-on dielectric (SOD) materials such as oxides. In some embodiments, the top surface of the first insulating layer 150 and the top surface of the bit line BL may be coplanar. In some embodiments, the top surface of the first insulating layer 150 and the top surface of the third material layer 130 are coplanar. In some embodiments, the first insulating layer 150 may be formed by the following steps. First, insulating material is filled into a plurality of trenches TR1 to cover the first conductive layer 140, wherein the insulating material also covers the top surfaces of the spacer wall SP and the third material layer 130. Next, the portion of the insulating material on the top surfaces of the spacer wall SP and the third material layer 130 is removed by performing a planarization process such as chemical mechanical polishing (CMP) on the insulating material to form the first insulating layer 150. In this embodiment, the gap wall SP and the third material layer 130 can serve as a stop layer in the planarization process described above.

[0029] Next, referring to Figures 4A and 4B, a plurality of trenches TR2 exposing multiple character lines WL are formed in the first insulating layer 150, the first conductive layer 140, and the substrate 102, wherein the trenches TR2 extend in the first direction D1 and are arranged in the second direction D2. Then, a second insulating layer 160 is formed in each trench TR2. In some embodiments, the second insulating layer 160 may be formed by the following steps: First, a hard mask pattern HM1 is formed on the first insulating layer 150 and the third material layer 130. Then, a portion of the first insulating layer 150 exposed by the hard mask pattern HM1, as well as a portion of the first conductive layer 140 and the substrate 102 below that portion, is removed to form a plurality of trenches TR2 extending in the first direction D1 and arranged in the second direction D2. In this embodiment, the sidewalls of each trench TR2 may be defined by the first insulating layer 152 and the first conductive layer 142, while the bottom surface of each trench TR2 is defined by the substrate 102. In some embodiments, the bottom surface of each trench may be lower than the bottom surface of the groove r1. Next, an insulating material is filled into the trenches TR2, wherein the insulating material also covers the top surface of the rigid mask pattern HM1. Then, the insulating material on the top surface of the rigid mask pattern HM1 is removed by a process such as etch-back to form a second insulating layer 160. For clarity, the rigid mask pattern HM1 shown in FIG4A is omitted in FIG4B.

[0030] In this embodiment, the second insulating layer 160 may include nitrides such as silicon nitride. Since the second insulating layer 160 can be used to separate storage node contacts (e.g., storage node contacts SNC shown in FIG. 7) formed in subsequent processes, it may be referred to as a separation nitride. That is, before forming the separation nitride used to define the openings of the storage node contacts, the grooves r1 are formed in each active region AA of the substrate 102. This ensures that the process of forming the grooves r1 is not affected by the second insulating layer 160 and can have the desired profile and area, thereby increasing the process stability and process margin of forming the storage node contacts SNC. This avoids the grooves r1 having undesirable profiles and areas, which could cause an increase in resistance between the subsequently formed storage node contacts SNC and the active regions AA, affecting the device's startup current (Ion).

[0031] Then, referring to FIG5, the mask pattern PR1 is overlaid on the hard mask pattern HM1 in the peripheral area PR and the dummy area DR, exposing the hard mask pattern HM1 in the cell area CR. In this embodiment, the mask pattern PR1 may be a mask pattern used to define the cell area CR and the dummy area DR. In some embodiments, the mask pattern PR1 may include a photoresist material.

[0032] Next, referring to Figures 5 and 6, the hard mask pattern HM1 exposed by the mask pattern PR1 and the first insulating layer 152 below the hard mask pattern HM1 are removed to form a plurality of openings OP1 in the cell region CR that expose the first conductive layer 142, and a dummy structure DS including the first conductive layer 142 and the first insulating layer 154 and a hard mask pattern HM2 on the dummy structure DS are formed in the dummy region DR, wherein the hard mask pattern HM2 is also formed on the third material layer 130 of the peripheral region PR. In this embodiment, the opposite sidewalls of the openings OP1 in the first direction D1 are defined by two adjacent gap walls SP, and the opposite sidewalls of the openings OP1 in the second direction D2 are defined by two adjacent second insulating layers 160. After forming the openings OP1, the mask pattern PR1 is removed.

[0033] Next, referring to Figures 6 and 7, a second conductive layer 170 is formed in each opening OP1 to form a storage node contact SNC comprising the first conductive layer 142 and the second conductive layer 170 in the cell region CR. In some embodiments, the second conductive layer 170 may be formed by the following steps. First, conductive material is filled into the opening OP1, wherein the conductive material also covers the top surface of the second insulating layer 160 and the hard mask pattern HM2. Next, the hard mask pattern HM2, the second insulating layer 160, and the conductive material thereon are removed at the level of the top surface of the third material layer 130 and the first insulating layer 154 by a planarization process such as chemical mechanical polishing (CMP) to form the second insulating layer 162 and the second conductive layer 170. The second conductive layer 170 may comprise a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In this embodiment, the material of the second conductive layer 170 may be different from the material of the first conductive layer 142. For example, the first conductive layer 140 may include polycrystalline silicon, while the second conductive layer 170 may include tungsten (W).

[0034] In this embodiment, as shown in FIG7, in the dummy region DR, a dummy structure DS may be included between two adjacent bit lines BL, which is composed of a first conductive layer 142 and a first insulating layer 154 formed on the first conductive layer 142. In this embodiment, the bottom surface of the dummy structure DS may include a surface defined by the groove r1, wherein the surface is lower than the top surface of the substrate 102 in the peripheral region PR.

[0035] In this embodiment, the first conductive layer 142 in the storage node contact SNC is formed on the active region AA of the substrate 102 before the second insulating layer 160 is formed. Therefore, the space for filling the conductive material is not restricted by the second insulating layer 160, so that no void is generated in the first conductive layer 142 due to the space for filling the conductive material being restricted (e.g., the opening has a small horizontal dimension and / or a deep vertical height). For example, the first conductive layer 142 is first formed in a trench TR1 extending in the second direction D2, and then defined by the trench TR2 in which the second insulating layer 160 is formed and extending in the first direction D1. In other words, during the process of forming the first conductive layer 140, the space restriction in the second direction D2 is reduced, so that the first conductive layer 140 is not limited by the space filled with conductive material and voids are generated therein. Therefore, the first conductive layer 142 defined by the trench TR2 in which the second insulating layer 160 is formed will not have voids.

[0036] In summary, in the method of forming a semiconductor device in the above embodiments, before forming the separating nitride (i.e., the second insulating layer) used to define the opening of the storage node contact (i.e., the first conductive layer and the second conductive layer formed in the cell region), at least one groove is formed in each active region of the substrate. This allows the groove to have the desired profile and area without being affected by the second insulating layer during the process of forming the groove, thereby increasing the process stability and process margin of forming the storage node contact, and avoiding the groove having an undesirable profile and area, which would cause the resistance between the storage node contact subsequently formed thereon and the active region to increase and affect the startup current (Ion) of the device. [Simplified Explanation of the Diagram]

[0037] Figures 1A to 7 are schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate includes a cell region, a peripheral region, and a dummy region between the cell region and the peripheral region, and the substrate includes an isolation structure formed in the cell region and the dummy region to define a plurality of active regions; Provide multiple character lines, wherein the multiple character lines are disposed in the substrate and extend in a first direction to cross the multiple active regions, and are arranged in a second direction different from the first direction; Provide multiple bit lines, wherein the multiple bit lines are disposed on the substrate and extend in the second direction to span the multiple active regions, and are arranged in the first direction; form gap walls on opposite sidewalls of each bit line, wherein the multiple gap walls extend in the second direction and are arranged in the first direction; A portion of the substrate exposed by the plurality of said gap walls and the plurality of said character lines is removed to form at least one groove in each of said active regions; And forming a plurality of first conductive layers between the plurality of said bit lines, wherein the plurality of first conductive layers extend in the second direction and are arranged in the first direction, and each first conductive layer is formed on the substrate and between the spacer wall and includes a portion filled in the at least one groove.

2. The method of claim 1, wherein the at least one groove comprises a first groove and a second groove respectively formed at opposite ends of each of the active regions.

3. The method as described in claim 1, wherein the top surface of the first conductive layer is lower than the top surface of the bit line.

4. The method as described in claim 3, further comprising: A first insulating layer is formed on each of the first conductive layers, wherein the material of the first insulating layer is different from the material of the spacer wall, and the top surface of the first insulating layer is coplanar with the top surface of the bit line.

5. The method as described in claim 4, further comprising: A plurality of trenches are formed in the first insulating layer, the first conductive layer and the substrate to expose a plurality of the character lines, wherein the plurality of trenches extend in the first direction and are arranged in the second direction; and a second insulating layer is formed in each of the trenches.

6. The method as described in claim 5, wherein the bottom surface of each of the trenches is lower than the bottom surface of the at least one groove.

7. The method as described in claim 5, further comprising: The first insulating layer in the cell region is removed to form a plurality of openings in the cell region that expose the first conductive layer, wherein the plurality of openings are defined by a plurality of second insulating layers and a plurality of spacer walls; and a second conductive layer is formed in each of the openings.

8. The method of claim 7, wherein in the dummy region, a dummy structure consisting of the first conductive layer and the first insulating layer formed on the first conductive layer is included between two adjacent bit lines.

9. The method of claim 8, wherein the bottom surface of the dummy structure includes a surface defined by the at least one groove, wherein the surface is lower than the top surface of the substrate in the peripheral region.

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