String zero / one full circle drain-side select gate over program countermeasure

Abstract

A memory apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means erases and programs the transistor threshold voltage of the drain-side select gate transistors of one of the strings in one of a plurality of combined erase program operations. Each of the plurality of combined erase program operations includes an erase portion and a first program portion and a second program portion. In response to a string counter not equaling a total quantity of the strings, the control means increments the string counter and erases and programs the transistor threshold voltage of the drain-side select gate transistors of another of the strings in another of the plurality of combined erase program operations.

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