Antifuse cell circuit

Abstract

An antifuse cell circuit is provided, which includes an antifuse cell and a test cell. The antifuse cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a bit line, a second terminal coupled to a node, and a first control terminal coupled to a word line. The second transistor has a first terminal coupled to the node and a second control terminal coupled to a source line. The test cell includes a test transistor. The test transistor has a first terminal coupled to the node, and a second terminal and a third control terminal coupled to a test voltage. The test cell is located between the word line and the source line.

Description

[Technical Field]

[0001] The present invention relates to an antifuse unit circuit, and more particularly to an antifuse unit circuit capable of performing programmed detection within the antifuse unit. [Previous Technology]

[0002] An antifuse is a component that breaks down the dielectric layer between two conductors by applying a voltage to both conductors, forming a permanent conductive path. It is often used in conjunction with other components in the programming of non-volatile memory. However, as memory capacity increases and size decreases, the component density in a single memory cell continues to increase, making it more difficult to determine whether each component is in the correct state (e.g., correctly storing "1" or "0" to represent data content). Therefore, a solution is needed to address these problems. [Summary of the Invention]

[0003] According to an embodiment of this disclosure, an antifuse unit circuit is provided, including a first antifuse unit and a first test unit. The first antifuse unit has a first transistor and a second transistor, wherein the first transistor has a first end coupled to a first bit line, a second end coupled to a first node, and a first control terminal coupled to a first word line, and the second transistor has a first end coupled to the first node and a second control terminal coupled to a first write line. The first test unit has a first test transistor, wherein the first end of the first test transistor is coupled to the first node, and its second end and a third control terminal are simultaneously coupled to a test voltage. The first test unit is located between the first word line and the first write line.

[0004] According to one embodiment of the present disclosure, the antifuse unit circuit further includes a second antifuse unit having a third transistor and a fourth transistor, wherein the third transistor has a first terminal coupled to a second bit line, a second terminal coupled to a second node, and a fourth control terminal coupled to a second word line, and the fourth transistor has a first terminal coupled to the second node and a fifth control terminal coupled to a second write line. The first test unit further includes a second test transistor having a first terminal coupled to the second node, a second terminal coupled to a test voltage, and a sixth control terminal.

[0005] According to another embodiment of this disclosure, the antifuse unit circuit further includes a third antifuse unit and a fourth antifuse unit. The third antifuse unit has a fifth transistor and a sixth transistor, wherein the fifth transistor has a first terminal coupled to a first bit line, a second terminal coupled to a first node, and a seventh control terminal coupled to a third word line. The sixth transistor has a first terminal coupled to the first node and an eighth control terminal coupled to a third write line. The fourth antifuse unit has a seventh transistor and a ground eighth transistor, wherein the seventh transistor has a first terminal coupled to a second bit line, a second terminal coupled to a second node, and a ninth control terminal coupled to a fourth word line. The eighth transistor has a first terminal coupled to the second node and a tenth control terminal coupled to a fourth write line.

[0006] According to another embodiment of this disclosure, the antifuse unit circuit further includes a third antifuse unit, a fourth antifuse unit, and a second test unit. The third antifuse unit has a fifth transistor and a sixth transistor. The fifth transistor has a first terminal coupled to a first bit line, a second terminal coupled to a third node, and a seventh control terminal coupled to a third word line. The sixth transistor has a first terminal coupled to a third node and an eighth control terminal coupled to a third write line. The fourth antifuse unit has a seventh transistor and an eighth transistor, wherein the seventh transistor has a first terminal coupled to a second bit line, a second terminal coupled to a fourth node, and a ninth control terminal coupled to a fourth word line. The eighth transistor has a first terminal coupled to a fourth node and a tenth control terminal coupled to a fourth write line. The second test unit has a third test transistor and a fourth test transistor, wherein the third test transistor has a first terminal coupled to a third node, a second terminal coupled to a test voltage, and an eleventh control terminal. The fourth test transistor has a first terminal coupled to a fourth node, a second terminal coupled to a test voltage VTG, and a twelfth control terminal.

Implementation Method

[0007] An antifuse is a special electronic component frequently used in programmable logic devices within non-volatile memory, such as one-time programmable memory. Unlike the traditional method of creating an open circuit by melting a fuse, an antifuse can create a conductive path after a certain voltage is applied. For example, an antifuse may consist of two conductors and an oxide layer (such as the gate oxide layer of a metal-oxide semiconductor (MOS)) between the conductors. Therefore, when not programmed, an antifuse can be considered an open circuit (i.e., not conducting). When the voltage difference between the two conductors exceeds the upper limit that the oxide layer can withstand, the oxide layer is "broken down," creating a conductive path.

[0008] Since each antifuse can only be programmed once, it is essential to ensure that all components (such as transistors) in the antifuse unit function correctly. For example, in an antifuse unit comprising two transistors (2T), a first transistor is used for programming, while a second transistor is connected to the bit lines used for reading data. If the first transistor is not successfully programmed, or if it forms a conductive path when it should not be programmed (e.g., due to manufacturing defects), the state of the entire antifuse unit will be affected. Furthermore, if the second transistor malfunctions (e.g., fails to conduct to connect to the bit lines for reading), the antifuse unit will also malfunction.

[0009] However, although the first transistor can be tested for normality after programming (e.g., whether it is "broken down" as expected), such as whether a large current flows through it, it is not possible to directly determine whether the second transistor, which has not been programmed, is abnormal. Furthermore, if it is possible to determine whether there are malfunctioning or defective components in the antifuse unit before programming the memory, the accuracy of the data stored in the memory can be increased.

[0010] Figure 1A is a schematic diagram of an antifuse unit circuit 100 disclosed herein. The antifuse unit circuit 100 includes an antifuse unit 110 and a test unit 120, wherein the antifuse unit 110 includes a read transistor M1 and a write transistor M2, and the test unit includes a test transistor M3. Therefore, the antifuse unit circuit 100 can also be considered as a three-transistor (3T) antifuse unit. The first source / drain terminal of the read transistor M1 is coupled to a bit line BL0, the second source / drain terminal is coupled to a node N0, and its control terminal is coupled to a word line WL0. The first source / drain terminal of the write transistor M2 is coupled to node N0, and its control terminal is coupled to a write line SL0. The first source / drain terminal of the test transistor M3 is coupled to node N0, and its second source / drain terminal and control terminal are jointly coupled to a test voltage VTG. The "x" mark written on the second source / drain terminal of transistor M2 represents the open circuit terminal (e.g., it is blown during circuit manufacturing to isolate it from other antifuse units).

[0011] Figure 1B is a schematic diagram of the programmed test of the antifuse unit circuit 100 in Figure 1A. In one embodiment, it is assumed that the antifuse unit circuit 100 is not programmed, that is, the gate oxide layer of the write transistor M2 is not "broken down" by the voltage applied by the write line SL0. At this time, due to the characteristics of the antifuse element, the write transistor M2 will remain in a high impedance state (e.g., regarded as an open circuit), while the read transistor M1 will be turned on or off according to the voltage level on the word line WL0. At this time, the gate terminal of the test transistor M3 (and the source / drain terminal electrically connected to the gate terminal) is connected to the test voltage VTG (e.g., the supply voltage or any voltage source not less than the threshold voltage of the test transistor M3), so that the test transistor M3 can be regarded as an extension of the source / drain terminals of the read transistor M1 and the write transistor M2.

[0012] Next, the read transistor M1 and write transistor M2 are tested respectively to determine whether they can operate normally. Assuming the read transistor M1 is an N-type metal-oxide-semiconductor (NMOS), the read transistor M1 is turned on when the voltage on the word line WL0 is not less than the threshold voltage of the read transistor M1. When the voltage on the word line WL0 is less than the threshold voltage, the read transistor M1 is turned off. Therefore, if a test current IW0 is measured on the test transistor M3 when the word line WL0 is enabled, and no current is measured on the test transistor M3 when the word line WL0 is disabled, it indicates that the read transistor M1 is operating normally. Since the antifuse unit 110 is not programmed in this embodiment, the write transistor M2 does not form a conduction path. Therefore, with the character line WL0 disabled, no current was measured on the test transistor M3 when the write line SL0 was enabled or disabled, indicating that the write transistor M2 was operating normally (i.e., it was not programmed).

[0013] In another embodiment, if the antifuse unit 110 is programmed, the write transistor M2 should form a conduction path. Therefore, in this embodiment, when the word line WL0 is disabled, a test current IS0 is measured on the test transistor M3 when the write line SL0 is enabled, and no current is measured on the test transistor M3 when the write line SL0 is disabled, it can be determined that the write transistor M2 is indeed programmed.

[0014] Figure 2A is a schematic diagram of an antifuse unit circuit 200 shown according to this disclosure. The antifuse unit circuit 200 includes antifuse units 110 and 210 and a test unit 220, wherein antifuse unit 210 is similar to antifuse unit 110 and includes a read transistor M4 and a write transistor M5. The first source / drain terminal of the read transistor M4 is coupled to a bit line BL1, the second source / drain terminal is coupled to a node N1, and its control terminal is coupled to a word line WL1. The first source / drain terminal of the write transistor M5 is coupled to node N1, the second source / drain terminal is considered open (or unconnected), and its control terminal is coupled to a write line SL1.

[0015] The test unit 220 includes test transistors M3 and M6, wherein the first source / drain terminal of test transistor M6 is coupled to node N1, and the second source / drain terminals and control terminals of test transistors M3 and M6 are jointly coupled to the test voltage VTG. In another embodiment, the second source / drain terminal and control terminal of test transistor M3, and the second source / drain terminal and control terminal of test transistor M6 are respectively coupled to the test voltage VTG via separate conductive paths (e.g., via different metal wires or conductors).

[0016] Figure 2B is a schematic diagram of the programmed test of the antifuse unit circuit 200 in Figure 2A. Similar to the antifuse unit 110 of the antifuse unit circuit 100, the read transistor M4 and write transistor M5 of the antifuse unit 210 can be programmed through the test transistor M6. In one embodiment, assuming that the antifuse unit 210 is not programmed, the write transistor M5 does not form a conduction path. Therefore, when the word line WL1 is enabled, a test current IW1 is measured on the test transistor M6, and when the word line WL1 is disabled, no current is measured on the test transistor M6, which indicates that the read transistor M4 is operating normally. Furthermore, under the condition that the word line WL1 is disabled, when the write line SL1 is enabled and disabled, no current is measured on the test transistor M6, which indicates that the write transistor M5 is operating normally (i.e., it is not programmed).

[0017] In another embodiment, assuming the antifuse unit 210 is programmed, the write line SL1 applies a voltage to the write transistor M5 to "break down" its gate oxide layer, thereby forming a conduction path. Therefore, when the word line WL1 is disabled, a test current IS1 is measured on the test transistor M6 when the write line SL1 is enabled, and no current is measured on the test transistor M6 when the write line SL1 is disabled, thus indicating that the write transistor M5 is indeed programmed.

[0018] Figure 3A is a schematic diagram of an antifuse unit circuit 300 according to the present disclosure. The antifuse unit circuit 300 includes antifuse units 110, 210, 310, and 320 and test units 220 and 330, wherein antifuse units 110, 210, and test unit 220 are similar to the antifuse unit circuit 200 in Figure 2A, and will not be described again here for the sake of simplicity. Antifuse unit 310 includes a read transistor M7 and a write transistor M8, antifuse unit 320 includes a read transistor M10 and a write transistor M11, and test unit 330 includes test transistors M9 and M12.

[0019] Read transistor M7: The first source / drain terminal is coupled to bit line BL0, its second source / drain terminal is coupled to node N2, and its control terminal is coupled to word line WL0'. Write transistor M8: The first source / drain terminal is coupled to node N2, and its control terminal is coupled to write line SL0'. Test transistor M9: The first source / drain terminal is coupled to node N2, and its second source / drain terminal and control terminal are both coupled to test voltage VTG. Read transistor M10: The first source / drain terminal is coupled to bit line BL1, its second source / drain terminal is coupled to node N3, and its control terminal is coupled to word line WL1'. Write transistor M11: The first source / drain terminal is coupled to node N3, and its control terminal is coupled to write line SL1'. Test transistor M12: The first source / drain terminal is coupled to node N3, and its second source / drain terminal and control terminal are both coupled to test voltage VTG.

[0020] As shown in Figure 3A, the second source / drain terminals of the write transistors M8 and M11 are marked with "x", representing an open circuit (or disconnected circuit). That is, there is an open circuit between the second source / drain terminals of the write transistors M2 and M8, and there is also an open circuit between the second source / drain terminals of the write transistors M5 and M11. In addition, the write lines SL0 and SL0' are complementary to each other, and the write lines SL1 and SL1' are also complementary to each other. That is, when the write transistor M2 (or M5) is programmed (e.g., the gate oxide layer is "broken down" and a conductive path is formed), the write transistor M8 (or M11) is not programmed (e.g., the gate oxide layer is not "broken down" and remains non-conductive). Conversely, if the written transistor M2 (or M5) is not programmed (e.g., the gate oxide layer is not "broken down" and remains non-conductive), then the written transistor M8 (or M11) is programmed (e.g., the gate oxide layer is "broken down" and a conductive path is formed).

[0021] Thus, the antifuse unit circuit 300 can be regarded as a differential antifuse unit, and the logic "0" and logic "1" of the circuit are represented by the states of the two write transistors (e.g., whether they are "broken down"), which increases the current difference between the two states of logic "0" and logic "1", thereby increasing the accuracy of the circuit. In addition, assuming that the word lines WL0 and WL0', WL1 and WL1' are complementary to each other, and the write lines SL0 and SL0', SL1 and SL1' are also complementary to each other, the antifuse units 110, 310 and the test transistors M3, M9 can be regarded as a set of antifuse units with six-transistors (6T), and the antifuse units 210, 320 and the test transistors M6, M12 can also be regarded as another set of 6T antifuse units.

[0022] Figure 3B is a schematic diagram of the programmed test of the antifuse unit circuit 300 in Figure 3A. Similar to the antifuse units 110 and 210 shown in Figure 2A, the read transistors M7 and M10 and write transistors M8 and M11 in antifuse units 310 and 320 can be tested for normal operation by enabling and / or disabling different word lines and write lines, and measuring the current flowing through the test unit 330. For example, in one embodiment, since word lines WL0 and WL0' are complementary to each other (i.e., when one of word lines WL0 and WL0' is enabled, the other is disabled), when testing the antifuse unit circuit 300, the presence of current flowing through the test unit 220 (e.g., test transistor) and 330 can be measured respectively to determine whether the read transistors M1 and M7 are operating normally. Similarly, by using complementary character lines WL1 and WL1' and test units 220 and 330, it is possible to determine whether read transistors M4 and M10 are operating normally. Furthermore, since write lines SL0 and SL0', and SL1 and SL1' are complementary, it is also possible to determine whether write transistors M2, M5, M8, and M11 are operating normally by using test units 220 and 330.

[0023] In one embodiment, write line SL0 is disabled and write line SL1 is enabled. Therefore, write line SL0' is enabled and write line SL1' is disabled, causing the gate oxide layer of write transistors M5 and M8 to be "broken down" and form a conductive path, while write transistors M2 and M11 maintain their original high impedance state (i.e., forming an open circuit or a broken circuit). Therefore, under the condition that all word lines are disabled, when write line SL0 is disabled and write line SL1 is enabled, only write transistors M5 and M8 should be conducting. At this time, if test currents IS1 and IS0' are measured on test transistor M6 in test unit 220 and test transistor M9 in test unit 330 respectively, it means that write transistors M5 and M8 are operating normally. If only test current IS1 is measured, it means that write transistor M5 is operating normally, while write transistor M8 is not operating normally. If neither of them is measured, it means that the writing to transistors M5 and M8 is abnormal (e.g., transistor manufacturing defects or failure to be successfully programmed).

[0024] The aforementioned test method also applies to write transistors M2 and M11. Specifically, when write transistor M2 is programmed (i.e., a conduction path is formed), if a test current IS0 is measured on test transistor M3 in test unit 220 when write line SL0 is enabled, it indicates that write transistor M2 is operating normally. If no current is measured, it indicates that write transistor M2 is not operating normally (e.g., it has not been successfully programmed). Similarly, when write transistor M11 is programmed, if a test current IS1' is measured on test transistor M12 in test unit 330 when write line SL1' is enabled, it indicates that write transistor M11 is operating normally. If no current is measured on test unit 330, it indicates that write transistor M11 is not operating normally.

[0025] A similar method can also be used to test whether the read transistors M1, M4, M7, and M10 are operating normally. In another embodiment, word line WL0 is enabled and word line WL1 is disabled, causing word line WL0' to be disabled and word line WL1' to be enabled. Thus, read transistors M1 and M10 are turned on, while read transistors M4 and M7 are turned off. At this time, if test currents IW0 and IW1' are measured on test transistor M3 in test unit 220 and test transistor M12 in test unit 330 respectively, it indicates that read transistors M1 and M10 are operating normally. If only test current IW1' is measured, it indicates that read transistor M10 is operating normally, while read transistor M1 is not operating normally. If neither the test currents IW0 nor IW1' are measured, it means that the readings of transistors M1 and M10 are abnormal (e.g., defective transistor manufacturing or failure to be successfully programmed).

[0026] When testing read transistors M4 and M7, the state of the four word lines can be switched to enable word lines WL0' and WL1, thus disabling word lines WL0 and WL0'. This turns on read transistors M4 and M7, and turns off read transistors M1 and M10. If test currents IW1 and IW0' are measured on test transistor M6 in test unit 220 and test transistor M9 in test unit 330, respectively, it indicates that read transistors M4 and M7 are operating normally. If only test current IW0' is measured, it indicates that read transistor M7 is operating normally, while read transistor M4 is not operating normally. If neither test currents IW0' nor IW1 are measured, it indicates that both read transistors M4 and M7 are operating normally.

[0027] It should be noted that since the antifuse unit circuit 300 has two test units, it is possible to perform both read and write transistor tests simultaneously. For example, when testing the antifuse unit circuit 300, since the antifuse units 110, 210 and 310, 320 are coupled to different test units respectively, one of the word lines WL0, WL1 and one of the write lines SL0', SL1' can be enabled simultaneously.

[0028] Figure 4A is a schematic diagram of one of the antifuse unit circuits 400 shown according to this disclosure. Referring to Figures 3A and 4A, the difference between antifuse unit circuit 400 and antifuse unit circuit 300 is that antifuse unit circuit 400 does not include test unit 330. Therefore, the second source / drain terminal of read transistor M7 and the first source / drain terminal of write transistor M8 are instead coupled to node N0, while the second source / drain terminal of read transistor M10 and the first source / drain terminal of write transistor M11 are instead coupled to node N1. Therefore, in antifuse unit circuit 400, antifuse units 110, 210, 310, and 320 can be considered to share test unit 220.

[0029] Figure 4B is a schematic diagram of the programmed test performed on the antifuse unit circuit 400 in Figure 4A. Similar to the antifuse unit circuit 300, the operation of read transistors M1, M4, M7, and M10 and write transistors M2, M5, M8, and M11 can be tested by enabling and disabling different write lines and word lines respectively. For example, when testing read transistors M1, M4, M7, and M10, word lines WL0, WL1, WL0', and WL1' can be enabled respectively, and the corresponding test currents IW0, IW1, IW0', and IW1' can be measured on test transistors M3 or M6. If a test current corresponding to the currently tested read transistor is measured, the read transistor is considered to be operating normally. If not, the read transistor is considered to be operating abnormally.

[0030] Similarly, write lines SL0, SL1, SL0', and SL1' can be enabled respectively to test whether write transistors M2, M5, M8, and M11 have been successfully programmed. In one embodiment, write transistors M2, M5, and M8 are programmed, while write transistor M11 is not programmed. Therefore, when write lines SL0, SL1, and SL0' are enabled respectively, if test currents IS0, IS1, and IS0' are measured on test unit 220 respectively, it means that the write transistor corresponding to the measured test current is operating normally (i.e., successfully programmed). Furthermore, since write transistor M11 is not programmed, if test current IS1 is not measured on test unit 220 regardless of whether write line SL1' is enabled or disabled, it means that write transistor M11 is operating normally.

[0031] It should be noted that although the antifuse unit circuit 400 only shows four antifuse units 110, 210, 310, and 320 coupled together to the test unit 220, the antifuse unit circuit 400 may include more than 2T antifuse units. Specifically, the test unit 220 with test transistors M3 and M6 can be coupled to 2n antifuse units, where n is a positive integer.

[0032] Figure 5 is a layout diagram 500 of the antifuse unit circuit shown in this disclosure. Layout diagram 500 can be considered as a layout diagram of the antifuse unit circuit 300 in Figure 3, and for ease of explanation, some components (such as the detailed structure of transistors) are omitted or simplified. Referring to Figure 3, read transistors M1 and M7 are electrically connected to bit line BL0 through via 510a, while read transistors M4 and M10 are electrically connected to BL1 through via 510b. Furthermore, the gate terminals (or control terminals) of read transistors M1, M4, M7, and M10 are coupled to word lines WL0, WL1, WL0', and WL1', respectively, and the gate terminals (or control terminals) of write transistors M2, M5, M8, and M11 are coupled to write lines SL0, SL1, SL0', and SL1', respectively.

[0033] As shown in Figure 5, the gate (or control) terminals and source / drain terminals of test transistors M3 and M6 are electrically connected to the test voltage VTG through vias 520a and 520b, and the gate (or control) terminals and source / drain terminals of test transistors M9 and M12 are electrically connected to the test voltage VTG through vias 520c and 520d. Therefore, although as shown in Figures 3 and 5, test units 220 (i.e., test transistors M3 and M6) and test units 330 (i.e., test transistors M9 and M12) are not directly connected, but are respectively coupled to the test voltage VTG. In one embodiment, test units 220 and 330 can also be directly connected using a metal wire, so that the test transistors in the two test units share a single port (e.g., via or wiring) coupled to the test voltage VTG.

[0034] It should be noted that, as shown in Figure 5, test units 220 and 330 are circuit elements located inside the antifuse unit circuit. Furthermore, test units 220 and 330 are located between the word line and write line that control the same antifuse unit.

[0035] As can be seen from the embodiments described above, by connecting the antifuse unit to the test unit, each transistor in the antifuse unit can be tested individually. Furthermore, by enabling and disabling the signal lines (e.g., word lines or write lines) corresponding to each transistor, the current flowing through the test unit can be used to determine whether the currently tested transistor is operating normally. In addition, the antifuse unit can be tested both before and after programming, thus not only identifying potentially defective components before programming but also checking whether each component has been programmed as expected or not after programming. [Simplified Explanation of the Diagram]

[0036] Figure 1A is a schematic diagram of the antifuse unit circuit shown in this disclosure. Figure 1B is a schematic diagram of the antifuse unit circuit of Figure 1A undergoing a programmed test. Figure 2A is a schematic diagram of the antifuse unit circuit shown in this disclosure. Figure 2B is a schematic diagram of the antifuse unit circuit of Figure 2A undergoing a programmed test. Figure 3A is a schematic diagram of the antifuse unit circuit shown in this disclosure. Figure 3B is a schematic diagram of the antifuse unit circuit of Figure 3A undergoing a programmed test. Figure 4A is a schematic diagram of the antifuse unit circuit shown in this disclosure. Figure 4B is a schematic diagram of the antifuse unit circuit of Figure 4A undergoing a programmed test. Figure 5 is a layout diagram of the antifuse unit circuit shown in this disclosure.

Claims

1. An antifuse unit circuit, comprising: A first antifuse unit has: a first transistor having a first end coupled to a first bit line, a second end coupled to a first node, and a first control terminal coupled to a first word line; And a second transistor having a first end coupled to the first node and a second control end coupled to a first write line; The first test unit has a first test transistor, wherein a first end of the first test transistor is coupled to the first node, and a second end and a third control end of the first test transistor are simultaneously coupled to a test voltage. In the layout configuration, the first test unit is located in the area between the first word line and the first write line.

2. The antifuse unit circuit as described in claim 1, wherein the test voltage is not lower than the threshold voltage of the first test transistor.

3. The antifuse unit circuit as claimed in claim 1, wherein the second transistor forms a conduction path in response to the first write line programming the first antifuse unit.

4. The antifuse unit circuit as described in claim 1, further comprising: A second antifuse unit has: a third transistor having a first end coupled to a second bit line, a second end coupled to a second node, and a fourth control end coupled to a second word line; And a fourth transistor having a first terminal coupled to the second node and a fifth control terminal coupled to a second write line, wherein the first test unit further includes a second test transistor having a first terminal coupled to the second node, a second terminal coupled to the test voltage and a sixth control terminal.

5. The antifuse unit circuit as claimed in claim 4, wherein the fourth transistor forms a conduction path in response to the programming of the second antifuse unit by the two write lines.

6. The antifuse unit circuit as described in claim 4, further comprising: A third antifuse unit has: a fifth transistor having a first end coupled to the first word line, a second end coupled to the first node, and a seventh control end coupled to a third word line; And a sixth transistor having a first end coupled to the first node and an eighth control end coupled to a third write line; and a fourth antifuse unit having: a seventh transistor having a first end coupled to the second bit line, a second end coupled to the second node, and a ninth control end coupled to a fourth word line; And an eighth transistor having a first end coupled to the second node and a tenth control end coupled to a fourth write line.

7. The antifuse unit circuit as described in claim 4 further includes: A third antifuse unit has: a fifth transistor having a first end coupled to the first word line, a second end coupled to a third node, and a seventh control end coupled to a third word line; And a sixth transistor having a first end coupled to the third node and an eighth control end coupled to a third write line; A fourth antifuse unit has: a seventh transistor having a first end coupled to the second bit line, a second end coupled to a fourth node, and a ninth control end coupled to a fourth word line; And an eighth transistor having a first end coupled to the fourth node and a tenth control end coupled to a fourth write line; And a second test unit, having: a third test transistor having a first terminal coupled to the third node, a second terminal coupled to the test voltage, and an eleventh control terminal; And a fourth test transistor having a first terminal coupled to the fourth node, a second terminal coupled to the test voltage, and a twelfth control terminal.

8. The antifuse unit circuit as described in claim 7, wherein, in the layout configuration, the second test unit is located in the region between the third character line and the third write line.

9. The antifuse unit circuit as claimed in claim 7, wherein the test voltage is not lower than the threshold voltage of the first test transistor, the second test transistor, the third test transistor, and the fourth test transistor.

10. The antifuse unit circuit as described in claim 6 or 7, wherein the second terminal of the sixth transistor is open, the second terminal of the second transistor is open, the second terminal of the fourth transistor is open, and the second terminal of the eighth transistor is open.

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