Memory with input data storage circuits for redundancy shift and store

Abstract

A memory is provided having a plurality of banks. A shared redundancy address decoder decodes a redundancy address for each of the banks to provide a decoded redundancy address to each bank. A serializer serializes the decoded redundancy address into a serialized decoded redundancy address. Each bank includes scan chain to deserialize the serialized decoded redundancy address to recover its decoded redundancy address. The scan chain includes data input latches that are included within corresponding data input paths to the bank. Should one of the banks have a defect, the bank repairs the defect by reconfiguring its resources responsive to its decoded redundancy address.

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