Method for analyzing SRAM voltage parameter and computer readable media

Abstract

A method for analyzing SRAM voltage parameter and a computer readable media are provided. The method for analyzing SRAM voltage parameter includes setting an initial value, an end value and a step value from the initial value to the end value of a test voltage, and then repeating a test on a plurality of memory devices from the initial value to the end value for obtaining fail bit count (FBC) values under different test voltages. FBC slopes under different test voltages are obtained by using a difference between this FBC value and the previous FBC value as the numerator and a difference between this test voltage and the previous test voltage as the denominator. The corresponding test voltages greater than a set value in all FBC slopes are recorded as VCCMIN. A VCCMIN plot is formed to confirm the performance of each memory device.

Description

Technical Field

[0001] This invention relates to a test and analysis technique for semiconductor devices, and more particularly to a method for analyzing memory voltage parameters and a computer-readable medium. Prior Technology

[0002] In semiconductor manufacturing technology, producing a semiconductor product typically involves numerous processes, such as lithography, etching, and ion implantation. This means that a vast number of machines and many complex procedures are required in semiconductor manufacturing. Therefore, those familiar with this technology dedicate themselves to ensuring the proper functioning of machines, maintaining or improving product yield, identifying and confirming problems, and performing machine maintenance, all in order to ensure that the production speed and quality of semiconductor products meet customer requirements.

[0003] Therefore, wafer testing is currently used to identify abnormal or deviated products, and the test results of abnormal products are used to determine the process station that may have problems, such as lithography, etching, and ion implantation processes.

[0004] However, in the early stages of product development, all bits were of poor quality, making it impossible to determine the product's performance and direction for improvement using existing testing methods. Summary of the Invention

[0005] This invention provides a method for analyzing memory voltage parameters, which is applicable to the analysis of semiconductor wafers in the early stages of development.

[0006] The present invention also provides a computer-readable medium that can be used to perform the above-described analysis method.

[0007] A memory voltage parameter analysis method of the present invention includes setting an initial value, an ending value, and a step value from the initial value to the ending value for a test voltage. Then, starting from the initial value and ending at the ending value, multiple memory elements are repeatedly tested to obtain the fail bit count (FBC) value under different test voltages. Using the difference between the current FBC value and the previous FBC value as the numerator and the difference between the current test voltage and the previous test voltage as the denominator, multiple FBC slopes under different test voltages are obtained. All test voltages with FBC slopes greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is plotted to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship graph is VCCMIN, and the vertical axis is the accumulated value (ACC), where ACC represents how much the voltage increases up to 100%.

[0008] Another memory voltage parameter analysis method of the present invention includes setting an initial value, an ending value, and a step value from the initial value to the ending value for a test voltage. Then, starting from the initial value and ending at the ending value, the test is repeatedly performed on multiple memory elements to obtain error bit count (FBC) curves under different test voltages. The FBC curves are then differentiated twice to obtain multiple FBC curvatures under different test voltages. All test voltages corresponding to FBC curvatures greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is plotted to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship graph is VCCMIN, and the vertical axis is the accumulated value (ACC), where the accumulated value is as defined above.

[0009] Another memory voltage parameter analysis method of the present invention includes setting an initial value, a termination value, and a step value from the initial value to the termination value for a test voltage, and then performing the following steps on multiple memory elements respectively: a) Test one of the multiple memory elements with the initial value to obtain a first fail bit count (FBC) value. b) Continuously perform the Nth test on this memory element to obtain the Nth FBC value, wherein the test voltage of the Nth test is the initial value plus (N-1) times the step value, and N is an integer greater than 1. c) Obtain the FBC slope, which is the difference between the current FBC value and the previous FBC value divided by the difference between the current test voltage and the previous test voltage. d) Compare the FBC slope with a set value. If the FBC slope is equal to or less than the set value, return to step b to test the next interval of the test voltage; if the FBC slope is greater than the set value, record the current test voltage as VCCMIN.

[0010] In the previous embodiment of the present invention, the testing of the memory element is ended after VCCMIN is obtained.

[0011] In various embodiments of the present invention, the initial value is the lower limit voltage of the test voltage, and the termination value is the upper limit voltage of the test voltage.

[0012] In various embodiments of the present invention, the memory element described above includes an SRAM element.

[0013] In various embodiments of the present invention, the above-mentioned set value is greater than 0 and less than 100.

[0014] The computer-readable medium of the present invention is a computer-readable medium containing a program. When the computer loads and executes the program, the above-mentioned memory voltage parameter analysis method can be completed.

[0015] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0016] Figure 1 is a flowchart of a memory voltage parameter analysis method according to a first embodiment of the present invention. Figure 2 is a schematic diagram of the result of one of the steps 104 to 106 in Figure 1. Figure 3 is a schematic diagram of the result of another example of step 106 in Figure 1. Figure 4 is a schematic diagram of the result of one example of step 108 in Figure 1. Figure 5 is a VCCMIN relationship diagram obtained from one example of step 110 in Figure 1. Figure 6 is a flowchart of a memory voltage parameter analysis method according to a second embodiment of the present invention. Figure 7 is a flowchart of a memory voltage parameter analysis method according to a third embodiment of the present invention. Implementation

[0017] Figure 1 is a flowchart of a memory voltage parameter analysis method according to a first embodiment of the present invention.

[0018] Referring to Figure 1, the analysis method 100 of the first embodiment first performs step 102, setting the initial value, the termination value, and the step value from the initial value to the termination value of the test voltage. In one embodiment, the initial value is the upper limit voltage of the test voltage, and the termination value is the lower limit voltage of the test voltage. In another embodiment, the initial value is the lower limit voltage of the test voltage, and the termination value is the upper limit voltage of the test voltage. The step value is the voltage value that increases or decreases sequentially throughout the test. For example, if the initial value is assumed to be 1.20V, the termination value is assumed to be 0.72V, and the step value is set to 0.02V, then the test voltage during the entire test will gradually decrease from 1.20V to 0.02V up to 0.72V. The aforementioned initial value, termination value, and step value can be changed according to the product under test and are not limited to a specific range or value.

[0019] The analysis method 100 of the first embodiment further includes step 104, which involves repeatedly testing multiple memory elements from an initial value to an end value to obtain the fail bit count (FBC) value under different test voltages. In some embodiments, the memory elements include static random access memory (SRAM) elements, but are not limited thereto. The memory elements may also be other memory elements, such as dynamic random access memory (DRAM) elements, erasable programmable read-only memory (EPROM) elements, flash memory elements, magnetic random access memory (MRAM) elements, ferroelectric random access memory (FeRAM) elements, phase-change random access memory (PRAM) elements, or resistive random access memory (RRAM) elements.

[0020] The analysis method 100 of the first embodiment further includes step 106, obtaining multiple FBC slopes under different test voltages. The FBC slope is calculated with the difference between the current FBC value and the previous FBC value as the numerator, and the difference between the current test voltage and the previous test voltage as the denominator. Therefore, the FBC slope is as follows: (Current FBC value - Previous FBC value) / (VDD delta) In the above formula, VDD delta is the value of the current test voltage (the chip's operating voltage) minus the previous test voltage.

[0021] The analysis method 100 of the first embodiment further includes step 108, recording all test voltages with FBC slopes greater than a set value as VCCMIN, where VCCMIN refers to the minimum value of VCC (the circuit's supply voltage), which signifies the minimum test voltage at which the tested memory element exhibits an abnormality. The set value is, for example, greater than 0 and less than 100. This set value refers to the point where the FBC slope suddenly increases. For example, an FBC slope close to 0 or 0.5 originally indicates no abnormality in the semiconductor element, but once the FBC value increases significantly, the FBC slope suddenly increases and exceeds the set value. In other words, the test voltage corresponding to the FBC slope exceeding the set value is the circuit supply voltage VCC at which the semiconductor element begins to exhibit an abnormality, so this test voltage is recorded as VCCMIN.

[0022] The analysis method 100 of the first embodiment further includes step 110, plotting a VCCMIN relationship diagram to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship diagram represents the individual VCCMIN values ​​obtained from testing for each memory element, and the vertical axis represents the cumulative value (ACC), where ACC represents how much the voltage increased up to 100%.

[0023] Figures 2 through 5 illustrate examples of memory voltage parameter analysis. Figures 2 through 5 are described with reference to Figure 1.

[0024] Figure 2 shows the FBC value and FBC slope of a memory element from the initial value to the final value, where VDDC = cell voltage and VDD = peripheral circuit voltage. The initial value is set to 1.20V, the final value to 0.72V, and the step value to 0.02V, but it is not necessary to test every point. Of course, it is also possible to test every step value. Therefore, Figure 2 is a schematic diagram of the result of one example of steps 104 to 108 in Figure 1. The slope in Figure 2 is the FBC slope divided by 1000. When the set value is 1, the FBC slope greater than 1 can be obtained from the table in Figure 2, which represents the result of the 6th test. Then, it can be deduced that the test voltage used for the 6th test is the initial value plus 5 times the step value, that is, 0.92V, which is the VCCMIN of the memory element under test.

[0025] Figure 2 shows the test results for a single memory element (chip). After completing step 106 on multiple memory elements, the table shown in Figure 3 is obtained. The table in Figure 3 contains the test results for a total of 42 memory elements (chips). The top column shows the test voltage, and the bottom column shows the FBC values ​​of different chips at different test voltages. Since the 42 memory elements tested were from the first few batches (lots) produced during the early stages of product development, almost all bits showed FBC.

[0026] Then, based on steps 106 and 108 in Figure 1, Figure 4 can be obtained from the results in Figure 3. Figure 4 contains a large amount of data, so some content may not be clear, but this does not affect the understanding of the analytical concept of the present invention by those skilled in the art. The table in Figure 4 shows the test results of 42 memory elements (chips). The top column is the test voltage, the bottom column is the FBC slope of different chips at different test voltages, and the rightmost row lists the VCCMIN of each chip (set to 1). For example, chip 1 has an FBC slope greater than 1 at a test voltage of 1.035V, so the VCCMIN of chip 1 is 1.035V; chip 10's FBC slope is greater than 1 only at a test voltage of 0.900V, so the VCCMIN of chip 10 is 0.900V; and so on.

[0027] The VCCMIN relationship diagram, plotted based on the results in Figure 4, is shown in Figure 5. In Figure 5, the horizontal axis represents VCCMIN, and the vertical axis represents the accumulated value (ACC). ACC is the ratio of VCCMIN to each operating voltage. For example, in Figure 5, a VCCMIN of 0.86V corresponds to an ACC of approximately 55%, indicating that more than 50% of the chips will pass 0.86V, thus affecting the chip's performance.

[0028] Figure 6 is a flowchart of a memory voltage parameter analysis method according to a second embodiment of the present invention, wherein the same technical terms as those in the first embodiment are used to represent the same technical terms, and the content of the first embodiment can be referred to, and will not be repeated here.

[0029] Referring to Figure 6, the analysis method 600 of the second embodiment first performs step 602, setting the initial value, the termination value, and the step value from the initial value to the termination value of the test voltage. In some embodiments, the initial value is the upper limit voltage of the test voltage, and the termination value is the lower limit voltage of the test voltage.

[0030] The analysis method 600 of the second embodiment further includes step 604, which involves repeatedly testing multiple memory elements from an initial value to an end value to obtain error bit count (FBC) curves under different test voltages. That is, each memory element or chip generates an FBC curve after testing, where the horizontal axis of the FBC curve is the test voltage and the vertical axis is the FBC (count).

[0031] The analysis method 600 of the second embodiment includes step 606, which involves performing a second differential on the FBC curve to obtain multiple FBC curvatures under different test voltages. After the second differential, the vertical axis of the FBC curve will clearly show the rate of change of FBC with the test voltage, thus clearly showing the corresponding voltage value of a sudden increase in FBC.

[0032] The analysis method 600 of the second embodiment includes step 608, recording all corresponding test voltages in the FBC curvature that are greater than a set value as VCCMIN, the set value being, for example, greater than 0 and less than 100.

[0033] The analysis method 600 of the second embodiment includes step 610, drawing a VCCMIN relationship diagram to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship diagram is each VCCMIN, and the vertical axis is ACC, where ACC is the accumulated value. Therefore, the resulting VCCMIN relationship diagram will resemble Figure 5.

[0034] Figure 7 is a flowchart of a memory voltage parameter analysis method according to a third embodiment of the present invention, wherein the same technical terms as those in the first embodiment are used to represent the same technical terms, and the content of the first embodiment can be referred to, and will not be repeated here.

[0035] Referring to Figure 7, the analysis method 700 of the third embodiment first performs step 702, setting the initial value, the termination value, and the step value from the initial value to the termination value of the test voltage.

[0036] The analysis method 700 of the third embodiment further includes step 704, which involves performing the following steps on each of the multiple memory elements.

[0037] In step 710, one of the memory elements is tested for the first time with an initial value to obtain the first fail bit count (FBC) value.

[0038] In step 712, the memory element is continuously tested for the Nth time to obtain the Nth FBC value, where the test voltage of the Nth test is the initial value plus a step value of (N-1) times, and N is an integer greater than 1.

[0039] In step 714, the FBC slope is obtained, which is the difference between the current FBC value and the previous FBC value divided by the difference between the current test voltage and the previous test voltage. Therefore, the FBC slope of the second test is (the FBC value of the second test minus the FBC value of the first test) divided by (the test voltage of the second test minus the test voltage of the first test); and so on.

[0040] In step 716, the FBC slope is compared with a set value. If the FBC slope is equal to or less than the set value, the process returns to step 712 to test the next interval of the test voltage. For example, if the set value is 1, and the FBC slope of the second test is equal to or less than 1, the process returns to step 712 to perform the third test, where the test voltage of the third test is the initial value plus twice the step value.

[0041] If the FBC slope is greater than the set value, then proceed to step 718 and record the test voltage as VCCMIN. For example, if the set value is 1, and the FBC slope of the second test is greater than 1, then the test voltage of the second test will be recorded as VCCMIN.

[0042] In some embodiments, the testing of the current memory element can be terminated directly after VCCMIN is obtained. That is, no further testing of the current memory element is required; for example, if the FBC slope obtained in the second test is greater than a set value, there is no need to perform subsequent tests from the third to the Nth time. Therefore, it is expected that the detection time can be reduced.

[0043] Furthermore, after completing step 704, a VCCMIN relationship diagram can be drawn based on the VCCMIN of multiple memory elements, as shown in step 110 of Figure 1. In other embodiments, other analyses or calculations can be performed based on the obtained VCCMIN.

[0044] Another aspect of the present invention relates to a computer-readable medium containing a program that includes instructions for testing integrated circuits. When the computer loads and executes the program, it can perform the memory voltage parameter analysis method described in the above embodiments. In some embodiments, the computer is one or more processors in a testing instrument, or a processor connected to the testing instrument.

[0045] Based on the above, the analysis method provided by the present invention can fix the lower limit voltage and the upper limit voltage in the early stage of product development, use the FBC slope method (or the second derivative method) and scan all memory components of the memory chip under the test voltage to perform data storage and read / write function tests. This can further provide more comprehensive information for subsequent memory low yield analysis or process / component adjustment, and provide an important basis for improving memory yield.

[0046] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0047] 100, 600, 700: Analysis Methods 102, 104, 106, 108, 110, 602, 604, 606, 608, 610, 702, 704, 710, 712, 714, 716, 718: Steps

Claims

1. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. Starting from the initial value and ending at the final value, multiple memory elements are repeatedly tested to obtain the fail bit count (FBC) value under different test voltages. Using the difference between the current FBC value and the previous FBC value as the numerator and the difference between the current test voltage and the previous test voltage as the denominator, multiple FBC slopes under different test voltages are obtained. All test voltages with slopes greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is then plotted to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship graph is VCCMIN, and the vertical axis is the accumulated value (ACC), where the accumulated value is the ratio of VCCMIN to the operating voltage, and this ratio ranges from 0% to 100%.

2. The memory voltage parameter analysis method as described in claim 1, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

3. The memory voltage parameter analysis method as described in claim 1, wherein the set value is greater than 0 and less than 100.

4. The memory voltage parameter analysis method as described in claim 1, wherein the memory element includes an SRAM element.

5. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. Starting from the initial value and ending at the final value, multiple memory elements are repeatedly tested to obtain multiple fail bit count (FBC) curves under different test voltages; the multiple FBC curves are differentiated twice to obtain multiple FBC curvatures under different test voltages; all test voltages corresponding to the multiple FBC curvatures that are greater than a set value are recorded as VCCMIN, where the set value is greater than 0 and less than 100; and a VCCMIN relationship graph is plotted to confirm the performance of each memory element, where the horizontal axis of the VCCMIN relationship graph is VCCMIN and the vertical axis is the accumulated value (ACC), where the accumulated value represents how much it increases by up to 100% at each voltage.

6. The memory voltage parameter analysis method as described in claim 5, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

7. The memory voltage parameter analysis method as described in claim 5, wherein the memory element includes an SRAM element.

8. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. The following steps are performed on multiple memory elements: a) Test one of the multiple memory elements with the initial value to obtain the first fail bit count (FBC) value; b) Continuously test the memory element for the Nth time to obtain the Nth FBC value, wherein the test voltage of the Nth test is the initial value plus (N-1) times the step value, where N is an integer greater than 1; c) Obtain the FBC slope, which is the difference between the current FBC value and the previous FBC value divided by the difference between the current test voltage and the previous test voltage. And d) Compare the FBC slope with a set value. If the FBC slope is equal to or less than the set value, return to step b to perform the test of the next interval of the test voltage; if the FBC slope is greater than the set value, record the test voltage as VCCMIN.

9. The memory voltage parameter analysis method as described in claim 8, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

10. The memory voltage parameter analysis method as described in claim 8, wherein the memory element includes an SRAM element.

11. The memory voltage parameter analysis method as described in claim 8, wherein the set value is greater than 0 and less than 100.

12. The memory voltage parameter analysis method as described in claim 8, wherein the test of a memory element is terminated after obtaining the VCCMIN.

13. A computer-readable medium containing a program, which, when loaded and executed by a computer, can perform a memory voltage parameter analysis method as described in any one of claims 1 to 12.

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