Low ohm chip resistor

Abstract

A low ohm chip resistor includes a carrier, a resistance layer, first to fourth inner electrodes, an insulating protection layer, and first and second outer electrodes. The carrier has first and second surfaces opposite to each other, and first and second end surfaces opposite to each other. The resistance layer is disposed on the first surface. The resistance layer includes a resistance functional area, and first and second electrode areas located on two sides of the resistance functional area. The resistance layer has first and second grooves adjacent to the first and second electrode areas. The first and second inner electrodes are disposed on the first and second electrode areas. The insulating protection layer covers the resistance functional area and portions of the first and second inner electrodes. The third and fourth inner electrodes are disposed on the second surface. The first outer electrode covers a portion of the insulating protection layer, the first inner electrode, and the third inner electrode, and the second outer electrode covers another portion of the insulating protection layer, the second inner electrode, and the fourth inner electrode.

Description

Technical Field

[0001] This disclosure relates to a manufacturing technique for an electronic component, and more particularly to a low-resistance chip resistor. Prior Technology

[0002] A typical low-resistance resistor mainly consists of a resistive layer and a pair of terminals on either side of the resistive layer. The resistive layer is made of various types of copper alloys, and the terminals are also made of copper. Shunt-type resistors can be all-metal blocks formed by welding metal alloys and copper terminals. Chip-type resistors have a carrier on one side of the resistive layer, and the main resistive layer and some of the inner electrodes are covered with a resin protective layer to prevent oxidation. An outer electrode is provided around the inner electrode to facilitate soldering.

[0003] Low-resistance resistors are generally used in products for current measurement. However, the resistance value of low-resistance resistors varies greatly with temperature. Therefore, reducing the temperature coefficient of resistance (TCR) of low-resistance resistors has become a key focus of research and development.

[0004] Some low-resistance resistors utilize slot or four-terminal designs for voltage measurement to reduce the temperature coefficient of resistance (TCR) of low-resistance resistors. While designing the voltage sampling points can reduce the TCR of low-resistance resistors, this technique has limitations in product miniaturization. For example, it is difficult to manufacture products smaller than an SMD1206 using this technique. Furthermore, different voltage sampling points need to be designed for different applications, which increases the difficulty of using the resistors or mounting them on printed circuit boards.

[0005] On the other hand, chip-type resistors can only reduce the temperature coefficient of resistance by utilizing the inherent properties of the material itself. This presents material limitations for resistors with extremely low resistance values ​​(<5mΩ), making it impossible to further reduce the temperature coefficient of resistance. Summary of the Invention

[0006] Therefore, one of the objectives of this disclosure is to provide a low-resistance chip resistor that can effectively reduce the temperature coefficient of resistance of the low-resistance chip resistor by reducing the current density at the voltage measurement point, thereby improving the measurement accuracy of the low-resistance chip resistor.

[0007] According to the above-mentioned objectives of this disclosure, a low-resistance wafer resistor is proposed, comprising a carrier, a resistive layer, a first inner electrode, a second inner electrode, an insulating protective layer, a third inner electrode, a fourth inner electrode, a first outer electrode, and a second outer electrode. The carrier has a first surface and a second surface opposite to each other, and a first end face and a second end face opposite to each other. The resistive layer is disposed on the first surface. The resistive layer includes a resistance functional region, and a first electrode region and a second electrode region located on opposite sides of the resistance functional region. The resistive layer has a first groove and a second groove located in the middle region of the resistance functional region and adjacent to the first electrode region and the second electrode region, respectively. The first inner electrode is disposed on the first electrode region. The second inner electrode is disposed on the second electrode region. The insulating protective layer covers the resistance functional region, a portion of the first inner electrode, and a portion of the second inner electrode. The third inner electrode is disposed on the second surface and opposite to the first inner electrode. The fourth inner electrode is disposed on the second surface and opposite to the second inner electrode. The first outer electrode covers a portion of the insulating protective layer, the first inner electrode, the first end face, and the third inner electrode. The second outer electrode covers another part of the insulating protective layer, the second inner electrode, the second end face, and the fourth inner electrode, and is separated from the first outer electrode.

[0008] According to one embodiment of the present disclosure, the aforementioned low-resistance chip resistor further includes an adhesive layer between the first surface of the carrier and the resistive layer.

[0009] According to one embodiment of this disclosure, the first groove and the second groove do not penetrate the resistive layer, and the depth of the first groove and the second groove is 50 μm to 150 μm.

[0010] According to one embodiment of this disclosure, both the first groove and the second groove are inverted U-shaped grooves. Both the first groove and the second groove include a first portion, a second portion, and a third portion. The second and third portions of the first groove extend from the first portion of the first groove toward the first electrode region. The second and third portions of the second groove extend from the first portion of the second groove toward the second electrode region.

[0011] According to one embodiment of this disclosure, the length and width of the first groove and the second groove are respectively 1 / 5 to 1 / 3 of the length of the resistance functional area and 1 / 5 to 1 / 3 of the width of the resistance functional area. In each of the first groove and the second groove, the distance between the second portion and the third portion is 1 / 5 to 1 / 3 of the width of each of the first groove and the second groove, and the length of the second portion and the third portion is 1 / 5 to 1 / 3 of the length of each of the first groove and the second groove.

[0012] According to one embodiment of this disclosure, the resistive layer further has a third groove and a fourth groove. The third groove extends from the first electrode region to the first groove. The fourth groove extends from the second electrode region to the second groove. The first external electrode has a fifth groove correspondingly located above the third groove. The second external electrode has a sixth groove correspondingly located above the fourth groove.

[0013] According to one embodiment of this disclosure, the third and fourth grooves do not penetrate the resistive layer, and the depths of the third and fourth grooves are both 5 μm to 50 μm.

[0014] According to one embodiment of this disclosure, both the third and fourth grooves are inverted T-shaped grooves and include a fourth portion and a fifth portion that engage with each other. The fourth portion of the third groove and the fourth portion of the fourth groove respectively extend longitudinally through the first electrode region and the second electrode region in one direction. The fifth portion of the third groove is located between the second and third portions of the first groove. The fifth portion of the fourth groove is located between the second and third portions of the second groove.

[0015] According to one embodiment of this disclosure, the length of the fourth portion of the third groove is 50 μm to 250 μm, and the distance between it and the outer side of the first electrode region is 1 / 4 to 1 / 2 of the length of the first electrode region. The length of the fourth portion of the fourth groove is 50 μm to 250 μm, and the distance between it and the outer side of the second electrode region is 1 / 4 to 1 / 2 of the length of the second electrode region.

[0016] According to one embodiment of the present disclosure, the length and width of the third inner electrode and the fourth inner electrode are respectively 25% to 35% of the length and 80% to 95% of the width of the low-resistance chip resistor.

[0017] According to the above embodiments, the middle region of the resistance functional area of ​​the resistance layer of the disclosed low-resistance chip resistor is provided with a first groove and a second groove, which can concentrate the current path on both sides of the first groove and the second groove and in the middle of the resistance functional area. In this way, the current density in the middle region between the first external electrode and the second external electrode can be significantly reduced, thereby reducing the thermal impact of the current on the measurement, and further reducing the resistance temperature coefficient of the low-resistance chip resistor and improving the accuracy of resistance measurement.

[0018] Furthermore, the resistive layer can be provided with a third and a fourth groove, allowing the first and second external electrodes to form corresponding fifth and sixth grooves. The fifth and sixth grooves allow the current to bypass the solder pads on the circuit board via shorter current paths outside the fifth and sixth grooves. This reduces the current density at voltage measurement points on the circuit board, further improving measurement accuracy. Moreover, the presence of the fifth and sixth grooves makes it easier for solder paste to fill the first and second external electrodes, thus improving the stability of low-resistance chip resistors soldered onto the circuit board. Simple Explanation of the Diagram

[0019] A better understanding of the features disclosed herein can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion. [Figure 1] is a perspective view of a low-resistance chip resistor according to one embodiment of the present disclosure. [Figure 2] is a perspective view of a low-resistance chip resistor according to one embodiment of the present disclosure. [Figure 3] is a schematic cross-sectional view of a low-resistance chip resistor obtained along section line AA of Figure 1. [Figure 4] is a schematic cross-sectional view of a low-resistance chip resistor obtained along section line BB of Figure 1. Figures 5 through 16 are schematic diagrams illustrating various manufacturing stages of a low-resistance wafer resistor according to one embodiment of this disclosure. [Figure 17] is a schematic diagram illustrating the current flow when measuring the resistance of a low-resistance chip resistor according to one embodiment of the present disclosure. [Figure 18] is a schematic diagram showing the current flow when measuring the resistance of a conventional low-resistance chip resistor. [Figure 19] is a box plot comparing the resistance temperature coefficient data of a low-resistance chip resistor according to one embodiment of the present disclosure and a conventional low-resistance chip resistor when measuring resistance. Implementation

[0020] The embodiments of this disclosure are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of this disclosure. All embodiments of this disclosure disclose a variety of different features, but these features can be implemented individually or in combination as needed.

[0021] Furthermore, the terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0022] The spatial relationship between the two components described in this disclosure applies not only to the orientation shown in the diagrams, but also to orientations not shown in the diagrams, such as inverted orientations. Furthermore, the terms "connection," "electrical connection," or similar expressions used in this disclosure to refer to the two components are not limited to a direct or electrical connection, but may also include indirect or electrical connections as needed.

[0023] Besides the material itself and the resistance contribution of the electrode pairs, the inventors have discovered that current density also affects the temperature coefficient of resistance in resistor products. Since the temperature of the area through which current flows rises locally, when the temperature at the voltage sampling point (sensor point) of the resistor rises due to current density, it affects the accuracy of voltage measurement, and consequently, the temperature coefficient of the resistor itself. Therefore, this disclosure proposes a low-resistance chip resistor that can reduce the current density at the voltage measurement point, thereby reducing the temperature coefficient of resistance of the low-resistance chip resistor and improving the accuracy of the temperature coefficient of resistance measurement.

[0024] Please refer to Figures 1 to 4, which are perspective views of a low-resistance chip resistor 10 according to one embodiment of this disclosure from two different perspectives, and a cross-sectional view of the low-resistance chip resistor 10 obtained along section lines AA and BB in Figure 1. The low-resistance chip resistor 10 is a resistor with a resistance value of less than 1Ω. The low-resistance chip resistor 10 can be used as a resistor for automotive applications or voltage sensing in medical, communication, automotive charging piles, battery management systems (BMS), and engine control units (ECUs).

[0025] As shown in Figures 3 and 4, the low-resistance chip resistor 10 mainly includes a carrier 100, a resistive layer 200, a first inner electrode 300, a second inner electrode 400, an insulating protective layer 500, a third inner electrode 600, a fourth inner electrode 700, a first outer electrode 800, and a second outer electrode 900. The carrier 100 can be used to carry other components of the low-resistance chip resistor 10. The carrier 100 can be square or rectangular. The carrier 100 has a first surface 110 and a second surface 120 opposite to each other, and a first end face 130 and a second end face 140 opposite to each other. For example, the first surface 110 and the second surface 120 can be the upper and lower surfaces of the carrier 100, respectively, and the first end face 130 and the second end face 140 can be the two sides of the carrier 100 and located between the first surface 110 and the second surface 120. The carrier 100 can be, for example, polyimide (PI), FR4, glass, ceramic, or epoxy resin.

[0026] A resistive layer 200 is disposed on the first surface 110 of the carrier 100. The resistive layer 200 may be disposed on the first surface 110 of the carrier 100, for example, by sputtering. As shown in Figures 3 and 4, in some embodiments, the low-resistance wafer resistor 10 further includes an adhesive layer AD. The adhesive layer AD is disposed on the first surface 110 of the carrier 100. Furthermore, the resistive layer 200 may be an alloy metal sheet and may be bonded to the first surface 110 of the carrier 100 through the adhesive layer AD. Therefore, the adhesive layer AD is located between the first surface 110 of the carrier 100 and the resistive layer 200.

[0027] As shown in Figures 3, 4, and 7, the resistive layer 200 includes a resistance functional region 210, a first electrode region 220, and a second electrode region 230. The first electrode region 220 and the second electrode region 230 are located on opposite sides of the resistance functional region 210. As shown in Figure 9, both the first electrode region 220 and the second electrode region 230 have a length CL and a width CW. In some embodiments, the width CW is between 80% and 95% of the width W of the low-resistance chip resistor 10, and the length CL is between 1 / 6 and 2 / 6 of the length L of the low-resistance chip resistor 10. The width RW of the resistance functional region 210 is between 40% and 80% of the width W of the low-resistance chip resistor 10. The design that the width RW of the resistance functional region 210 is smaller than the width W of the low-resistance chip resistor 10 can prevent the edges of the resistance functional region 210 from being plated during electroplating, thus avoiding short circuits.

[0028] As shown in Figures 3 and 9, the resistance functional area 210 has a first groove 240 and a second groove 250 separated from each other. The first groove 240 and the second groove 250 are located on opposite sides of the middle region of the resistance functional area 210. The first groove 240 is adjacent to the first electrode region 220, and the second groove 250 is adjacent to the second electrode region 230. The first groove 240 and the second groove 250 can increase the resistance of their respective regions, thereby driving current to flow to both sides and reducing the current density in these regions. Since the voltage measurement point of the low-resistance chip resistor 10 is generally located in the middle region of the resistance functional area 210, the arrangement of the first groove 240 and the second groove 250 can reduce the current density at the voltage measurement point, thereby improving the accuracy of voltage measurement.

[0029] The first groove 240 and the second groove 250 may penetrate the resistive layer 200, or they may not. In some embodiments, the first groove 240 and the second groove 250 do not penetrate the resistive layer 200 to improve process yield. For example, the thickness of the resistive layer 200 may be from 75 μm to 500 μm, and the depth of the first groove 240 and the second groove 250 may be from 50 μm to 150 μm.

[0030] The shapes of the first groove 240 and the second groove 250 can be designed according to product specifications and process requirements. As shown in Figure 9, in some embodiments, both the first groove 240 and the second groove 250 are inverted U-shaped grooves. Specifically, the first groove 240 includes a first portion 242, a second portion 244, and a third portion 246, with the second portion 244 and the third portion 246 extending from the first portion 242 toward the first electrode region 220. Similarly, the second groove 250 includes a first portion 252, a second portion 254, and a third portion 256, with the second portion 254 and the third portion 256 extending from the first portion 252 toward the second electrode region 230.

[0031] Both the first groove 240 and the second groove 250 have a length RL1 and a width d. A distance RL2 separates the first groove 240 and the second groove 250. The length RL of the resistance function area 210 is length RL1*2 + distance RL2. The second portions 244 and 254 and the third portions 246 and 256 each have a length b. A spacing a exists between the second portions 244 and 246 of the first groove 240 and between the second portions 254 and 256 of the second groove 250. In some embodiments, the length RL1 and width d of the first groove 240 and the second groove 250 are 1 / 5 to 1 / 3 of the length RL and width RL of the resistance function area 210, respectively. Furthermore, the spacing a is 1 / 5 to 1 / 3 of the width d of the first groove 240 and the second groove 250. The length b of the second part 244 and 254 and the third part 246 and 256 is 1 / 5 to 1 / 3 of the length RL1 of the first groove 240 and the second groove 250.

[0032] As shown in Figures 3 and 11, in some embodiments, the resistive layer 200 further comprises a third groove 260 and a fourth groove 270. The third groove 260 extends from the first electrode region 220 to the first groove 240 and is connected to the first groove 240. The fourth groove 270 extends from the second electrode region 230 to the second groove 250 and is connected to the second groove 250. The third groove 260 and the fourth groove 270 do not penetrate the resistive layer 200. In some embodiments, the depth of the third groove 260 and the fourth groove 270 is 5 μm to 50 μm. The provision of the third groove 260 and the fourth groove 270 allows the electrode structures subsequently formed on the first electrode region 220 and the second electrode region 230 to have corresponding grooves, thereby facilitating the planning of current paths and the upper board soldering of the low-resistance chip resistor 10.

[0033] As shown in Figure 11, in some embodiments, both the third groove 260 and the fourth groove 270 are inverted T-shaped grooves. Specifically, the third groove 260 includes a fourth portion 262 and a fifth portion 264, the fifth portion 264 being engaged with one side of the fourth portion 262 and extending toward the first groove 240. In some embodiments, the fourth portion 262 extends longitudinally through the first electrode region 220 along direction D. Direction D may be, for example, parallel to the width direction of the low-resistance chip resistor 10. The fourth portion 262 may extend in the first electrode region 220 but does not longitudinally penetrate the entire first electrode region 220. The fifth portion 264 extends from the fourth portion 262 to between the second portion 244 and the third portion 246 of the first groove 240. The fifth portion 264 may be engaged with the first portion 242, the second portion 244, and the third portion 246.

[0034] Similarly, the fourth groove 270 includes a fourth portion 272 and a fifth portion 274, the fifth portion 274 engaging one side of the fourth portion 272 and extending toward the second groove 250. In some embodiments, the fourth portion 272 extends longitudinally through the second electrode region 230 in direction D. The fourth portion 272 may extend longitudinally through the entire second electrode region 230. The fifth portion 274 extends from the fourth portion 272 to between the second portion 254 and the third portion 256 of the second groove 250, and may engage with the first portion 252, the second portion 254, and the third portion 256.

[0035] As shown in Figure 11, both the fourth portions 262 and 272 have a length c. A distance g is provided between the fourth portion 262 and the outer side of the first electrode region 220, and between the fourth portion 272 and the outer side of the second electrode region 230. In some embodiments, the length c is between 50 μm and 250 μm. If the length c is less than 50 μm, the grooves of the subsequently formed electrode structure will be too small, making it difficult for solder paste to fill during board mounting. If the length c is greater than 250 μm, the grooves of the subsequently formed electrode structure will be too large, resulting in insufficient solder paste filling during board mounting. Both of these situations will cause a decrease in the bonding strength between the low-resistance chip resistor 10 and the printed circuit board. Furthermore, the distance g is 1 / 4 to 1 / 2 of the length CL of the first electrode region 220 and the second electrode region 230 (as shown in Figure 9), so that the third groove 260 and the fourth groove 270 can be located in the central regions of the first electrode region 220 and the second electrode region 230, respectively.

[0036] In some embodiments, the resistive layer 200 includes one or more resistance-correcting grooves 280. For example, the resistance-correcting grooves 280 may be recessed into the resistance functional region 210. The resistive layer 200 may be a metal alloy. For example, the material of the resistive layer 200 may be a copper-manganese alloy (MnCu), a copper-nickel alloy (CuNi), a copper-manganese-nickel alloy (CuMnNi), a copper-manganese-tin alloy (CuMnSn), a nickel-chromium-aluminum alloy (NiCrAl), a nickel-chromium-aluminum-silicon alloy (NiCrAlSi), or an iron-chromium-aluminum alloy (FeCrAl). However, the material of the resistive layer 200 may be other suitable resistive materials, and this disclosure is not limited thereto.

[0037] Referring simultaneously to Figures 3, 4, and 14, the first inner electrode 300 is disposed on the first electrode region 220 and a portion of the resistance functional region 210. Specifically, the first inner electrode 300 covers the first electrode region 220 and a portion of the resistance functional region 210, and fills the fourth portion 262 and the fifth portion 264 of the third groove 260. The first inner electrode 300 has a groove 310. The position and shape of this groove 310 correspond to the third groove 260, and the size of the groove 310 may be equal to or smaller than the third groove 260.

[0038] The second internal electrode 400 is disposed on the second electrode region 230 and a portion of the resistance functional region 210. Specifically, the second internal electrode 400 covers the second electrode region 230 and a portion of the resistance functional region 210, and fills the fourth portion 272 and the fifth portion 274 of the fourth groove 270. The second internal electrode 400 has a groove 410. The position and shape of this groove 410 correspond to the fourth groove 270, and the size of the groove 410 may be equal to or smaller than the fourth groove 270. The materials of the first internal electrode 300 and the second internal electrode 400 may be, for example, copper.

[0039] As shown in Figures 4 and 15, the insulating protective layer 500 extends and covers the resistance functional region 210, a portion of the first internal electrode 300, and a portion of the second internal electrode 400. For example, the insulating protective layer 500 covers the entire resistance functional region 210, a portion of the first internal electrode 300 located in the fifth portion 264 of the third groove 260, and a portion of the second internal electrode 400 located in the fifth portion 274 of the fourth groove 270. The insulating protective layer 500 may also cover the carrier 100 on both sides of the resistance functional region 210. The insulating protective layer 500 protects the resistive layer 200 from oxidation. The material of the insulating protective layer 500 may be, for example, epoxy resin, resin, epoxy resin containing fillers, or polyimide, etc., as an insulating material.

[0040] As shown in Figures 3, 4, and 16, the third inner electrode 600 is disposed on the second surface 120 of the carrier 100 and is opposite to the first inner electrode 300. The fourth inner electrode 700 is also disposed on the second surface 120 and is opposite to the second inner electrode 400. The third inner electrode 600 and the fourth inner electrode 700 are spaced apart from each other. Both the third inner electrode 600 and the fourth inner electrode 700 have a length BCL and a width BCW. In some embodiments, the length BCL is 25% to 35% of the length L of the low-resistance chip resistor 10, and the width BCW is 80% to 95% of the width W of the low-resistance chip resistor 10. The materials of the third inner electrode 600 and the fourth inner electrode 700 may be, for example, a mixture of epoxy resin and silver, or copper.

[0041] As shown in Figures 3 and 4, the first outer electrode 800 covers the insulating protective layer 500, the first inner electrode 300, the first end face 130, and the third inner electrode 600. The second outer electrode 900 covers another portion of the insulating protective layer 500, the second inner electrode 400, the second end face 140, and the fourth inner electrode 700. The second outer electrode 900 and the first outer electrode 800 are opposite to each other and spaced apart. The cross-sectional shape of the first outer electrode 800 can be C-shaped, and the cross-sectional shape of the second outer electrode 900 can be an inverted C-shaped.

[0042] In some embodiments, the first external electrode 800 includes a copper layer 810, a nickel layer 820, and a tin layer 830 stacked sequentially from the inside out. The second external electrode 900 includes a copper layer 910, a nickel layer 920, and a tin layer 930 stacked sequentially from the inside out. As shown in FIG4, in some exemplary embodiments, the distance h between the top surface 812 of the copper layer 810 and the top surface 510 of the insulating protective layer 500 is greater than 5 μm. This prevents excessive solder paste from entering between the insulating protective layer 500 and the circuit board, thus affecting the bonding between the low-resistance chip resistor 10 and the external circuit board.

[0043] Referring simultaneously to Figures 1 and 4, the first external electrode 800 has a fifth groove 840 located above the third groove 260 of the resistive layer 200. Groove 310 is located between the fifth groove 840 and the third groove 260. The positions and shapes of the fifth groove 840, the third groove 260, and the groove 310 correspond, and the size of the fifth groove 840 may be equal to or smaller than that of the groove 310. The second external electrode 900 has a sixth groove 940 located above the fourth groove 270. Groove 410 is located between the sixth groove 940 and the fourth groove 270. The positions and shapes of the sixth groove 940, the fourth groove 270, and the groove 410 correspond, and the size of the sixth groove 940 may be equal to or smaller than that of the groove 410. Therefore, the fifth groove 840 and the sixth groove 940 can be T-shaped grooves.

[0044] The fifth groove 840 of the first external electrode 800 and the sixth groove 940 of the second external electrode 900 allow the current to flow through the solder pads of the low-resistance chip resistor 10 after it has been soldered onto the circuit board, as the current path is shorter at the non-grooved locations. This reduces the current density at voltage measurement points on the circuit board, thereby improving the accuracy of voltage measurements. Furthermore, during soldering, the presence of the fifth groove 840 and the sixth groove 940 makes it easier for solder paste to fill the first external electrode 800 and the second external electrode 900 of the low-resistance chip resistor 10, thus improving the bonding strength and stability of the low-resistance chip resistor 10 to the circuit board.

[0045] In some embodiments, the depth of the fifth groove 840 and the sixth groove 940 is 5 μm to 50 μm. If the depth of the fifth groove 840 and the sixth groove 940 exceeds 50 μm, it may cause too much solder paste to flow into the fifth groove 840 and the sixth groove 940, resulting in insufficient solder on the solder surface and making it difficult to solder.

[0046] Please refer to Figures 5 to 16, which are schematic diagrams illustrating various manufacturing stages of a low-resistance chip resistor 10 according to one embodiment of this disclosure. When fabricating the low-resistance chip resistor 10 as shown in Figures 1 to 4, a carrier 100 is first provided, and then a resistive layer 200 is formed on the first surface 110 of the carrier 100, as shown in Figure 5. As shown in Figure 3, in an embodiment where the low-resistance chip resistor 10 has an bonding layer AD, the resistive layer 200 can be an alloy resistive foil, which is bonded to the first surface 110 of the carrier 100 through the bonding layer AD. In an embodiment where the low-resistance chip resistor 10 does not have a bonding layer AD, the resistive layer 200 can be formed on the first surface 110 using, for example, sputtering.

[0047] Next, as shown in Figure 6, a mask layer M1 can be applied to the resistive layer 200 using methods such as printing, lamination, coating, or photolithography. The mask layer M1 is a patternable and removable etch-resistant protective layer. The material used to etch the mask layer M1 can be, for example, photoresist, a removable adhesive film, or a strippable ink. The area of ​​the resistive layer 200 not covered by the mask layer M1 is the area to be etched, primarily the edges of the resistive layer 200, to etch out the designed width of the resistive layer 200.

[0048] Then, using an alloy metal etching solution such as ferric chloride, copper chloride, sulfuric acid, phosphoric acid, or nitric acid, the areas of the resistive layer 200 not covered by the masking layer M1 are etched until the underlying carrier 100 or bonding layer AD is exposed. After etching the resistive layer 200, the masking layer M1 can be removed using, for example, a film-removing solvent or water washing to expose the resistive layer 200, as shown in Figure 7.

[0049] Next, as shown in Figure 8, a mask layer M2 can be applied to the resistive layer 200 using methods such as printing, lamination, coating, or photolithography. The mask layer M2 is a patternable and removable etch-resistant protective layer. The material of the mask layer M2 can be, for example, photoresist, a removable adhesive film, or a peelable ink. The areas of the resistive layer 200 not covered by the mask layer M2 are the etching areas 202 and 204. In the embodiment shown in Figure 8, the etching areas 202 and 204 are a pair of opposite inverted U-shaped areas.

[0050] Subsequently, using an alloy metal etching solution such as ferric chloride, copper chloride, sulfuric acid, phosphoric acid, or nitric acid, the areas 202 and 204 of the resistor layer 200 to be etched are micro-etched to define the first groove 240 and the second groove 250 in the resistance functional area 210. In some embodiments, this micro-etching operation controls the etching depth to 50 μm to 150 μm, without etching through the resistor layer 200 but exposing the lower part of the resistor layer 200. After forming the first groove 240 and the second groove 250, the mask layer M2 can be removed by, for example, a film-removing solvent or water washing to expose the resistor layer 200, as shown in FIG9.

[0051] Next, as shown in Figure 10, a mask layer M3 can be applied to the resistive layer 200 using methods such as printing, lamination, coating, or photolithography. The mask layer M3 is a patternable and removable etch-resistant protective layer, such as a photoresist layer, a removable adhesive film, or a peelable ink layer. The areas of the resistive layer 200 not covered by the mask layer M3 are the etching areas 206 and 208. In the embodiment shown in Figure 10, the etching areas 206 and 208 are a pair of opposite inverted T-shaped areas.

[0052] Then, using an alloy metal etching solution such as ferric chloride, copper chloride, sulfuric acid, phosphoric acid, or nitric acid, the areas 206 and 208 of the resistor layer 200 to be etched are micro-etched to define the third groove 260 and the fourth groove 270 in the resistor layer 200. In some embodiments, this micro-etching operation controls the etching depth to 5 μm to 50 μm, thus exposing the underlying resistor layer 200 without etching through it. Subsequently, the mask layer M3 can be removed using, for example, a film-removing solvent or water washing to expose the resistor layer 200, as shown in FIG11. At this point, the architecture of the resistor layer 200 is complete. The architecture and dimensions of each part of the resistor layer 200 have been described above and will not be repeated here.

[0053] Next, as shown in Figure 12, a mask layer M4 can be applied to a portion of the exposed first surface 110 of the resistive layer 200 and the carrier 100 using methods such as printing, lamination, coating, or photolithography. The mask layer M4 is a patternable and removable anti-plating protective layer, such as a photoresist layer, a removable adhesive film, or a peelable ink layer. At this time, the area not covered by the mask layer M4 is the area to be plated with the inner electrodes, namely the first electrode area 220, the second electrode area 230, and part of the resistance function area 210.

[0054] Next, as shown in Figure 13, a first internal electrode 300 can be formed on the first electrode region 220 and a portion of the resistance functional region 210 of the resistive layer 200, and a second internal electrode 400 can be formed on the second electrode region 230 and another portion of the resistance functional region 210, for example, by electroplating. The material of the first internal electrode 300 and the second internal electrode 400 can be, for example, copper.

[0055] After completing the first inner electrode 300 and the second inner electrode 400, the mask layer M4 can be removed using, for example, a film-removing solvent or water washing, exposing the resistance functional area 210 covered by the mask layer M4 and the first surface 110 of the carrier 100. Next, depending on product requirements, a resistance-adjusting operation can be selectively performed on the resistance functional area 210 of the resistance layer 200 to adjust the resistance value of the resistance layer 200. As shown in FIG14, the resistance-adjusting operation removes at least a portion of the resistance layer 200, forming a resistance-adjusting groove 280 in the resistance layer 200. For example, the resistance-adjusting operation can be performed using laser or physical processing methods.

[0056] Next, an insulating protective layer 500 can be formed using methods such as printing, lamination, or photolithography. As shown in Figures 4 and 15, the insulating protective layer 500 covers the resistance functional area 210 of the resistive layer 200, a portion of the first electrode area 220 and a portion of the first inner electrode 300 thereon, and a portion of the second electrode area 230 and a portion of the second inner electrode 400 thereon. The insulating protective layer 500 also fills the first groove 240, the second groove 250, and the resistance repair groove 280, and covers a portion of the exposed first surface 110 of the carrier 100.

[0057] Next, as shown in FIG16, a third internal electrode 600 can be formed on a portion of the second surface 120 of the carrier 100, and a fourth internal electrode 700 can be formed on another portion of the second surface 120, for example, by printing or sputtering. The third internal electrode 600 and the fourth internal electrode 700 are respectively opposite to the first internal electrode 300 and the second internal electrode 400.

[0058] Subsequently, as shown in Figures 1 to 4, the first external electrode 800 and the second external electrode 900 are formed using, for example, electroplating, to complete the fabrication of the low-resistance wafer resistor 10. The first external electrode 800 and the second external electrode 900 are opposite to each other and spaced apart. The first external electrode 800 extends from the portion of the insulating protective layer 500 adjacent to the first internal electrode 300, through the first end face 130 of the first internal electrode 300 and the carrier 100 to the second surface 120 of the carrier 100, and covers the first internal electrode 300 and the third internal electrode 600. The second external electrode 900 extends from the portion of the insulating protective layer 500 adjacent to the second internal electrode 400, through the second end face 140 of the second internal electrode 400 and the carrier 100 to the second surface 120 of the carrier 100, and covers the second internal electrode 400 and the fourth internal electrode 700. As described above with reference to Figures 3 and 4, the first external electrode 800 and the second external electrode 900 can be a multilayer structure. The first external electrode 800 and the second external electrode 900 can be made by electroplating copper layers 810 and 910, nickel layers 820 and 920, and tin layers 830 and 930 in sequence.

[0059] Please refer to Figures 17 and 18, which are schematic diagrams illustrating the current C flow during resistance measurement of a low-resistance chip resistor 10 and a conventional low-resistance chip resistor 1000 according to one embodiment of this disclosure. Both the low-resistance chip resistors 10 and 1000 are soldered onto the solder pads SP of a circuit board. As shown in Figure 17, since the resistive layer 200 has a first groove 240 and a second groove 250, the current C is distributed above and below the first groove 240 and the second groove 250. The voltage measurement point V1 of the circuit board is adjacent to the first groove 240 and the second groove 250, thus reducing the current density at the voltage measurement point V1 and lowering the temperature coefficient of resistance of the low-resistance chip resistor 10. Furthermore, the third groove 260 and the fourth groove 270 of the resistive layer 200 ensure that the first external electrode 800 and the second external electrode 900 each have corresponding fifth groove 840 and sixth groove 940. The fifth groove 840 and the sixth groove 940 allow the low-resistance chip resistor 10 to be soldered onto the solder pad SP of the circuit board. Because the current C at the solder pad SP is shorter than at the non-grooved locations, it follows this shorter current path. Furthermore, the fifth groove 840 and the sixth groove 940 protrude towards the first groove 240 and the second groove 250, respectively. Therefore, the current density at the voltage measurement point V1 on the circuit board is reduced, further improving the accuracy of resistance measurement.

[0060] In contrast, as shown in Figure 18, the current C of the conventional low-resistance chip resistor 1000 flows substantially uniformly through it. Therefore, the current density at voltage measurement point V2 is significantly higher than the current density at voltage measurement point V1 in Figure 17. Consequently, the temperature coefficient of resistance of the low-resistance chip resistor 1000 cannot be reduced.

[0061] The following comparative examples and embodiments are used to illustrate the technical content and effects of this embodiment in more detail. However, they are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention.

[0062] Taking a 1mΩ low-resistance chip resistor with surface mount element 0603 as an example, the carrier of the low-resistance chip resistor in the comparative example and the embodiment is polyimide, the metal alloy material of the resistive layer is CuMnSn, and the thickness of the resistive layer is 0.15mm. Furthermore, in the low-resistance chip resistor of the comparative example, the width of the first electrode region and the second electrode region is 0.7mm and the length is 0.6mm, and the length of the resistance functional region is 0.3mm and the width is 0.6mm. In the low-resistance chip resistor of the embodiment, the width of the first electrode region and the second electrode region are 0.7 mm and the length is 0.6 mm, the width of the resistance functional region is 0.68 mm, the length of the first groove and the second groove is 75 μm, the distance between the first groove and the second groove is 0.15 mm, the width of the first groove and the second groove is 0.28 mm, the spacing between the second and third portions of the first groove and the second groove is 75 μm, the length of the second and third portions is 25 μm, the distance between the fourth portion of the third groove and the outer side of the first electrode region and the distance between the fourth portion of the fourth groove and the outer side of the first electrode region are 0.25 mm, and the length of the fourth portion is 0.15 mm. Both the comparative example and the embodiment of the low-resistance chip resistor achieve a resistance of 1 mΩ during the manufacturing process using physical drilling and grinding.

[0063] Please refer to Figure 19, which is a comparison chart of box-and-whisker plots BB1 and BB2 showing the resistance temperature coefficient data of a low-resistance chip resistor according to one embodiment of this disclosure and a conventional low-resistance chip resistor during resistance measurement. Resistance temperature coefficient measurements were performed on the low-resistance chip resistors of the comparative example and the embodiment from 25°C to 125°C. As shown in box-and-whisker plot BB2 of Figure 19, the average value (AVG) of the measured resistance temperature coefficient data for the low-resistance chip resistor of the comparative example is 175 ppm, and the standard deviation (SD) is 11 ppm. As shown in box-and-whisker plot BB1 of Figure 19, the average value (AVG) of the measured resistance temperature coefficient data for the low-resistance chip resistor of the embodiment is 127 ppm, and the standard deviation (SD) is 7 ppm. From the above measurement results, it can be seen that the resistance temperature coefficient of the low-resistance chip resistor of the embodiment can be reduced by approximately 48 ppm.

[0064] According to the above embodiments, the middle region of the resistance functional area of ​​the resistance layer of the disclosed low-resistance chip resistor is provided with a first groove and a second groove, which can concentrate the current path on both sides of the first groove and the second groove and in the middle of the resistance functional area. Therefore, the current density in the middle region between the first external electrode and the second external electrode can be significantly reduced, thereby reducing the thermal impact of the current on the measurement, and further reducing the resistance temperature coefficient of the low-resistance chip resistor and improving the accuracy of resistance measurement.

[0065] Furthermore, the resistive layer can be provided with a third and a fourth groove, allowing the first and second external electrodes to form corresponding fifth and sixth grooves. The fifth and sixth grooves allow the current to bypass the solder pads on the circuit board via shorter current paths outside the fifth and sixth grooves. This reduces the current density at voltage measurement points on the circuit board, further improving measurement accuracy. Moreover, the presence of the fifth and sixth grooves makes it easier for solder paste to fill the first and second external electrodes, thus improving the stability of low-resistance chip resistors soldered onto the circuit board.

[0066] Although this disclosure has been shown above by way of embodiments, it is not intended to limit this disclosure. Anyone with ordinary knowledge in this art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

[0067] 10: Low-resistance chip resistors 100: Carrier 110: First Surface 120: Second Surface 130: First end face 140: Second end face 200: Resistive layer 202: Area to be etched 204: Area to be etched 206: Area to be etched 208: Area to be etched 210: Resistance Function Area 220: First electrode region 230: Second electrode region 240: First Groove 242: Part One 244: Part Two 246: Part Three 250: Second groove 252: Part One 254: Part Two 256: Part Three 260: Third groove 262: Part Four 264: Part Five 270: Fourth Groove 272: Part Four 274: Part Five 280: Repair groove 300: First internal electrode 310: Groove 400: Second internal electrode 410: Groove 500: Insulation protective layer 510: Top surface 600: Third internal electrode 700: Fourth internal electrode 800: First external electrode 810: Copper layer 812: Top surface 820: Nickel layer 830: Tin layer 840: Fifth Groove 900: Second external electrode 910: Copper layer 912: Top surface 920: Nickel layer 930: Tin layer 940: Sixth Groove 1000: Low-resistance chip resistor a: Spacing AA: Section line AD: Adhesive layer b: Length BB: Section line BB1: Box and Whiskers Diagram BB2: Box and Whiskers Diagram BCL: Length BCW: Width C: Current c: Length CL: Length CW: Width D: Direction d: width g: distance h: distance L: Length M1: Cover Layer M2: Covering Layer M3: Cover Layer M4: Cover Layer RL: Length RL1: Length RL2: Distance RW: Width SP: solder pad V1: Voltage measurement point V2: Voltage measurement point W: Width

Claims

1. A low-resistance chip resistor, comprising: a carrier having a first surface and a second surface opposite to each other, and a first end face and a second end face opposite to each other; a resistive layer disposed on the first surface, wherein the resistive layer includes a resistance functional region, and a first electrode region and a second electrode region respectively located on opposite sides of the resistance functional region, the resistive layer having a first groove and a second groove located in an intermediate region of the resistance functional region and respectively adjacent to the first electrode region and the second electrode region; a first inner electrode disposed on the first electrode region; a second inner electrode disposed on the second electrode region; an insulating protective layer covering the resistance functional region, a portion of the first inner electrode, and a portion of the second inner electrode; a third inner electrode disposed on the second surface and opposite to the first inner electrode; and a fourth inner electrode disposed on the second surface and opposite to the second inner electrode. A first external electrode covers a portion of the insulating protective layer, the first internal electrode, the first end face, and the third internal electrode; and a second external electrode covers another portion of the insulating protective layer, the second internal electrode, the second end face, and the fourth internal electrode, and is spaced apart from the first external electrode, wherein each of the first groove and the second groove is an inverted U-shaped groove, and each of the first groove and the second groove includes a first portion, a second portion, and a third portion, and the second portion and the third portion of the first groove extend from the first portion of the first groove toward the first electrode region, and the second portion and the third portion of the second groove extend from the first portion of the second groove toward the second electrode region.

2. The low-resistance wafer resistor as claimed in claim 1 further includes an adhesive layer, wherein the adhesive layer is disposed between the first surface of the carrier and the resistive layer.

3. The low-resistance wafer resistor as claimed in claim 1, wherein the first groove and the second groove do not penetrate the resistive layer, and each of the first groove and the second groove has a depth of 50 μm to 150 μm.

4. The low-resistance chip resistor as claimed in claim 1, wherein the length and width of each of the first groove and the second groove are 1 / 5 to 1 / 3 of the length and 1 / 5 to 1 / 3 of the width of the resistance functional area, respectively, and in each of the first groove and the second groove, a spacing between the second portion and the third portion is 1 / 5 to 1 / 3 of the width of each of the first groove and the second groove, and a length of each of the second portion and the third portion is 1 / 5 to 1 / 3 of the length of each of the first groove and the second groove.

5. The low-resistance wafer resistor as claimed in claim 1, wherein the resistive layer further has a third groove and a fourth groove, the third groove extending from the first electrode region to the first groove, the fourth groove extending from the second electrode region to the second groove, the first external electrode having a fifth groove correspondingly located on the third groove, and the second external electrode having a sixth groove correspondingly located on the fourth groove.

6. The low-resistance wafer resistor as claimed in claim 5, wherein the third groove and the fourth groove do not penetrate the resistive layer, and each of the third groove and the fourth groove has a depth of 5 μm to 50 μm.

7. The low-resistance wafer resistor as claimed in claim 5, wherein each of the third groove and the fourth groove is an inverted T-shaped groove and includes a fourth portion and a fifth portion that engage with each other, the fourth portion of the third groove and the fourth portion of the fourth groove respectively extending longitudinally through the first electrode region and the second electrode region in a direction, and the fifth portion of the third groove is located between the second portion and the third portion of the first groove, and the fifth portion of the fourth groove is located between the second portion and the third portion of the second groove.

8. The low-resistance wafer resistor as claimed in claim 7, wherein the length of one of the fourth portions of the third groove is 50 μm to 250 μm, and the distance between it and one of the outer edges of the first electrode region is 1 / 4 to 1 / 2 of the length of one of the first electrode regions; and the length of one of the fourth portions of the fourth groove is 50 μm to 250 μm, and the distance between it and one of the outer edges of the second electrode region is 1 / 4 to 1 / 2 of the length of one of the second electrode regions.

9. The low-resistance chip resistor as claimed in claim 1, wherein the length and width of each of the third inner electrode and the fourth inner electrode are 25% to 35% of the length and 80% to 95% of the width of the low-resistance chip resistor, respectively.

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