Switching power converter circuit and control method thereof

Abstract

A switching power converter circuit includes a power stage circuit, configured to generate an output voltage based on an input voltage; a control circuit, configured to compare a ramp signal with a first reference voltage to generate a control signal for controlling the power stage circuit; and a ramp signal generator, coupled to the control circuit, configured to generate the ramp signal and determine a slope of the ramp signal according to a function; wherein the function includes multiple parameters, and the parameters include the input voltage and a second reference voltage but do not include the output voltage.

Description

Technical Field

[0001] The present invention relates to a switching power converter circuit and a control method thereof, and in particular to a switching power converter circuit and a control method thereof that can improve system stability and optimize load transient response performance. Prior Art

[0002] Switching power converters are widely used in various electronic devices to convert input voltage to the desired output voltage. Among the various control architectures, constant on-time (COT) control has attracted attention due to its simple structure and fast transient response.

[0003] Specifically, a switching power converter using a COT control topology directly compares the output voltage with a reference voltage to generate a control signal. This advantage lies in its extremely fast load transient response, as changes in the output voltage are directly and quickly reflected in the control signal. However, the COT control topology lacks a proper frequency compensation mechanism, resulting in poor closed-loop stability and compromised output voltage accuracy. This instability can cause system oscillations under certain operating conditions, impacting the reliability of the switching power converter. This issue is particularly critical in low-power applications, which typically require the power converter to deliver high efficiency and fast transient response while maintaining a stable and accurate output voltage.

[0004] Therefore, how to ensure that the system has good closed-loop stability and output voltage accuracy while maintaining fast load transient response has become one of the goals of this field. Summary of the Invention

[0005] Therefore, the present invention mainly provides a switching power converter circuit and a control method thereof to improve the shortcomings of the conventional technology.

[0006] An embodiment of the present invention discloses a switching power converter circuit comprising a power stage circuit for generating an output voltage based on an input voltage; a control circuit for comparing a ramp signal with a first reference voltage to generate a control signal for controlling the power stage circuit; and a ramp signal generator coupled to the control circuit for generating the ramp signal and determining the slope of the ramp signal based on a function; wherein the function comprises multiple parameters, and the parameters include the input voltage and a second reference voltage, but do not include the output voltage.

[0007] An embodiment of the present invention further discloses a control method for a switching power converter circuit, wherein the switching power converter circuit is configured to generate an output voltage based on an input voltage. The control method includes comparing a ramp signal with a first reference voltage to generate a control signal for controlling the switching power converter circuit; and generating the ramp signal based on a function; wherein the function includes multiple parameters, and the parameters include the input voltage and a second reference voltage, but do not include the output voltage. Simple diagram description

[0008] FIG1 is a functional block diagram of a switching power converter circuit according to an embodiment of the present invention. FIG2 is a schematic diagram of a switching power converter circuit according to an embodiment of the present invention. FIG3 is a schematic diagram of a ramp signal, a second reference voltage, and an output voltage according to an embodiment of the present invention. FIG4A is a schematic diagram of a calibration circuit according to an embodiment of the present invention. FIG. 4B is a schematic diagram illustrating how the calibration circuit of FIG. 4A adjusts the first transconductance parameter to change the output voltage. FIG5A is a schematic diagram of a calibration circuit according to an embodiment of the present invention. FIG. 5B is a schematic diagram illustrating how the calibration circuit of FIG. 5A adjusts the second transconductance parameter to change the output voltage. FIG6A is a schematic diagram of a calibration circuit according to an embodiment of the present invention. FIG6B is a schematic diagram showing how the calibration circuit in FIG6A adjusts the second reference voltage to change the output voltage. FIG7 is a schematic diagram of a control flow according to an embodiment of the present invention. FIG8 is a schematic diagram of a conventional switching power converter. Implementation Method

[0009] Please refer to Figure 1, which is a functional block diagram of a switching power converter circuit 10 according to an embodiment of the present invention. The switching power converter circuit 10 includes a power stage circuit 12, a control circuit 14, and a ramp signal generator 16. The power stage circuit 12 is controlled by a control signal CTRL and is configured to generate an output voltage VOUT based on an input voltage VIN. The power stage circuit 12 can be a buck, boost, or buck-boost power converter. The control circuit 14 compares a ramp signal VRMP with a first reference voltage VREF1 to generate a control signal CTRL for controlling the power stage circuit 12. The first reference voltage VREF1 can be designed to have a fixed voltage value that is independent of temperature to enhance system stability. The ramp signal generator 16 is coupled to the control circuit 14, and is used to generate the ramp signal VRMP and determine the slope (rising and falling slopes) of the ramp signal VRMP according to a function, wherein the function includes multiple parameters, and the parameters include the input voltage VIN and a second reference voltage VREF2, but do not include the output voltage VOUT.

[0010] In the switching power converter circuit 10, parasitic resistance inevitably exists in the transmission path of the output voltage VOUT. This resistance can cause unstable operation of the control circuit 14, resulting in a large error between the average value of the output voltage VOUT and its target value. To address this issue, the switching power converter circuit 10 employs a ramp signal generator 16 to generate a ramp signal VRMP, which enables the control circuit 14 to generate a control signal CTRL based on the ramp signal VRMP and a first reference voltage VREF1. The slope of the ramp signal VRMP generated by the ramp signal generator 16 is determined by a function that includes the input voltage VIN and the second reference voltage VREF2, but does not include the output voltage VOUT. This function can be expressed as f(VIN, VREF2). Because the parameter used by the ramp signal generator 16 to determine the slope of the ramp signal VRMP does not include the output voltage VOUT, noise from the output voltage VOUT can be prevented from affecting system performance through the feedback path, thereby ensuring system stability and further improving load transient response. Furthermore, the switching power converter circuit 10 does not require an error amplifier, thus avoiding the delay associated with using a resistor-capacitor compensation circuit and achieving a faster load transient response. In one embodiment, the switching power converter circuit 10 does not require an error amplifier in the circuitry associated with generating the ramp signal VRMP, which is disposed before the control circuit 14 (e.g., the ramp signal generator 16 or the circuitry used to control the ramp signal generator 16). In other words, the switching power converter circuit 10 does not require an error amplifier to generate the ramp signal VRMP.

[0011] It should be noted that the ramp signal generator 16 is used to generate the ramp signal VRMP and determines the slope of the ramp signal VRMP based on a function that does not include the output voltage VOUT. That is, the ramp signal generator 16 does not need to consider the output voltage VOUT when determining the slope of the ramp signal VRMP. However, depending on different system requirements or application areas, the ramp signal generator 16 may still use the output voltage VOUT for other purposes when generating the ramp signal VRMP, such as as a reference voltage or initial voltage for the ramp signal VRMP. This does not affect the characteristic of the present invention that the slope of the ramp signal VRMP is determined by the input voltage VIN and the second reference voltage VREF2 (rather than the output voltage VOUT). For example, in one embodiment, the switching power converter circuit 10 may further include a calibration circuit coupled to the power stage circuit 12 and the ramp signal generator 16. The calibration circuit is used to adjust at least one parameter of the function (used by the ramp signal generator 16 to determine the slope of the ramp signal VRMP) based on the output voltage VOUT and the second reference voltage VREF2, so that the output voltage VOUT approaches the target voltage. In other words, the calibration circuit can provide and adjust the parameters of the function used by the ramp signal generator 16 to ensure the accuracy of the output voltage VOUT.

[0012] In short, the slope of the ramp signal VRMP generated by the ramp signal generator 16 is unaffected by the output voltage VOUT and its noise, thereby ensuring system stability. Furthermore, as described above, the switching power converter circuit 10 does not require an error amplifier, thus avoiding the delay caused by the use of a compensation circuit and achieving a faster load transient response.

[0013] The power stage circuit 12, control circuit 14, and ramp signal generator 16 in FIG. 1 represent the basic architecture of the switching power converter circuit 10. Those skilled in the art should appropriately design or adjust the circuit architecture based on system requirements, application areas, and the like. For example, please refer to FIG. 2, which is a schematic diagram of a switching power converter circuit 20 according to an embodiment of the present invention. The switching power converter circuit 20 is derived from the switching power converter circuit 10 and can also be considered an implementation of the switching power converter circuit 10. Therefore, the same symbols are used to represent the same circuits or signals. Specifically, in the switching power converter circuit 20, the power stage circuit 12 includes a high-side switch HS, a low-side switch LS, an inductor L, and an output capacitor COUT. The high-side switch HS is coupled between the input voltage VIN and a switching node NSW, the low-side switch LS is coupled between the switching node NSW and a ground terminal GND, the inductor L is coupled between the switching node NSW and the output voltage VOUT, and the output capacitor COUT is coupled between the output voltage VOUT and ground terminal GND. The operating principles of the power stage circuit 12 are well known in the art. Briefly, the high-side switch HS and the low-side switch LS are used to switch the coupling path between the inductor L and the input voltage VIN or ground GND. Energy is accumulated or released through the inductor L, and the energy in the inductor L is converted into an appropriate output voltage VOUT, which is then supplied to the load circuit (e.g., the equivalent resistor RL shown in FIG2 ). Furthermore, in this architecture, it is necessary to ensure that only one of the high-side switch HS and the low-side switch LS is turned on at any given time to avoid a shoot-through phenomenon caused by simultaneous conduction of the high-side switch HS and the low-side switch LS, which could result in a power short circuit. Therefore, in FIG2 , the control signal CTRL is implemented by complementary switching signals S_D and S_DB, meaning that only one switching signal can be enabled at a time. Specifically, the control circuit 14 of the switching power converter circuit 20 is a pulse width modulation circuit comprising a comparison circuit 202 and an on-time generation circuit 204. The comparator circuit 202 receives a first reference voltage VREF1 at its positive input terminal (+) and a ramp signal VRMP at its negative input terminal (-) for comparing the ramp signal VRMP with the first reference voltage VREF1. The on-time generator circuit 204 generates complementary switching signals S_D and S_DB and controls the duty ratios of the switching signals S_D and S_DB based on the comparison result of the comparator circuit 202.That is, if the duty cycle of the switching signal S_D is D, then the duty cycle of the switching signal S_DB is (1-D). The comparison result of the comparison circuit 202 can be used to control the duty cycles D and (1-D) by changing the length of time that the switching signal S_D or S_DB is in the disabled state. This adjusts the off-time of the high-side switch HS and the low-side switch LS, thereby controlling the energy accumulated in the inductor L and generating an appropriate output voltage VOUT.

[0014] In the switching power converter circuit 20, the ramp signal generator 16 includes a resistor-capacitor circuit 206, a first current source 208, a first switch 210, a second current source 212, and a second switch 214. A node NRMP is formed between the negative input terminal of the comparison circuit 202 of the control circuit 14, the resistor-capacitor circuit 206, the first switch 210, and the second switch 214. The signal at the node NRMP is the ramp signal VRMP. The resistor-capacitor circuit 206 includes a resistor R and a capacitor C connected in parallel. It is coupled between the comparison circuit 202 of the control circuit 14 and the output voltage VOUT (i.e., coupled between the node NRMP and the output voltage VOUT), so that the output voltage VOUT can be directly coupled to the ramp signal VRMP, thereby accelerating the response speed of load transients. The first current source 208 is used to generate a first current I1, and the first current I1 is related to the input voltage VIN, the second reference voltage VREF2, and a first transconductance parameter gm1, i.e. One end of the first switch 210 is coupled to the first current source 208, and the other end is coupled to the node NRMP, for switching the conduction state of the two ends according to the switching signal S_D. The second current source 212 is used to generate a second current I2, and the second current I2 is related to the second reference voltage VREF2 and a second transconductance parameter gm2, that is, One end of the second switch 214 is coupled to the node NRMP, and the other end is coupled to the second current source 212, for switching the conduction status of the two ends according to the switching signal S_DB.

[0015] Furthermore, the resistor-capacitor circuit 206 can be considered an integrator, cooperating with the first current source 208 and the second current source 212 to generate the ramp signal VRMP. Specifically, when the switching signal S_D is enabled to turn on the first switch 210, and the switching signal S_DB is disabled to turn off the second switch 214, the first current I1 from the first current source 208 charges the capacitor C, causing the resistor-capacitor circuit 206 to generate the rising phase of the ramp signal VRMP. When the switching signal S_D is disabled to turn off the first switch 210, and the switching signal S_DB is enabled to turn on the second switch 214, the second current source 212 draws the second current I2 from the capacitor C, causing the resistor-capacitor circuit 206 to generate the falling phase of the ramp signal VRMP. Control circuit 14 compares ramp signal VRMP with first reference voltage VREF1 and, accordingly, controls the duty cycle of switching signals S_D and S_DB. This in turn controls the amplitude VSW of ramp signal VRMP (i.e., the difference between the voltage value of ramp signal VRMP when it transitions from a rising phase to a falling phase and the lowest voltage value of ramp signal VRMP). This is also related to the switching of the voltage at node NSW (inductor L), thereby regulating output voltage VOUT to maintain a target voltage. Ramp signal VRMP is superimposed on output voltage VOUT (via resistor-capacitor circuit 206). Therefore, the relative relationship between ramp signal VRMP, second reference voltage VREF2, and output voltage VOUT can be shown in FIG. 3 .

[0016] The above-described feedback control mechanism ensures that the output voltage VOUT is maintained at the target voltage. It should be noted that in the embodiment of FIG. 2 , the output voltage VOUT is coupled to the ramp signal VRMP via the resistor-capacitor circuit 206 . However, the output voltage VOUT only affects the level of the ramp signal VRMP and does not affect the slope of the ramp signal VRMP. Therefore, in one embodiment, the ground terminal GND can be connected to the resistor-capacitor circuit 206 instead of the output voltage VOUT (that is, the resistor-capacitor circuit 206 is coupled between the node NRMP and the ground terminal GND). In this case, the signal at the ground terminal GND is coupled to the ramp signal VRMP via the resistor-capacitor circuit 206 . Alternatively, in another embodiment, the resistor-capacitor circuit 206 may further include a switch for switching between the connection to the output voltage VOUT or the ground terminal GND, thereby selectively determining whether the signal at the output voltage VOUT or the ground terminal GND is coupled to the ramp signal VRMP. It should be noted that when the output voltage VOUT is coupled to the ramp signal VRMP, the load transient response is better. When the signal at the local GND is coupled to the ramp signal VRMP, the load transient response is worse, but it can still operate normally, depending on the designer's design choice.

[0017] In short, in the embodiment of FIG. 2 , the slope of the ramp signal VRMP is primarily influenced by the input voltage VIN and the second reference voltage VREF2. Furthermore, in this embodiment, the first transconductance parameter gm1 and the second transconductance parameter gm2 can also be used to adjust the slope of the ramp signal VRMP.

[0018] According to the above, the rising slope of the ramp signal VRMP is determined by the first current I1 ( ), and the falling slope of the ramp signal VRMP is determined by the second current I2 ( ). Therefore, the rising slope of the ramp signal VRMP is affected by the input voltage VIN and the second reference voltage VREF2, while the falling slope of the ramp signal VRMP is affected by the second reference voltage VREF2. The function f(VIN, VREF2) used to determine the slope (rising and falling slopes) of the ramp signal VRMP can be expressed as:

[0019] From the above, it can be seen that the slope of the ramp signal VRMP is determined by a function including the input voltage VIN and the second reference voltage VREF2 but not including the output voltage VOUT.

[0020] The factors affecting the slope of ramp signal VRMP can also be understood from the derivation of output voltage VOUT. Specifically, when switching power converter circuit 20 operates in continuous conduction mode (i.e., the current in inductor L does not drop to zero during each switching cycle), assuming output voltage VOUT is a fixed DC value, and assuming one switching cycle is T, the duty cycle of switching signal S_D is D, and the duty cycle of switching signal S_DB is (1-D), and the amplitude of ramp signal VRMP is VSW, then according to the principle of capacitor charge balance, we can know that:

[0021] (Formula 1) ;

[0022] During the period when the switching signal S_D is in the enabled state,

[0023] (Formula 2) ;

[0024] From formula 1, we can get

[0025] (Formula 3) ;

[0026] From formula 2, we can get

[0027] (Formula 4) ;

[0028] After sorting out formula 4, we can get:

[0029] (Formula 5) ;

[0030] From Equation 3 and Equation 5, we can get

[0031] (Equation 6) ;

[0032] Formula 6 can be rearranged to obtain

[0033] (Equation 7) .

[0034] Therefore, it can be seen from the above that the input voltage VIN, the second reference voltage VREF2, the first transconductance parameter gm1, and the second transconductance parameter gm2 affect the slope of the ramp signal VRMP (e.g., the rising and / or falling slopes of the ramp signal VRMP), but the output voltage VOUT does not affect the slope of the ramp signal VRMP. Furthermore, according to Equation 7, the output voltage VOUT can achieve the desired accuracy specification by adjusting the second reference voltage VREF2, the first transconductance parameter gm1, or the second transconductance parameter gm2.

[0035] In this case, the switching power converter circuit 20 further incorporates a calibration circuit 18, coupled to the power stage circuit 12 and the ramp signal generator 16. The calibration circuit 18 is configured to determine one or more of the first transconductance parameter gm1, the second transconductance parameter gm2, and the second reference voltage VREF2 based on the output voltage VOUT and the second reference voltage VREF2, thereby causing the output voltage VOUT to approach a target voltage to meet accuracy specifications. In other words, the calibration circuit 18 is configured to adjust at least one parameter in the function used to determine the slope of the ramp signal VRMP based on the output voltage VOUT and the second reference voltage VREF2, thereby causing the output voltage VOUT to approach the target voltage.

[0036] The implementation of calibration circuit 18 is not limited to a specific architecture, as long as it can determine one or more of the first transconductance parameter gm1, the second transconductance parameter gm2, and the second reference voltage VREF2 based on the output voltage VOUT and the second reference voltage VREF2. For example, please refer to FIG. 4A , which is a schematic diagram of a calibration circuit 40 according to an embodiment of the present invention. Calibration circuit 40 is used to implement calibration circuit 18 and is used to determine the first transconductance parameter gm1, which is related to the first current I1 generated by the first current source 208. Calibration circuit 40 includes a comparison circuit 402, an up / down counter 404, a digital-to-analog converter 406, and an operational transconductance amplifier (OTA) 408. Comparison circuit 402 is used to compare the output voltage VOUT with the second reference voltage VREF2 to generate a comparison result. Up / down counter 404 is coupled to comparison circuit 402 and is used to generate a digital count value based on the comparison result of comparison circuit 402. The digital-to-analog converter 406 is coupled to the up-down counter 404 and is configured to generate an analog signal IBIAS1 based on the digital count value of the up-down counter 404, which serves as a bias current for the operational transconductance amplifier 408. The operational transconductance amplifier 408 is coupled to the digital-to-analog converter 406 and the first current source 208 of the ramp signal generator 16 and is configured to generate an output current based on a voltage difference between the input voltage VIN and the second reference voltage VREF2. The output current is provided to the first current source 208 as the first current I1. Furthermore, the operational transconductance amplifier 408 determines a conversion ratio from the voltage difference to the output current based on the analog signal IBIAS1, which serves as a first transconductance parameter gm1.

[0037] During operation of the calibration circuit 40, the comparator circuit 402 first compares the output voltage VOUT with the second reference voltage VREF2. If the output voltage VOUT is greater than the second reference voltage VREF2, the comparator circuit 402 outputs a high-level comparison result. Conversely, if the output voltage VOUT is less than the second reference voltage VREF2, the comparator circuit 402 outputs a low-level comparison result. The up / down counter 404 counts based on this comparison result, incrementing the count value when the comparison result is a high level and decrementing the count value when the comparison result is a low level. The digital-to-analog converter 406 generates a corresponding analog signal IBIAS1 based on this digital count value. In this example, analog signal IBIAS1 is in the form of a current. Finally, the operational transconductance amplifier 408 determines the conversion ratio between the voltage difference between the input voltage VIN and the second reference voltage VREF2 and the output current based on the analog signal IBIAS1. Specifically, the main function of the operational transconductance amplifier 408 is to convert the input voltage difference into an output current. In this embodiment, the operational transconductance amplifier 408 receives an input voltage VIN and a second reference voltage VREF2 as differential inputs and converts this voltage difference into an output current. The conversion ratio (i.e., the first transconductance parameter gm1) is determined by the analog signal IBIAS1. When the analog signal IBIAS1 increases, the first transconductance parameter gm1 increases accordingly, resulting in a larger output current for the same input voltage difference. Conversely, when the analog signal IBIAS1 decreases, the first transconductance parameter gm1 decreases, resulting in a smaller output current for the same input voltage difference. By adjusting the first transconductance parameter gm1, the magnitude of the first current I1 generated by the first current source 208 is altered, ultimately affecting the characteristics of the ramp signal VRMP (e.g., the rising slope of the ramp signal VRMP), allowing the output voltage VOUT to gradually approach the target voltage. This feedback adjustment mechanism allows the output voltage VOUT to gradually approach the target voltage.

[0038] For example, please refer to FIG. 4B , which illustrates how the calibration circuit 40 of FIG. 4A adjusts the first transconductance parameter gm1 to change the output voltage VOUT. In FIG. 4B , curve 42 indicates that when the calibration circuit 40 adjusts the first transconductance parameter gm1 to 0.5 μV, the output voltage VOUT is 1.8149 volts. Curve 44 indicates that when the calibration circuit 40 adjusts the first transconductance parameter gm1 to 1 μV, the output voltage VOUT is 1.7699 volts. Curve 46 indicates that when the calibration circuit 40 adjusts the first transconductance parameter gm1 to 1.5 μV, the output voltage VOUT is 1.7272 volts. Therefore, FIG. 4B shows that by adjusting the first transconductance parameter gm1, the characteristics of the ramp signal VRMP can be influenced, allowing the output voltage VOUT to approach the target voltage.

[0039] Please refer to FIG. 5A , which is a schematic diagram of a calibration circuit 50 according to an embodiment of the present invention. Calibration circuit 50 is used to implement calibration circuit 18 and is configured to determine a second transconductance parameter gm2, which is related to the second current I2 generated by second current source 212. Calibration circuit 50 includes a comparator circuit 502, an up / down counter 504, a digital-to-analog converter 506, and an operational transconductance amplifier 508. Comparator circuit 502 is configured to compare output voltage VOUT with a second reference voltage VREF2 to generate a comparison result. Up / down counter 504 is coupled to comparator circuit 502 and is configured to generate a digital count value based on the comparison result of comparator circuit 502. Digital-to-analog converter 506 is coupled to up / down counter 504 and is configured to generate an analog signal IBIAS2 based on the digital count value of up / down counter 504, which serves as a bias current for operational transconductance amplifier 408. Operational transconductance amplifier 508 is coupled to digital-to-analog converter 506, second current source 212, and second switch 214. Operational transconductance amplifier 508 generates an output current based on a voltage difference between a second reference voltage VREF2 and a ground voltage, and provides the output current to first current source 212 as second current I2. Furthermore, operational transconductance amplifier 508 determines a conversion ratio from the voltage difference to the output current based on analog signal IBIAS2, which serves as a second transconductance parameter gm2.

[0040] The operation mode and operating principle of the calibration circuit 50 are similar to those of the calibration circuit 40, which can be appropriately deduced from the above description and will not be repeated here.

[0041] Therefore, the calibration circuit 50 can adjust the characteristics of the second current source 212 (e.g., the falling slope of the ramp signal VRMP), thereby adjusting the characteristics of the ramp signal VRMP so that the output voltage VOUT approaches the target voltage. For example, please refer to Figure 5B, which shows how the calibration circuit 50 in Figure 5A adjusts the second transconductance parameter gm2 to change the output voltage VOUT. In Figure 5B, curve 52 shows that when the calibration circuit 50 adjusts the second transconductance parameter gm2 to 1.5u, the output voltage VOUT is 1.8637 volts; curve 54 shows that when the calibration circuit 50 adjusts the second transconductance parameter gm2 to 1u, the output voltage VOUT is 1.8193 volts; and curve 56 shows that when the calibration circuit 50 adjusts the second transconductance parameter gm2 to 0.5u, the output voltage VOUT is 1.7739 volts. Therefore, as can be seen from FIG. 5B , by adjusting the second transconductance parameter gm2 , the characteristics of the ramp signal VRMP can be affected, so that the output voltage VOUT can approach the target voltage value.

[0042] Please refer to FIG. 6A , which is a schematic diagram of a calibration circuit 60 according to an embodiment of the present invention. In this embodiment, calibration circuit 60 is used to implement calibration circuit 18 and is configured to determine a second reference voltage VREF2, i.e., a reference voltage relative to first current source 208 and second current source 212. This second reference voltage VREF2 serves as a parameter for determining first current I1 generated by first current source 208 and second current I2 generated by second current source 212. Specifically, calibration circuit 60 is a feedback circuit comprising a comparator circuit 602, an up / down counter 604, and a digital-to-analog converter 606. Comparator circuit 602 is configured to compare output voltage VOUT with second reference voltage VREF2 to generate a comparison result. Up / down counter 604 is coupled to comparator circuit 602 and is configured to generate a digital count value based on the comparison result of comparator circuit 602. The digital-to-analog converter 606 is coupled to the up-down counter 604 for generating a second reference voltage VREF2 according to the digital count value of the up-down counter 604 and feeding the second reference voltage VREF2 back to the comparison circuit 602 .

[0043] During operation, the calibration circuit 60 forms a complete feedback loop. First, the comparator circuit 602 compares the output voltage VOUT with the second reference voltage VREF2. If the output voltage VOUT is greater than the second reference voltage VREF2, the comparator circuit 602 outputs a high-level comparison result. Conversely, if the output voltage VOUT is less than the second reference voltage VREF2, the comparator circuit 602 outputs a low-level comparison result. The up / down counter 604 adjusts its count value based on this comparison result. When the comparison result is a high level, the count value is incremented, indicating that the second reference voltage VREF2 needs to be increased; when the comparison result is a low level, the count value is decremented, indicating that the second reference voltage VREF2 needs to be decreased. The digital-to-analog converter 606 converts this digital count value into a new second reference voltage VREF2 and feeds it back to the comparator circuit 602, completing a new round of comparison. In this architecture, the digital-to-analog converter 606 may be a digital-to-analog converter based on a resistor network, such as a ladder network composed of single and double resistor values ​​or a voltage divider composed of a string of equal-value resistors, but is not limited thereto.

[0044] Because the second reference voltage VREF2 serves as the reference voltage for both the first current source 208 and the second current source 212, changes in its value simultaneously affect the magnitudes of both currents, thereby altering the characteristics of the ramp signal VRMP. Through this feedback adjustment mechanism, the system can adjust the value of the second reference voltage VREF2 so that the output voltage VOUT reaches the desired target voltage.

[0045] Therefore, the calibration circuit 60 can adjust the reference voltages of the first current source 208 and the second current source 212, thereby adjusting the characteristics of the ramp signal VRMP so that the output voltage VOUT approaches the target voltage. For example, please refer to FIG. 6B , which shows how the calibration circuit 60 in FIG. 6A adjusts the second reference voltage VREF2 to change the output voltage VOUT. In FIG. 6B , curve 62 shows that the calibration circuit 60 adjusts the second reference voltage VREF2 to 1.81 volts, resulting in an output voltage VOUT of 1.7976 volts. Curve 64 shows that the calibration circuit 60 adjusts the second reference voltage VREF2 to 1.8 volts, resulting in an output voltage VOUT of 1.7876 volts. Curve 66 shows that the calibration circuit 60 adjusts the second reference voltage VREF2 to 1.79 volts, resulting in an output voltage VOUT of 1.7777 volts. Therefore, as can be seen from FIG. 6B , by adjusting the second reference voltage VREF2 , the characteristics of the ramp signal VRMP can be affected, so that the output voltage VOUT can approach the target voltage value.

[0046] It should be noted that calibration circuits 40, 50, and 60 can all achieve the purpose of adjusting the characteristics of ramp signal VRMP so that the output voltage VOUT approaches the target voltage. In practical applications, one implementation can be selected based on circuit design requirements, or multiple implementations can be combined, or an appropriate circuit architecture can be selected. Furthermore, calibration circuits 40, 50, and 60 are used to implement calibration circuit 18, and their operation timing can be flexibly configured based on system requirements to further improve the performance and efficiency of switching power converter circuit 10 or 20. For example, in one embodiment, calibration circuits 18, 40, 50, and 60 can operate during system power-on. Through an initial calibration process, they dynamically adjust the first transconductance parameter gm1, the second transconductance parameter gm2, or the second reference voltage VREF2 to ensure that the output voltage VOUT quickly converges to the target voltage while compensating for manufacturing variations or environmental conditions. In addition, the calibration circuits 18, 40, 50, 60 may also be operated periodically after power-on, for example, triggered at regular intervals or when a significant change in the load or input voltage VIN is detected, to maintain the stability and accuracy of the output voltage VOUT through regular calibration.

[0047] According to one embodiment, the switching power converter circuit 10 or 20 may not include the calibration circuit 18. In this embodiment, each of the second reference voltage VREF2, the first transconductance parameter gm1, and the second transconductance parameter gm2 may be pre-set to a predetermined fixed value based on the target voltage of the output voltage VOUT. Alternatively, each of the second reference voltage VREF2, the first transconductance parameter gm1, and the second transconductance parameter gm2 may be pre-set to a predetermined range based on the target voltage of the output voltage VOUT. During operation of the switching power converter circuit 10 or 20, each of the second reference voltage VREF2, the first transconductance parameter gm1, and the second transconductance parameter gm2 may be set to a value within the corresponding predetermined range based on manufacturing variations or environmental conditions.

[0048] Overall, the switching power converter circuit 10 of Figure 1 or the switching power converter circuit 20 of Figure 2 generates a ramp signal VRMP via a ramp signal generator 16. The ramp signal VRMP's slope is determined by the input voltage VIN and the second reference voltage VREF2 and is unaffected by the output voltage VOUT, thereby improving system stability and optimizing load transient response performance. With this architecture, the switching power converter circuits 10 and 20 do not require an error amplifier, avoiding compensation circuit delays and achieving faster response speeds. Furthermore, the switching power converter circuits 10 and 20 can be appropriately configured with a calibration circuit to dynamically adjust the first transconductance parameter gm1, the second transconductance parameter gm2, or the second reference voltage VREF2 to ensure that the output voltage VOUT accurately approaches the target voltage, further enhancing the closed-loop stability of the system and the accuracy of the output voltage VOUT.

[0049] Furthermore, the switching power converter circuits 10 and 20 of the present invention and their calibration mechanisms are suitable for various applications, such as mobile devices, Internet of Things (IoT) devices, server power management, and industrial control systems. In particular, in low-power applications, the error amplifier-free design of the present invention avoids delays in the compensation circuit, improving system efficiency and response speed. Furthermore, dynamic adjustment of the calibration circuit ensures output voltage stability, meeting high reliability requirements.

[0050] The operation of the switching power converter circuits 10 and 20 can be summarized as a control process 70, as shown in FIG7. The control process 70 can be used with the switching power converter circuits 10 or 20 and includes the following steps:

[0051] Step 700: Start.

[0052] Step 702: Compare the ramp signal VRMP with the first reference voltage VREF1 to generate a control signal CTRL for controlling the switching power converter circuit 10.

[0053] Step 704: Generate a ramp signal VRMP according to a function; wherein the function includes multiple parameters, and the parameters include the input voltage VIN and the second reference voltage VREF2 and do not include the output voltage VOUT.

[0054] Step 706: End.

[0055] The detailed operation or derivative changes of the control process 70 can be referred to the above description and will not be repeated here.

[0056] Conventional switching power converters with a COT control architecture lack a proper frequency compensation mechanism, resulting in poor closed-loop stability and impacting reliability. For example, please refer to FIG8 , which is a schematic diagram of a conventional switching power converter 80. Switching power converter 80 employs a COT control architecture, in which the control circuit directly compares the output voltage with a reference voltage to generate a control signal. This architecture offers the advantage of extremely fast load transient response, as changes in the output voltage are directly and quickly reflected in the control signal. However, due to the lack of a proper frequency compensation mechanism, switching power converter 80 suffers from poor closed-loop stability and affects the accuracy of the output voltage. This instability can cause system oscillation under certain operating conditions, impacting the reliability of switching power converter 80. In contrast, the switching power converter circuit 10 or 20 of the present invention utilizes a ramp signal generator 16 to generate a ramp signal VRMP. Its slope is determined by the input voltage VIN and the second reference voltage VREF2 and is unaffected by the output voltage VOUT. This improves system stability and optimizes load transient response.

[0057] Conventional technology also provides an improved architecture that incorporates a ramp signal generation circuit based on a functional relationship between input and output voltages, based on the switching power converter 80, to increase the system's noise tolerance. This design improves closed-loop stability and enhances output voltage accuracy. However, this improvement comes at the cost of increased circuit complexity, requiring the addition of an error amplifier before the ramp signal generation circuit. This error amplifier, in turn, requires additional compensation circuitry to ensure system stability. These additional circuits inevitably increase signal transmission delay. When the output voltage experiences a load transient, the signal must be processed by the error amplifier and then transmitted through the ramp circuit before being reflected in the control signal, resulting in a slower load transient response. In contrast, the switching power converter circuits 10 and 20 of the present invention do not require an error amplifier, thus avoiding compensation circuit delay and achieving a faster response speed.

[0058] In summary, the switching power converter circuit of the present invention generates a ramp signal through a ramp signal generator, and its slope is not affected by the output voltage, thereby improving system stability and optimizing load transient response performance. Furthermore, the circuit does not require an error amplifier, thus avoiding compensation circuit delay and achieving a faster response speed. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0059] 10: Switching Power Converter Circuit 12: Power stage circuit 14: Control circuit 16: Ramp signal generator VIN: input voltage VOUT: output voltage CTRL: control signal VRMP: Ramp signal VREF1: first reference voltage VREF2: Second reference voltage 18: Calibration circuit 20: Switching Power Converter Circuit HS: High-side switch LS: Low-side switch L: Inductance COUT: output capacitor RL: equivalent resistance SD: Switching signal SDB: Switching signal NSW: Switch Node GND: ground terminal 202: Comparison Circuit 204: On-time generating circuit 206:Resistor-Capacitor Circuit 208: first current source 210: First switch 212: Second current source 214: Second switch gm1: first transduction parameters gm2: Second transduction parameter I1: first current I2: Second current R: resistance C: Capacitor 40: Calibration circuit 402: Comparison circuit 404: Up and down counter 406: Digital to Analog Converter 408: Operational Transconductance Amplifier 50: Calibration circuit 502: comparison circuit 504: Up and down counter 506: Digital to Analog Converter 508: Operational Transconductance Amplifier 60: Calibration circuit 602: Comparison circuit 604: Up and down counter 606: Digital to Analog Converter IBIAS1: analog signal IBIAS2: Analog signal VSW:Amplitude 70: Control Flow 700~706: Steps 80:Switching Power Converter

Claims

1. A switching power converter circuit, comprising: a power stage circuit for generating an output voltage based on an input voltage; a control circuit for comparing a ramp signal with a first reference voltage to generate a control signal for controlling the power stage circuit; and a ramp signal generator coupled to the control circuit at a node, for generating the ramp signal at the node and determining a slope of the ramp signal based on a function; wherein the function comprises a plurality of parameters, and the parameters include the input voltage and a second reference voltage and do not include the output voltage; wherein the ramp signal generator is configured to provide a first current to the node based on the input voltage, the second reference voltage, and a first transconductance parameter, and to provide a second current from the node to a ground based on the second reference voltage and a second transconductance parameter.

2. The switching power converter circuit of claim 1, wherein the ramp signal generator comprises: a resistor-capacitor circuit coupled between the node and the output voltage or a ground terminal; a first current source for generating the first current, the first current being related to the input voltage, the second reference voltage, and the first transconductance parameter; a first switch comprising a first terminal coupled to the first current source and a second terminal coupled to the node, for switching the first terminal to the second terminal in accordance with the control signal; a second current source for generating the second current, the second current being related to the second reference voltage and the second transconductance parameter; and a second switch comprising a first terminal coupled to the second current source and a second terminal coupled to the node, for switching the first terminal to the second terminal in accordance with the control signal; wherein the parameters of the function further include the first transconductance parameter and the second transconductance parameter.

3. The switching power converter circuit of claim 2, wherein the resistor-capacitor circuit further comprises a switch for switching the connection with the output voltage or the ground.

4. The switching power converter circuit as described in claim 2 further includes: a calibration circuit coupled to the power stage circuit and the ramp signal generator, for determining one or more of the first transconductance parameter, the second transconductance parameter and the second reference voltage based on the output voltage and the second reference voltage, so that the output voltage approaches a target voltage.

5. The switching power converter circuit of claim 1, wherein the switching power converter circuit generates the ramp signal without using an error amplifier.

6. The switching power converter circuit of claim 1, wherein the first reference voltage has a fixed voltage value that is not temperature-dependent.

7. A control method for a switching power converter circuit configured to generate an output voltage based on an input voltage, the control method comprising: comparing a ramp signal with a first reference voltage to generate a control signal for controlling the switching power converter circuit; and generating the ramp signal at a node based on a function; wherein the function comprises a plurality of parameters, and the parameters include the input voltage and a second reference voltage and do not include the output voltage; wherein generating the ramp signal at the node based on the function comprises providing a first current to the node based on the input voltage, the second reference voltage, and a first transconductance parameter, and providing a second current from the node to a ground based on the second reference voltage and a second transconductance parameter.

8. The control method of claim 7, wherein the step of generating the ramp signal at the node according to the function further comprises: controlling the charging and discharging of a resistor-capacitor circuit by the first current and the second current through the node according to the control signal to generate the ramp signal; wherein the parameters of the function further include the first transconductance parameter and the second transconductance parameter.

9. The control method of claim 8, further comprising: determining one or more of the first transconductance parameter, the second transconductance parameter, and the second reference voltage according to the output voltage and the second reference voltage, so that the output voltage approaches a target voltage.

10. The control method of claim 8, further comprising: switching the connection between the resistor-capacitor circuit and the output voltage or a ground terminal.

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