Clock generation circuit and semiconductor components

Abstract

A clock generation circuit that reduces frequency of a clock signal when a power supply voltage increases is provided. The clock generation circuit of the present invention includes a reference current setting unit, a bias voltage generation unit, and a ring oscillator. The bias voltage generation unit generates a PBIAS voltage applied to gates of PMOS transistors and an NBIAS voltage applied to gates of NMOS transistors in the ring oscillator. In response to the power supply voltage reaching a target voltage, the bias voltage generation unit increases the PBIAS voltage, thereby reducing a current supplied by the PMOS transistors and lowering frequency of the clock signal.

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