Level shift circuit and level shifter

Abstract

In order to enable generating an output logic signal having a duty cycle substantially equal to a duty cycle of an input logic signal, provided is a level shift circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a clamp circuit for limiting voltages of a first node and a second node within a range from a third voltage to a fourth voltage, and a waveform shaping circuit for providing an output logic signal based on level transitions of an input first logic signal and an input second logic signal in the same direction.

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