Voltage compensation circuit and phase lock loop

Abstract

The present application discloses a voltage compensation circuit and a phase lock loop. The voltage compensation circuit is configured to compensate a voltage of a node. The voltage compensation circuit includes a metal-oxide-semiconductor (MOS) capacitor, and a current mirror unit. The MOS capacitor has a first terminal coupled to a system voltage, and a second terminal. The current mirror unit is coupled to the node, and the current mirror unit includes a first branch unit and a second branch unit. The first branch unit generates a first current according to a voltage of the second terminal of the MOS capacitor, and the second branch unit generates a second current that is related to the first current by a scaling factor so as to adjust the voltage of the node.

Description

Technical Field

[0001] This disclosure relates to a voltage compensation circuit, and more particularly to a voltage compensation circuit for a phase-locked loop. Prior Technology

[0002] Phase-locked loops (PLLs) are widely used in communication, radar, and timing systems to generate precise and stable signals. PLLs track the frequency and phase of the output and input signals through a feedback mechanism, thus synchronizing the frequencies and phases of the two signals.

[0003] Generally, a phase-locked loop (PLL) includes a phase frequency detector (PFD), a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider. The frequency divider divides the PLL's output signal to generate a feedback signal, while the phase frequency detector generates a control signal based on the phase and frequency differences between the feedback signal and the reference signal, thereby adjusting the control voltage generated by the charge pump. In this way, the VCO can adjust the frequency of its output signal according to the magnitude of the control voltage generated by the charge pump. Furthermore, to prevent noise from the control voltage from causing instability in the VCO's output, the PLL also uses a low-pass filter to remove high-frequency components and interference signals from the control voltage.

[0004] In existing technologies, the capacitors in low-pass filters are metal-oxide-semiconductor (MOS) capacitors, typically fabricated using high-voltage processes to reduce leakage. However, MOS capacitors fabricated using high-voltage processes have a large area, potentially occupying up to two-thirds of the total area of ​​the phase-locked loop (PLL). If a smaller, non-high-voltage process, such as a core device process, is used to fabricate the MOS capacitor, leakage problems may arise. Therefore, reducing the required circuit area of ​​the PLL while maintaining its stability has become a pressing issue in this field. Summary of the Invention

[0005] One embodiment of this disclosure provides a voltage compensation circuit for compensating voltage at a node. The voltage compensation circuit includes a first metal-oxide-semiconductor (MOS) capacitor and a current mirror. The first MOS capacitor has a first terminal and a second terminal, the first terminal of which is coupled to the system voltage. The current mirror is coupled to the node and includes a first branch unit and a second branch unit. The first branch unit generates a first current based on the voltage at the second terminal of the first MOS capacitor, and the second branch unit generates a second current that is a multiple of the first current to adjust the node voltage.

[0006] Another embodiment disclosed herein provides a phase-locked loop (PLL). The PLL includes the aforementioned voltage compensation circuit, a phase-frequency detector, a charge pump, a voltage-controlled oscillator (VCO), a frequency divider, and a low-pass filter. The phase-frequency detector generates at least one control signal based on the phase and frequency difference between a feedback signal and a reference signal. The charge pump generates a control voltage based on the control signal and outputs the control voltage through a node. The VCO generates an output signal based on the control voltage. The frequency divider divides the output signal to generate a feedback signal. The low-pass filter performs low-pass filtering on the control voltage. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of a phase-locked loop according to a comparative embodiment of the present disclosure.

[0008] Figure 2 is a waveform diagram of the control voltage of a comparative embodiment disclosed herein.

[0009] Figure 3 is a waveform diagram of the control voltage of a comparative embodiment disclosed herein.

[0010] Figure 4 is a schematic diagram of a phase-locked loop according to an embodiment of this disclosure.

[0011] Figure 5 is a schematic diagram of the voltage compensation circuit in Figure 4.

[0012] Figure 6 is the waveform diagram of the control voltage in Figure 4.

[0013] Figure 7 is a schematic diagram of a voltage compensation circuit according to another embodiment of this disclosure.

[0014] Figure 8 is the waveform diagram of the control voltage in Figure 7.

[0015] Figure 9 is a schematic diagram of a voltage compensation circuit according to another embodiment of this disclosure.

[0016] Figure 10 is a schematic diagram of a voltage compensation circuit according to another embodiment of this disclosure. Implementation

[0017] Figure 1 is a schematic diagram of a phase-locked loop 100 according to a comparative embodiment of the present disclosure. The phase-locked loop 100 includes a phase-frequency detector 110, a charge pump 120, a voltage-controlled oscillator 130, a frequency divider 140, and a low-pass filter 150. The phase-frequency detector 110 generates at least one control signal, such as a control signal SIG UP and a control signal SIG DN, based on the phase and frequency difference between the feedback signal SIG FB and the reference signal SIG REF. The charge pump 120 generates a control voltage V CTRL based on the control signals SIG UP and SIG DN generated by the phase-frequency detector 110, and outputs the control voltage V CTRL through node N1. The voltage-controlled oscillator 130 generates an output signal SIG OUT based on the control voltage V CTRL, and the frequency divider 140 divides the output signal SIG OUT by a specific value to generate the feedback signal SIG FB.

[0018] For example, when the frequency of the reference signal SIG REF is lower than the frequency of the feedback signal SIG FB, the phase frequency detector 110 can output a control signal SIG UP to increase the control voltage V CTRL, causing the voltage-controlled oscillator 130 to increase its oscillation frequency, thereby outputting a higher frequency output signal SIG OUT. Conversely, when the frequency of the reference signal SIG REF is higher than the frequency of the feedback signal SIG FB, the phase frequency detector 110 can output a control signal SIG DN to decrease the control voltage V CTRL, causing the voltage-controlled oscillator 130 to decrease its oscillation frequency, thereby outputting a lower frequency output signal SIG OUT. Through this feedback mechanism, the phase-locked loop 100 can generate a precise and stable signal.

[0019] Furthermore, to prevent high-frequency noise in the control voltage VCTRL from causing instability in the oscillation frequency of the voltage-controlled oscillator 130, the phase-locked loop 100 can perform low-pass filtering on the control voltage VCTRL through a low-pass filter 150, thereby eliminating high-frequency noise. As shown in Figure 1, the low-pass filter 150 may include metal-oxide-semiconductor (MOS) capacitors 152 and 154 and a resistor 156. MOS capacitor 152 has a first terminal and a second terminal, and the first terminal of MOS capacitor 152 is coupled to the system voltage, such as the power supply voltage VDD. Resistor 156 has a first terminal and a second terminal, the first terminal of resistor 156 is coupled to the second terminal of MOS capacitor 152, and the second terminal of resistor 156 is coupled to node N1. MOS capacitor 154 has a first terminal and a second terminal, the first terminal of MOS capacitor 154 is coupled to the system voltage, such as the power supply voltage VDD, and the second terminal of MOS capacitor 154 is coupled to node N1.

[0020] In some embodiments, MOS capacitors 152 and 154 can be fabricated using a process for manufacturing low-voltage components. In this case, the low-pass filter 150 can have a smaller circuit area compared to MOS capacitors fabricated using a high-voltage component process. However, MOS capacitors fabricated using a low-voltage component process are generally more prone to leakage, which may also cause a shift in the control voltage VCTRL. Figure 2 is a waveform diagram of the control voltage VCTRL in a comparative embodiment of this disclosure. In time period T1 of Figure 2, due to leakage from capacitors 152 and 154, the control voltage VCTRL is pulled up to near the power supply voltage VDD, causing the frequency of the output signal SIG OUT generated by the voltage-controlled oscillator 130 to be too high. In this case, through the feedback mechanism of the phase-locked loop 100, the phase frequency detector 110 outputs a control signal SIG DN to pull down the control voltage VCTRL generated by the charge pump 120. Therefore, in time period T2, the control voltage VCTRL will return to a level close to its original value. As shown in Figure 2, the leakage current generated by capacitors 152 and 154 will cause drastic fluctuations in the control voltage VCTRL, resulting in a decrease in the stability of the phase-locked loop 100.

[0021] Furthermore, in some embodiments, the first terminals of MOS capacitors 152 and 154 may be coupled to a reference voltage VSS (e.g., ground) in the system voltage instead of the power supply voltage VDD. In this case, leakage current in MOS capacitors 152 and 154 may cause the control voltage VCTRL to shift towards the reference voltage VSS. Figure 3 is a waveform diagram of the control voltage VCTRL in a comparative embodiment of this disclosure. In time period T1' of Figure 4, due to leakage current in capacitors 152 and 154, the control voltage VCTRL is pulled down to near the reference voltage VSS, resulting in a lower frequency of the output signal SIG OUT generated by the voltage-controlled oscillator 130. In this case, through the feedback mechanism of the phase-locked loop 100, the phase frequency detector 110 outputs a control signal SIG UP to pull up the control voltage VCTRL generated by the charge pump 120, so in time period T2', the control voltage VCTRL can return to a level close to its original value. As shown in Figure 3, the leakage current generated by capacitors 152 and 154 will cause drastic fluctuations in the control voltage VCTRL, resulting in a decrease in the stability of the phase-locked loop 100.

[0022] Figure 4 is a schematic diagram of a phase-locked loop 200 according to an embodiment of this disclosure. In this embodiment, the difference between phase-locked loop 200 and phase-locked loop 100 is that phase-locked loop 200 may additionally include a voltage compensation circuit 260. Since the voltage compensation circuit 260 can compensate for the influence of leakage current from capacitors 152 and 154 on the voltage at node N1 (which is the control voltage VCTRL in this embodiment), the voltage change of the control voltage VCTRL can be made more gradual, thereby making the output signal SIG OUT of phase-locked loop 200 more stable.

[0023] Figure 5 is a schematic diagram of a voltage compensation circuit 260 according to an embodiment of this disclosure. As shown in Figure 5, the voltage compensation circuit 260 may include a MOS capacitor C1A and a current mirror 262. The MOS capacitor C1A has a first terminal and a second terminal, and the first terminal of the MOS capacitor C1A is coupled to the system voltage, such as the power supply voltage VDD. The current mirror 262 is coupled to node N1, and the current mirror 262 may include a first branch unit 2621 and a second branch unit 2622. The first branch unit 2621 can generate a first current I1 based on the voltage of the second terminal of the MOS capacitor C1A, while the second branch unit 2622 can generate a second current I2 that is a multiple of the first current I1 to adjust the voltage of node N1.

[0024] In this embodiment, the MOS capacitor C1A and the MOS capacitor 152 in the low-pass filter 150 coupled to node N1 can be the same type of capacitor, thus simulating leakage of the MOS capacitor 152. In some embodiments, both the MOS capacitor 152 and the MOS capacitor C1A can be implemented as P-type transistors, and the first terminal of the MOS capacitor 152 and the first terminal of the MOS capacitor C1A can correspond to the source / drain of the P-type transistor, while the second terminal of the MOS capacitor 152 and the second terminal of the MOS capacitor C1A can correspond to the gate of the P-type transistor; however, this disclosure is not limited thereto.

[0025] When MOS capacitor 152 leaks current and pulls up the control voltage VCTRL, MOS capacitor C1A may also leak current and pull up the voltage at its second terminal. At this time, the first branch unit 2621 will enhance the first current I1, and the second branch unit 2622 will also enhance the second current I2 drawn from node N1, thereby pulling down the voltage of node N1 (which is the control voltage VCTRL in this embodiment), achieving the effect of voltage compensation. Figure 6 is a waveform diagram of the control voltage VCTRL according to an embodiment of this disclosure. In Figure 6, the solid line L1 represents the waveform of the control voltage VCTRL when the voltage compensation circuit 260 is used, and the dashed line L2 represents the waveform of the control voltage VCTRL when the voltage compensation circuit is not used (i.e., equivalent to the waveform shown in Figure 2). As shown in Figure 6, since the voltage compensation circuit 260 can increase the current drawn from node N1 when leakage occurs in the MOS capacitors 152 and 154 in the low-pass filter 150, it can reduce the fluctuation of the control voltage VCTRL, thereby increasing the stability of the phase-locked loop 200.

[0026] In Figure 5, the first branch unit 2621 may include an N-type transistor N1A. The N-type transistor N1A has a first terminal and a second terminal. The first terminal of the N-type transistor N1A is coupled to a reference voltage VSS (which may be, for example, ground) that is less than the power supply voltage VDD. The second terminal of the N-type transistor N1A is coupled to the second terminal of the MOS capacitor C1A, and the control terminal of the N-type transistor N1A is coupled to the second terminal of the N-type transistor N1A. The second branch unit 2622 may include an N-type transistor N2A. The N-type transistor N2A has a first terminal and a second terminal. The first terminal of the N-type transistor N2A is coupled to the reference voltage VSS. The second terminal of the N-type transistor N2A is coupled to node N1, and the control terminal of the N-type transistor N2A is coupled to the control terminal of the N-type transistor N1A. In the description of this disclosure, the first terminal, second terminal, and control terminal of the transistor may, for example, be the source, drain, and gate of the transistor, respectively. However, this disclosure is not limited thereto.

[0027] Furthermore, in some embodiments, the area of ​​MOS capacitor 152 can be N times the area of ​​MOS capacitor C1A, and by adjusting the aspect ratio of N-type transistors N1A and N2A, the second current I2 can be M times the first current I1 (for example, the aspect ratio of N-type transistor N2A can be M times the aspect ratio of N-type transistor N1A), where N and M are greater than 1. In this way, the leakage current of MOS capacitor 152 can be simulated using a smaller area MOS capacitor C1A. In some embodiments, N and M can be equal; however, this disclosure is not limited to this.

[0028] Furthermore, in the embodiment of Figure 5, the low-pass filter 150 is coupled to the power supply voltage VDD through MOS capacitors 152 and 154; however, this disclosure is not limited thereto. In some embodiments, the low-pass filter 150 may also be coupled to the reference voltage VSS through a MOS capacitor.

[0029] Figure 7 is a schematic diagram of a voltage compensation circuit 360 according to an embodiment of this disclosure. In this embodiment, the charge pump 120 can output a control voltage VCTRL through node N1. The main difference between Figure 7 and Figure 5 is that the low-pass filter 150' in Figure 7 can be coupled to a reference voltage VSS through MOS capacitors 152' and 154', and the voltage compensation circuit 360 in Figure 7 can replace the voltage compensation circuit 260 in Figure 5. The voltage compensation circuit 360 may include a MOS capacitor C1B and a current mirror 362. The MOS capacitor C1B has a first terminal and a second terminal, and the first terminal of the MOS capacitor C1B is coupled to the system voltage, such as the reference voltage VSS. The current mirror 362 is coupled to node N1, and the current mirror 362 may include a first branch unit 3621 and a second branch unit 3622. The first branch unit 3621 can generate a first current I1 based on the voltage at the second terminal of the MOS capacitor C1B, while the second branch unit 3622 can generate a second current I2 that is a multiple of the first current I1 to adjust the voltage of node N1.

[0030] Specifically, when leakage occurs in MOS capacitor C1B, the voltage at the second terminal of the MOS capacitor is pulled down. At this time, the first branch unit 3621 will correspondingly increase the first current I1, and the second branch unit 3622 will correspondingly increase the second current I2 flowing into node N1, thereby pulling up the voltage of node N1 (which is the control voltage VCTRL in this embodiment). Figure 8 is a waveform diagram of the control voltage VCTRL according to an embodiment of this disclosure. In Figure 8, the solid line L1' represents the waveform of the control voltage VCTRL when the voltage compensation circuit 360 is used, and the dashed line L2' represents the waveform of the control voltage VCTRL when the voltage compensation circuit is not used (i.e., equivalent to the waveform shown in Figure 3). As shown in Figure 8, since the voltage compensation circuit 360 can increase the current flowing into node N1 when leakage occurs in MOS capacitors 152' and 154' in the low-pass filter 150', it can reduce the fluctuation amplitude of the control voltage VCTRL, thereby increasing the stability of the phase-locked loop 200.

[0031] In this embodiment, the first branch unit 3621 may include a P-type transistor P1B. The P-type transistor P1B has a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor P1B is coupled to the power supply voltage VDD, the second terminal of the P-type transistor P1B is coupled to the second terminal of the MOS capacitor C1B, and the control terminal of the P-type transistor P1B is coupled to the second terminal of the P-type transistor P1B. The second branch unit 3622 may include a P-type transistor P2B. The P-type transistor P2B has a first terminal and a second terminal. The first terminal of the P-type transistor P2B is coupled to the power supply voltage VDD, the second terminal of the P-type transistor P2B is coupled to node N1, and the control terminal of the P-type transistor P2B is coupled to the control terminal of the P-type transistor P1B.

[0032] Furthermore, in some embodiments, both MOS capacitor 152' and MOS capacitor C1B may be capacitors implemented with N-type transistors, and the first terminal of MOS capacitor 152' and the first terminal of MOS capacitor C1B may correspond to the source / drain of the N-type transistor, while the second terminal of MOS capacitor 152' and the second terminal of MOS capacitor C1B may correspond to the gate of the N-type transistor. However, this disclosure is not limited thereto.

[0033] Figure 9 is a schematic diagram of a voltage compensation circuit 460 according to another embodiment of this disclosure. The main difference between Figure 9 and Figure 5 is that the voltage compensation circuit 460 in Figure 9 can replace the voltage compensation circuit 260 in Figure 5. The voltage compensation circuit 460 may include a current mirror 262, a MOS capacitor C1A, and a control unit 464.

[0034] Specifically, the control unit 464 may include a P-type transistor P3C, an N-type transistor N3C, a resistor R1C, and a current source CS1. The P-type transistor P3C has a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor P3C is coupled to the second terminal of the MOS capacitor C1A, and the second terminal of the P-type transistor P3C is coupled to the current mirror 262. In this embodiment, the second terminal of the P-type transistor P3C may be coupled to the second terminal of the N-type transistor N1A in the current mirror 262. The N-type transistor N3C has a first terminal, a second terminal, and a control terminal. The first terminal of the N-type transistor N3C is coupled to the control terminal of the P-type transistor P3C, and the control terminal of the N-type transistor N3C is coupled to node N1. The resistor R1C has a first terminal and a second terminal. The first terminal of the resistor R1C is coupled to the power supply voltage VDD, and the second terminal of the resistor R1C is coupled to the second terminal of the N-type transistor N3C. The current source CS1 is coupled to the first terminal of the N-type transistor N3C.

[0035] In this embodiment, when the MOS capacitor 152 leaks current, the control voltage VCTRL will be pulled up. At this time, the N-type transistor N3C and the P-type transistor P3C will be turned on, thereby activating the current mirror 262, causing the first branch unit 2621 to generate the first current I1, and causing the second branch unit 2622 to draw the second current I2 from node N1, thereby pulling the control voltage VCTRL down to its original level.

[0036] In this embodiment, the control unit 464 can make the voltage VC at the second terminal of the MOS capacitor C1A approach the voltage of node N1 (which is the control voltage VCTRL in this embodiment), thus helping the voltage compensation circuit 460 to more accurately compensate for the leakage current generated by the MOS capacitors 152 and 154. In addition, the control unit 464 also helps to eliminate the second-order effect caused by the mismatch between the N-type transistors N1A and N2A in the current mirror 262, thus also helping to improve the accuracy of compensation.

[0037] Figure 10 is a schematic diagram of a voltage compensation circuit 560 according to another embodiment of this disclosure. The main difference between Figure 10 and Figure 7 is that the voltage compensation circuit 560 of Figure 10 can replace the voltage compensation circuit 360 of Figure 7. The voltage compensation circuit 560 may include a current mirror 362, a MOS capacitor C1B, and a control unit 564.

[0038] Specifically, the control unit 564 may include a P-type transistor P3D, an N-type transistor N3D, a resistor R1D, and a current source CS2. The N-type transistor N3D has a first terminal, a second terminal, and a control terminal. The first terminal of the N-type transistor N3D is coupled to the second terminal of the MOS capacitor C1B, and the second terminal of the N-type transistor N3D is coupled to the current mirror 362. In this embodiment, the second terminal of the N-type transistor N3D may be coupled to the second terminal of the P-type transistor P1B in the current mirror 262. The P-type transistor P3D has a first terminal, a second terminal, and a control terminal. The second terminal of the P-type transistor P3D is coupled to the control terminal of the N-type transistor N3D, and the control terminal of the P-type transistor P3D is coupled to node N1. The resistor R1D has a first terminal and a second terminal. The first terminal of the resistor R1D is coupled to the reference voltage VSS, and the second terminal of the resistor R1D is coupled to the second terminal of the P-type transistor P3D. The current source CS2 is coupled to the first terminal of the P-type transistor P3D.

[0039] In this embodiment, when the MOS capacitor 152' leaks current, the control voltage VCTRL will be pulled down. At this time, the P-type transistor P3D and the N-type transistor N3D will be turned on, thereby activating the current mirror 362, causing the first branch unit 3621 to generate the first current I1, and causing the second branch unit 3622 to generate the second current I2, which flows into node N1, thereby pulling the control voltage VCTRL up to its original level.

[0040] In the foregoing embodiments, voltage compensation circuits 260, 360, 460, and 560 can be applied to phase-locked loops; however, this disclosure is not limited thereto. In some embodiments, voltage compensation circuits 260, 360, 460, and 560 can also be applied to other circuits containing MOS capacitors or low-pass filters, and can similarly be used to compensate the voltage at nodes coupled to MOS capacitors or low-pass filters.

[0041] In summary, the voltage compensation circuit and phase-locked loop provided in the embodiments disclosed herein can compensate for voltage changes caused by leakage current in the MOS capacitor. Therefore, even if a low-voltage component process is used to fabricate the MOS capacitor in the low-pass filter to reduce the circuit area, the circuit output can still remain stable. Furthermore, the voltage compensation circuit provided in the embodiments disclosed herein requires only a small number of electronic components to achieve the voltage compensation effect, thus avoiding excessive increase in the overall circuit complexity and making it widely applicable in various circuits.

[0042] 100, 200: Phase-locked loop 110: Phase and frequency detector 120: Charge Pump 130: Voltage-controlled oscillator 140: Frequency divider 150,150': Low-pass filter 152, 154, 152', 154': MOS capacitors 156, 156', R1C, R1D: Resistors 260, 360, 460, 560: Voltage compensation circuit 262,362: Current mirror 464, 564: Control Unit 2621, 2622, 3621, 3622: Branch units C1A, C1B: MOS capacitors CS1, CS2: Current sources I1, I2: Current L1, L1': Solid lines L2, L2': Dashed lines N1: Node N1A, N2A, N3C, N3D: N-type transistors P1B, P2B, P3C, P3D: N-type transistors SIG FB: Feedback Signal SIG OUT: Output signal SIG REF: Reference Signal SIG UP, SIG DN: Control signals T1, T2, T1', T2': Time period VC: Voltage V CTRL: Control voltage VDD: Power supply voltage VSS: Reference voltage

Claims

1. A voltage compensation circuit for compensating voltage at a node, comprising: a first metal-oxide-semiconductor (MOS) capacitor having a first terminal coupled to a system voltage and a second terminal; and a current mirror coupled to the node, the current mirror comprising: a first branch unit for generating a first current based on the voltage at the second terminal of the first MOS capacitor; and a second branch unit for generating a second current having a multiple relationship with the first current to adjust the voltage of the node; wherein the node is coupled to the system voltage through a filter including a second MOS capacitor, and the first MOS capacitor and the second MOS capacitor are capacitors of the same type.

2. The voltage compensation circuit as claimed in claim 1, wherein the system voltage is a power supply voltage, and when the voltage at the second terminal of the first MOS capacitor is pulled up, the first branch unit amplifies the first current, and the second branch unit amplifies the second current drawn from the node, thereby pulling down the voltage of the node.

3. The voltage compensation circuit as described in claim 2, wherein: The first branch unit includes a first N-type transistor having a first terminal coupled to a reference voltage less than the power supply voltage, a second terminal coupled to the second terminal of the first MOS capacitor, and a control terminal coupled to the second terminal of the first N-type transistor; and the second branch unit includes a second N-type transistor having a first terminal coupled to the reference voltage, a second terminal coupled to the node, and a control terminal coupled to the control terminal of the first N-type transistor.

4. The voltage compensation circuit as claimed in claim 1, wherein the system voltage is a reference voltage, and when the voltage at the second terminal of the first MOS capacitor is pulled down, the first branch unit amplifies the first current, and the second branch unit amplifies the second current flowing into the node, thereby pulling up the voltage of the node.

5. The voltage compensation circuit as described in claim 4, wherein: The first branch unit includes a first P-type transistor having a first terminal coupled to a power supply voltage greater than the reference voltage, a second terminal coupled to the second terminal of the first MOS capacitor, and a control terminal coupled to the second terminal of the first P-type transistor; and the second branch unit includes a second P-type transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the node, and a control terminal coupled to the control terminal of the first P-type transistor.

6. The voltage compensation circuit as described in claim 1 further includes a control unit for making the voltage at the second terminal of the first MOS capacitor approach the voltage of the node.

7. The voltage compensation circuit as claimed in claim 6, wherein the system voltage is a power supply voltage, and the regulating unit comprises: a third P-type transistor having a first terminal coupled to the second terminal of the first MOS capacitor, a second terminal coupled to the current mirror, and a control terminal; a third N-type transistor having a first terminal coupled to the control terminal of the third P-type transistor, a second terminal, and a control terminal coupled to the node; a resistor having a first terminal coupled to the power supply voltage and a second terminal coupled to the second terminal of the third N-type transistor; and a current source coupled to the first terminal of the third N-type transistor.

8. The voltage compensation circuit as described in claim 7, wherein: The first branch unit includes a first N-type transistor having a first terminal coupled to a reference voltage less than the power supply voltage, a second terminal coupled to the second terminal of the third P-type transistor, and a control terminal coupled to the second terminal of the first N-type transistor; and the second branch unit includes a second N-type transistor having a first terminal coupled to the reference voltage, a second terminal coupled to the node, and a control terminal coupled to the control terminal of the first N-type transistor.

9. The voltage compensation circuit as claimed in claim 6, wherein the system voltage is a reference voltage, the control unit comprising: a third N-type transistor having a first terminal coupled to the second terminal of the first MOS capacitor, a second terminal coupled to the current mirror, and a control terminal; a third P-type transistor having a first terminal, a second terminal coupled to the control terminal of the third N-type transistor, and a control terminal coupled to the node; a resistor having a first terminal coupled to the reference voltage and a second terminal coupled to the second terminal of the third P-type transistor; and a current source coupled to the first terminal of the third P-type transistor.

10. The voltage compensation circuit as described in claim 9, wherein: The first branch unit includes a first P-type transistor having a first terminal coupled to a power supply voltage greater than the reference voltage, a second terminal coupled to the second terminal of the third N-type transistor, and a control terminal coupled to the second terminal of the first P-type transistor; and the second branch unit includes a second P-type transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the node, and a control terminal coupled to the control terminal of the first P-type transistor.

11. The voltage compensation circuit as claimed in claim 1, wherein the area of ​​the second MOS capacitor is N times the area of ​​the first MOS capacitor, and the second current is M times the first current, wherein N and M are greater than 1.

12. A phase-locked loop comprising: the voltage compensation circuit as described in claim 1; a phase-frequency detector for generating at least one control signal based on a phase and frequency difference between a feedback signal and a reference signal; a charge pump for generating a control voltage based on the control signal and outputting the control voltage through the node; a voltage-controlled oscillator for generating an output signal based on the control voltage; a frequency divider for dividing the output signal to generate the feedback signal; and a low-pass filter for low-pass filtering the control voltage.

13. The phase-locked loop as described in claim 12, wherein the low-pass filter includes a second MOS capacitor, and the first MOS capacitor and the second MOS capacitor are capacitors of the same type.

14. The phase-locked loop as described in claim 13, wherein the first MOS capacitor and the second MOS capacitor are manufactured using a process for manufacturing low-voltage components.

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