Wireless frame processing method and wireless communication device

Abstract

A wireless frame processing method includes: performing a first demodulation, a first equalization, a first data detection, and a first decoding on a physical layer header field of the wireless frame to obtain first header data with a first data rate; when the first header data fails the check, performing a second demodulation, a second equalization, and a second data detection on some symbols in a payload field of the wireless frame according to the first data rate, and performing a joint decoding on the physical layer header field and some symbols in the payload field, followed by a header decoding on a result of the second decoding to obtain second header data; and when the second header data passes the check, performing a third demodulation, a third equalization, a third data detection, and a payload decoding on the payload field based on a second data rate and a frame length in the second header data.

Description

Technical Field

[0001] This disclosure relates to the processing of wireless frames, and more particularly to a wireless frame processing method and a wireless communication device with joint decoding function. Prior Technology

[0002] Convolutional coding improves communication reliability by adding redundant information and is used in many communication network systems, such as wireless personal area networks (WPANs). At the receiver, Viterbi decoding is typically used. This utilizes the changing patterns of registers and the soft information obtained after equalization at the receiver to construct a transfer network and search for the optimal global path, thereby achieving coding gain. Ultra-wideband (UWB) systems using the 802.15.4 series of protocols also employ convolutional coding. In this series of protocols, when the constraint length of convolutional coding is 3, the header and payload fields are jointly encoded, and the decoding of the payload fields depends on the content of the header fields. In the conventional processing flow, the header fields are decoded first to obtain the data rate and frame length information of the payload fields, and then the payload fields are processed. Under this processing method, some fields in the header may lead to decoding errors due to insufficient backtracking length. If the header field cannot be decoded correctly, it will also affect the decoding performance of the payload field. Summary of the Invention

[0003] This disclosure proposes a resource unit configuration method, comprising: performing a first demodulation, a first equalization, a first data detection, and a first decoding on the physical layer header field of a wireless frame to obtain first header bit data, the first header bit data including a first data rate and a first frame length; if the first header bit data fails verification, performing a second demodulation, a second equalization, and a second data detection on the first M symbols in the payload field of the wireless frame according to the first data rate, and performing a second decoding on the first M symbols in the physical layer header field and the payload field, and performing header decoding on the result of the second decoding to obtain second header bit data, where M is a positive integer, and the second decoding is joint decoding; and if the second header bit data passes verification, performing a third demodulation, a third equalization, a third data detection, and a payload decoding on the payload field according to the second data rate and the second frame length in the second header bit data to obtain payload bit data.

[0004] This disclosure also proposes a wireless communication device, comprising a radio frequency (RF) circuit, a pulse shaper, a data detector, a data decoder, a header decoder, and a load decoder. The pulse shaper is coupled to the RF circuit, the data detector is coupled to the pulse shaper, the data decoder is coupled to the data detector, the header decoder is coupled to the data decoder, and the load decoder is coupled to the data decoder. The RF circuit, pulse shaper, and data detector are used to sequentially perform a first demodulation, a first equalization, and a first data detection on the first M symbols in the load field of the wireless frame according to the data rate in the physical layer header field of the wireless frame. The data decoder is used to perform a first decoding on the first M symbols in the physical layer header field and the load field, and the header decoder is used to perform header decoding on the result of the first decoding to obtain first header bit data, where M is a positive integer, and the first decoding is a joint decoding. After the first header bit data passes verification, the RF circuit, pulse shaper, data detector, and data decoder are used to sequentially perform second demodulation, second equalization, second data detection, and second decoding on the load field, and the load decoder is used to perform load decoding on the result of the second decoding to obtain the load bit data. Simple Explanation of the Diagram

[0005] To gain a more complete understanding of the embodiments and their advantages, the following description, taken in conjunction with the accompanying drawings, is provided, wherein: Figures 1 and 2 are schematic diagrams of the circuit blocks of the transmitting end and receiving end in the wireless communication network of the present disclosure embodiment; Figure 3 shows an example of an ultra-wideband frame; Figure 4 shows an example of a convolutional encoder used by the data encoder in the transmission end of Figure 1; Figure 5 shows an example of a symbol structure formed by burst position modulation (BPM); and Figure 6 is a flowchart of the wireless frame processing method according to an embodiment of this disclosure. Implementation

[0006] The embodiments disclosed herein are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0007] It is understood that while terms such as "first," "second," and "third" may be used in this disclosure to describe various signals, information, and / or operations, these terms should not limit these signals, information, and / or operations. These terms are used only to distinguish one signal, information, and / or operation from another.

[0008] Figures 1 and 2 are schematic diagrams of the circuit blocks of the transmitting end 100 and the receiving end 200 in the wireless communication network of the present disclosure embodiment. The wireless communication network can be a wireless personal area network, such as IEEE 802.15.3 or IEEE 802.15.4, and the transmitting end 100 can transmit wireless frames to the receiving end 200 through the channel in the wireless communication network. The transmitting end 100 and the receiving end 200 can be wireless communication devices that support technologies such as, but not limited to, ultra-wideband, Zigbee, and Thread. In some embodiments, the transmitting end 100 and the receiving end 200 may also have the functions of receiving and transmitting wireless frames, respectively.

[0009] As shown in Figure 1, the transmitting end 100 includes a header encoder 102, a payload encoder 104, a data encoder 106, a symbol mapper 108, a preamble inserter 110, a pulse shaper 112, and an RF circuit 114. The header encoder 102 and the payload encoder 104 are both coupled to the data encoder 106, and the data encoder 106, symbol mapper 108, preamble inserter 110, pulse shaper 112, and RF circuit 114 are coupled sequentially. The header encoder 102, payload encoder 104, data encoder 106, symbol mapper 108, preamble inserter 110, pulse shaper 112, and RF circuit 114 can be integrated into one or more chips. The header encoder 102 and payload encoder 104 encode the header bit data HB and the payload bit data PB, respectively. The encoded header bit data HB and the encoded payload bit data PB are merged into bit data DB, and then the data encoder 106 continuously encodes the bit data DB. Subsequently, the symbol mapper 108, the preamble inserter 110, the pulse shaper 112, and the radio frequency circuit 114 sequentially perform symbol mapping, preamble insertion, and modulation on the encoded bit data DB to generate a wireless frame F. The wireless frame F is transmitted from the antenna (not shown) of the transmitter 100 and transmitted to the receiver 200 via the wireless channel.

[0010] Corresponding to the transmitting end 100 in Figure 1, as shown in Figure 2, the receiving end 200 includes an RF circuit 202, a pulse shaper 204, a synchronizer 206, a data detector 208, a data decoder 210, a header decoder 212, and a load decoder 214. The RF circuit 202, pulse shaper 204, synchronizer 206, data detector 208, and data decoder 210 are sequentially coupled, and the header decoder 212 and load decoder 214 are jointly coupled to the data decoder 210. Similarly, the RF circuit 202, pulse shaper 204, synchronizer 206, data detector 208, data decoder 210, header decoder 212, and load decoder 214 can be integrated into one or more chips. At the receiving end 200, the antenna (not shown in the diagram) first receives the wireless frame F′ (formed by the influence of the wireless channel and noise on the wireless frame F). Then, the RF circuit 202, pulse shaper 204, synchronizer 206, and data detector 208 sequentially perform synchronization, demodulation, equalization, and data detection on the wireless frame F′ to obtain a bit stream. Subsequently, the data decoder 210 decodes the bit stream to obtain bit data DB, and the header decoder 212 and load decoder 214 decode the bit data DB to obtain header bit data HB and load bit data PB from the bit data DB, respectively.

[0011] The wireless frame transmitted from the transmitter 100 to the receiver 200 can be an ultra-wideband frame, and the data decoder 210, header decoder 212, and payload decoder 214 can be a convolutional decoder (e.g., a Viterbi decoder), a single error correction, double error detection (SECDED) decoder, and a Reed-Solomon decoder, respectively. Figure 3 shows an example of an ultra-wideband frame 300. The ultra-wideband frame 300 is a packet format in the IEEE 802.15.4 standard. It includes a synchronization field 310, a start of frame delimiter (SFD) field 320, a physical layer header (PHR) field 330, and a payload field 340. The synchronization field 310 is used for synchronization between the transmitter and receiver. The start of frame delimiter field 320 is used to indicate the starting point of the frame. The physical layer header field 330 contains payload-related information, and the payload field 340 is the physical service data unit (PSDU). Furthermore, the data structure of the entity layer header field 330 includes data rate 331, frame length 332, ranging packet 333, header extension 334, preamble duration 335, and single error correction double error detection check bit (hereinafter referred to as SECDED check bit) 336. Among them, data rate 331 is the transmission rate of the load, frame length 332 is the length of the load, ranging packet 333 is used to measure the distance between the transmitting end and the receiving end, header extension 334 is a reserved bit, preamble duration 335 is the length of synchronization field 310, and SECDED check bit 336 is used for frame decoding verification.

[0012] Data encoder 106 can use a convolutional encoder to continuously encode bit data DB. Figure 4 shows an example of a convolutional encoder 400 used by data encoder 106. As shown in Figure 4, the convolutional encoder 400 employs systematic coding with a constraint length and rate of 3 and 1 / 2, respectively, and includes registers 402 and 404 and an adder 406, wherein the input terminal of register 402 receives input bits. The input of register 404 is coupled to the output of register 402, and the two inputs of adder 406 are coupled to the input of register 402 and the output of register 404, respectively. Registers 402 and 404 are used to provide a unit delay to the input bits, while adder 406 is used to perform modulo-2 addition to obtain parity bits. In the convolutional encoder 400, the outputs of register 402 and adder 406 are used to output system bits. and corresponding position And the system-generated bits are output at the same time (i.e., the same n). and corresponding position This constitutes a symbol. Furthermore, in some embodiments, convolutional encoding may not be performed on the payload field 340.

[0013] Taking the ultra-wideband frame 300 shown in Figure 3 as an example, the entity layer header field 330 contains 19 bits, labeled H0, H1, ..., H18, while the subsequent payload field 340 contains N bits (N is a positive integer), labeled D0, D1, ..., D(N-1). The ultra-wideband frame 300 is encoded by the convolutional encoder 400, and the input bits corresponding to the symbol with index n... Systematic bits and corresponding position As shown in Table 1, T0 and T1 are the tail bits, while This represents modulo-2 addition. In this disclosed embodiment, the transmitting end performs continuous encoding on the entity layer header field 330 and the payload field 340, so the registers 402 and 404 will not return to zero at the end of the entity layer header field 330. Continuous encoding is the basis for the use of joint decoding. Table 1 Serial number n Input bits Systematic bits same position 0 H0 0 H0 1 H1 H0 H1 2 H2 H1 H0H2 3 H3 H2 H1H3 16 H16 H15 H14H16 17 H17 H16 H15H17 18 H18 H17 H16H18 19 D0 H18 H17D0 20 D1 D0 H18D1 21 D2 D1 D0D2 N+17 D(N-2) D(N-3) D(N-4)D(N-2) N+18 D(N-1) D(N-2) D(N-3)D(N-1) N+19 T0 D(N-1) D(N-2)T0 N+20 T1 T0 D(N-1)T1

[0014] Figure 5 shows an example of a symbol structure 500 formed by cluster position modulation. The symbol structure 500 corresponds to a symbol in a radio frame, where the position of the data is determined by the scrambling code and the system bits of the symbol, and the pulse polarity of the data is determined by the scrambling code and the corresponding bits of the symbol. Specifically, as shown in Figure 5, the symbol structure 500 has a symbol time length Tdsym, with Nhop possible cluster positions in both its first and second halves (each half a symbol time length TBPM, i.e., half the symbol time length Tdsym, and Nhop representing the number of possible cluster positions) and a subsequent guard interval GI. The encoded system bits determine whether the data is in the first or second half of the symbol structure 500, while the scrambling code determines one of the Nhop possible cluster positions. In the possible burst positions with data, the pulse polarity is determined by the scrambling code and the encoded corresponding bits, while the burst duration Tburst is determined by the mean pulse repetition frequency (mean PRF) and the data rate. The mean PRF is the number of chips per burst Ncpb divided by the duration Tdsym of one symbol (i.e., Ncpb / Tdsym). Since the burst position and duration of the payload field are both related to the data rate, and the payload data rate is recorded in the physical layer header section, the receiver must first decode the data rate of the physical layer header field to perform subsequent processing such as demodulation and equalization on the payload field.

[0015] Figure 6 is a flowchart of a wireless frame processing method 600 according to an embodiment of this disclosure. The wireless frame processing method 600 is applicable to the receiving end of a wireless communication network, such as the receiving end in Figure 2. Furthermore, the wireless frame decoded using the wireless frame processing method 600 can be, for example, an ultra-wideband frame.

[0016] In the wireless frame processing method 600, operation S602 is first performed to demodulate, equalize, detect data, and decode the entity layer header fields of the received wireless frame. Specifically, in operation S602, the entity layer header fields of the wireless frame are first demodulated, equalized, and detected sequentially to obtain the log-likelihood ratio (LLR) data of the corresponding entity layer header fields. Then, a convolutional decoder (e.g., a Viterbi decoder) is used to perform convolutional decoding on the LLR data of the corresponding entity layer header fields, and the decoding result of the convolutional decoder is used for header decoding to obtain header bit data (including data rate and frame length). The header decoder used for header decoding can be a decoder with error correction and verification functions, such as, but not limited to, a single-error-correction dual-error-detection decoder.

[0017] Next, operation S604 is performed to determine whether the obtained header bit data passes the verification. If the verification passes, operation S606 is performed to demodulate, equalize, detect, and decode the payload field of the wireless frame based on the data rate and frame length in the header bit data. Specifically, in operation S606, the payload field of the wireless frame is first demodulated, equalized, and detected sequentially to obtain the log-likelihood ratio data of the corresponding payload field. Then, a convolutional decoder (e.g., a Viterbi decoder) is used to perform convolutional decoding on the log-likelihood ratio data of the corresponding payload field, and the decoding result of the convolutional decoder is subjected to payload decoding (e.g., Reed-Solomon decoding) to obtain the payload bit data. After operation S606 is completed, operation S608 is performed to end the processing of the wireless frame.

[0018] Conversely, if the result of operation S604 is that the obtained header bit data fails the verification, operation S610 is performed. Based on the data rate in the header bit data, the first M symbols (M is a positive integer) in the payload field of the wireless frame are demodulated, equalized, and data detected (data parsing). Then, operation S612 is performed to jointly decode the first M symbols in the physical layer header field and payload field, and the header is decoded on the result of the joint decoding to obtain the header bit data (including data rate and frame length) again. Specifically, operation S610 involves sequentially demodulating, equalizing, and performing data detection (data parsing) on ​​the first M symbols in the payload field of the wireless frame to obtain the log-likelihood ratio data of the first M symbols in the corresponding payload field. Operation S612 involves concatenating the log-likelihood ratio data of the corresponding entity layer header field with the log-likelihood ratio data of the first M symbols in the corresponding payload field, and using a convolutional decoder (e.g., a Viterbi decoder) to perform continuous convolutional decoding on the concatenated log-likelihood ratio data. The decoding result of the convolutional decoder is then subjected to header decoding (which can be performed by a decoder with error correction and verification functions, such as a single-error-correction dual-error-detection decoder), to re-obtain the header bit data.

[0019] After operation S612 is completed, operation S614 is performed to determine whether the verification passes. If the verification passes, operation S606 is performed; otherwise, operation S608 is performed (indicating that header decoding has failed).

[0020] It should be noted that the aforementioned wireless frame processing method 600 includes an independent decoding section (operation S602) and a joint decoding section (operations S610 and S612). The independent decoding section processes only the physical layer header field of the wireless frame, while the joint decoding section processes the first few bits of the physical layer header field and payload field of the wireless frame. This processing is only performed if the independent decoding section fails the verification, in order to avoid negative gain. The joint decoding section is a new processing step disclosed in this invention compared to the conventional processing flow. Furthermore, the wireless frame processing method 600 can be implemented in hardware (e.g., the components in the receiver 200 of FIG2), or the decoding section can be implemented in firmware or software while the remaining parts can be implemented in hardware.

[0021] According to the wireless frame processing method 600, if the independent decoding of the entity layer header field fails (fails verification), an additional iteration can be performed. This involves convolutional decoding using the log-likelihood ratio data of several symbols in both the entity layer header and payload fields. This improves the problem of decoding failures in some bits of the entity layer header field due to insufficient traceback depth. It's important to note that if the data rate is decoded incorrectly during the independent decoding stage, the log-likelihood ratio data of the payload field calculated based on this data rate is also unreliable. In this case, the joint decoding iteration will not improve the Viterbi decoding result of the entity layer header field. Fortunately, for ultra-wideband frames, since the data rate occupies the first two bits in the entity layer header field, and the traceback depth of the data rate bits is relatively deeper than subsequent data, the data rate decoding usually succeeds during the independent decoding stage. However, subsequent data may fail to decode due to insufficient traceback depth. Therefore, joint decoding is expected to improve the decoding accuracy of the entity layer header field, and this expectation can be verified through simulation. The prioritization of data rate in the protocol design is likely based on this consideration.

[0022] The number of symbols (M) in the payload field used for joint decoding can be 5 to 10 times the number of symbols in the tail portion of the corresponding wireless frame (corresponding to the number of encoder registers, which is the encoder constraint length - 1, for example, if the constraint length is 3, the number of tail portions is 2) to improve decoding performance without excessively increasing the computational load. For example, if the convolutional encoder 400 in Figure 4 is used to encode the ultra-wideband frame 300, the first 10 bits (M=10) in the physical layer header field 330 and payload field 340 of the ultra-wideband frame 300 can be combined before joint decoding. Simulations show that, in use cases with an average pulse repetition frequency of 3.9MHz, a physical layer header rate of 850kbps, and a load rate of 850kbps, the joint decoding method reduces the signal-to-noise ratio (SNR) required for a 1% packet error rate (PER) in physical layer header field 330 by 0.4 dB compared to using only independent decoding. For use cases with an average pulse repetition frequency of 62.4MHz, a physical layer header rate of 6.8Mbps, and a load rate of 6.8Mbps, the joint decoding method also reduces the SNR required for a 1% packet error rate (PER) in physical layer header field 330 by 0.8 dB compared to using only independent decoding.

[0023] In summary, the embodiments disclosed herein employ an iterative processing method to jointly decode the entity layer header field and a portion of the payload field in the received wireless frame, thereby avoiding decoding errors caused by insufficient backtracking depth in the entity layer header field. Therefore, in scenarios where payload field decoding depends on header field content and the header and payload fields are encoded consecutively, the embodiments disclosed herein can improve the packet error rate performance of the entity layer header field and correspondingly improve the packet error rate performance of the payload field.

[0024] In summary, this disclosure provides a wireless frame processing method, comprising: performing a first demodulation, a first equalization, a first data detection, and a first decoding on the physical layer header field of the wireless frame to obtain first header bit data, the first header bit data including a first data rate and a first frame length; if the first header bit data fails verification, performing a second demodulation, a second equalization, and a second data detection on the first M symbols in the payload field of the wireless frame according to the first data rate, and performing a second decoding on the first M symbols in the physical layer header field and the payload field, and performing header decoding on the result of the second decoding to obtain second header bit data, where M is a positive integer, and the second decoding is joint decoding; and if the second header bit data passes verification, performing a third demodulation, a third equalization, a third data detection, and a payload decoding on the payload field according to the second data rate and the second frame length in the second header bit data to obtain payload bit data. In one embodiment, the first decoding of the entity layer header field and the joint decoding of the first M symbols in the entity layer header field and the payload field respectively include convolutional decoding of the entity layer header field and sequential convolutional decoding of the first M symbols in the entity layer header field and the payload field. In one embodiment, the convolutional decoding of the entity layer header field and the sequential convolutional decoding of the first M symbols in the entity layer header field and the payload field are performed by a Viterbi decoder. In one embodiment, header decoding is performed by a single-error-corrected dual-error-detection decoder. In one embodiment, payload decoding is performed by a Reed-Solomon decoder. In one embodiment, the wireless frame is an ultra-wideband frame. In one embodiment, the joint decoding of the first M symbols in the entity layer header field and the payload field to obtain the second header bit data is performed by a single-error-corrected dual-error-detection decoder. In one embodiment, the wireless frame processing method further includes, after the first header bit data has been verified, performing third demodulation, third equalization, third data detection, and load decoding on the load field according to the first data rate and the first frame length to obtain the load bit data. In one embodiment, M is 5 to 10 times the number of bytes in the tail portion of the corresponding wireless frame.

[0025] In summary, this disclosure also provides a wireless communication device, comprising a radio frequency (RF) circuit, a pulse shaper, a data detector, a data decoder, a header decoder, and a load decoder. The pulse shaper is coupled to the RF circuit, the data detector is coupled to the pulse shaper, the data decoder is coupled to the data detector, the header decoder is coupled to the data decoder, and the load decoder is coupled to the data decoder. The RF circuit, pulse shaper, and data detector are used to sequentially perform a first demodulation, a first equalization, and a first data detection on the first M symbols in the load field of the wireless frame according to the data rate in the physical layer header field of the wireless frame. The data decoder is used to perform a first decoding on the first M symbols in the physical layer header field and the load field, and the header decoder is used to perform header decoding on the result of the first decoding to obtain first header bit data, where M is a positive integer, and the first decoding is a joint decoding. After the first header bit data passes verification, the RF circuit, pulse shaper, data detector, and data decoder sequentially perform second demodulation, second equalization, second data detection, and second decoding on the load field. The load decoder then performs load decoding on the result of the second decoding to obtain the load bit data. In one embodiment, the data decoder is a convolutional decoder. In another embodiment, the convolutional decoder is a Viterbi decoder. In one embodiment, the header decoder is a single-error-corrected dual-error-detection decoder. In one embodiment, the load decoder is a Reed-Solomon decoder. In one embodiment, the wireless frame is an ultra-wideband frame. In one embodiment, the radio frequency circuit, pulse shaper, data detector, and data decoder are further configured to sequentially perform a third demodulation, a third equalization, a third data detection, and a third decoding on the physical layer header field before sequentially performing the first demodulation, the first equalization, the first data detection, and the first decoding to obtain the second header bit data. If the second header bit data fails verification, the radio frequency circuit, pulse shaper, data detector, and data decoder sequentially perform the first demodulation, the first equalization, the first data detection, and the first decoding. In one embodiment, M is 5 to 10 times the number of bytes in the tail portion of the corresponding wireless frame.

[0026] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

[0027] 100: Transmission end 102: Standard Head Encoder 104: Load Encoder 106: Data Encoder 108: Symbolic Enumerator 110: Preamble Insertor 112,204: Pulse Shaper 114,202: Radio Frequency Circuits 200: Receiver 206: Synchronizer 208: Data Detector 210: Data Decoder 212: Header Decoder 214: Load Decoder 300: Ultra-wideband frame 310: Synchronized Fields 320: Message frame start delimiter field 330: Entity Layer Header Field 331: Data Rate 332: Frame length 333: Ranging packet 334: Header Extension 335: Preamble Duration 336: SECDED check bits 340: Load field 400: Convolutional Encoder 402, 404: Temporary registers 406: Adder 500: Symbol Structure 600: Wireless Frame Processing Method DB: Bit Data F,F′: Wireless frame GI: Guard Interval HB: Header bit data Ncpb: Number of chips Nhop: Number of possible cluster locations PB: Load bit data S602, S604, S606, S608, S610, S612, S614: Operation TBPM: The duration of half a rune Tburst: Duration of burst Tc: Chip Time Length Tdsym: The duration of a symbol Input bits System bits : Same position

Claims

1. A wireless frame processing method, comprising: performing a first demodulation, a first equalization, a first data detection, and a convolutional decoding on a physical layer header field of a wireless frame to obtain a first header bit data, the first header bit data including a first data rate and a first frame length; if the first header bit data fails verification, performing a second demodulation, a second equalization, and a second data detection on the first M symbols in a payload field of the wireless frame according to the first data rate, and performing a continuous convolutional decoding on the physical layer header field and the first M symbols, and performing header decoding on a result of the continuous convolutional decoding to obtain a second header bit data, wherein M is a positive integer; and if the second header bit data passes verification, performing a third demodulation, a third equalization, a third data detection, and a payload decoding on the payload field according to a second data rate and a second frame length in the second header bit data to obtain payload bit data.

2. The wireless frame processing method as described in claim 1, wherein the convolutional decoding of the entity layer header field and the sequential convolutional decoding of the entity layer header field and the first M symbols are performed by a one-dimensional terbi decoder.

3. The wireless frame processing method as described in claim 1, wherein the header decoding is performed by a single error correction, double error detection (SECDED) decoder.

4. The wireless frame processing method as described in claim 1, wherein the payload decoding is performed by a Reed-Solomon decoder.

5. The wireless frame processing method as described in claim 1, wherein the wireless frame is an ultra-wideband (UWB) frame.

6. The wireless frame processing method as described in claim 1 further includes: under the condition that the first header bit data passes verification, performing the third demodulation, the third equalization, the third data detection, and the load decoding on the load field according to the first data rate and the first frame length to obtain the load bit data.

7. The wireless frame processing method as described in claim 1, wherein M is 5 to 10 times the number of tail bits corresponding to one of the wireless frames.

8. A wireless communication device, comprising: a radio frequency circuit; a pulse shaper coupled to the radio frequency circuit; a data detector coupled to the pulse shaper; and a data decoder coupled to the data detector. And a header decoder, coupled to the data decoder; The system includes a load decoder coupled to the data decoder; wherein: the radio frequency circuit, the pulse shaper, and the data detector are used to sequentially perform a first demodulation, a first equalization, and a first data detection on the first M symbols in the load field of a wireless frame according to a data rate in the physical layer header field of a wireless frame; the data decoder is used to perform a first decoding on the physical layer header field and the first M symbols; and the header decoder is used to perform header decoding on the result of the first decoding to obtain a first header bit data, where M is a positive integer, and the first decoding is a continuous convolutional decoding; after the first header bit data passes verification, the radio frequency circuit, the pulse shaper, the data detector, and the data decoder are used to sequentially perform a second demodulation, a second equalization, a second data detection, and a second decoding on the load field; and the load decoder is used to perform load decoding on the result of the second decoding to obtain a load bit data.

9. The wireless communication device as claimed in claim 8, wherein the radio frequency circuit, the pulse shaper, the data detector, and the data decoder are further configured to sequentially perform a third demodulation, a third equalization, a third data detection, and a convolutional decoding on the physical layer header field before sequentially performing the first demodulation, the first equalization, the first data detection, and the sequential convolutional decoding to obtain a second header bit data, and if the second header bit data fails verification, the radio frequency circuit, the pulse shaper, the data detector, and the data decoder sequentially perform the first demodulation, the first equalization, the first data detection, and the sequential convolutional decoding.

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