Clock output apparatus having phase detection and calibration mechanism

Abstract

A clock output apparatus is provided. A clock output circuit generates output clock signals. A phase detection circuit includes a cross-coupled pair circuit, a differential input pair circuit and a determining circuit. The cross-coupled pair circuit is coupled between a power voltage and two output terminals. The differential input pair circuit is coupled between the output terminals and a ground terminal and has two input terminals to receiving the output clock signals. The output terminals generates output signals both within and both beyond a predetermined range respectively when the phases of the output clock signals are the same and opposite such that the determining circuit generates a phase determining result. The clock output circuit performs a phase calibration process when being operated from a second mode to a first mode and when the phase determining result indicates that the output clock signals does not have a predetermined phase relation.

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