Reception apparatus, memory controller, and memory system

Abstract

A reception apparatus includes a conversion circuit, a plurality of comparison circuits, and a selection circuit. The conversion circuit converts a second digital signal into a third digital signal synchronized with a phase of a first digital signal. The plurality of comparison circuits each shift a bit sequence of the first digital signal by a predetermined number and count a number of bit errors by comparing the bit sequence of the first digital signal shifted by the predetermined number with a bit sequence of the third digital signal. The selection circuit selects any one of the plurality of comparison circuits based on the plurality of numbers of bit errors respectively counted by the plurality of comparison circuits and detects the number of bit errors counted by the selected comparison circuit as an actual number of bit errors.

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