Bitline clamping circuits for bitline-cut image sensors

Abstract

Bitline cut image sensors with ASIC clamping are disclosed. In some embodiments, a imaging system includes a pixel array and a replica voltage reference generation circuit. The pixel array can include a plurality of pixel circuits, select ones of the pixel circuits each including a row select transistor and a source follower transistor coupled between a supply voltage and the row select transistor. The replica voltage reference generation circuit can have a input coupled to the row select transistor. The replica voltage reference generation circuit can be configured to receive a voltage at the input and generate a clamp voltage that follows the voltage received at the input for each of one or more bitlines coupled to one or more outputs of the replica voltage reference generation circuit.

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