Semiconductor memory structure and method for forming the same

Abstract

A semiconductor memory structure and a method for forming the same are provided. The semiconductor memory structure includes a substrate, a first word line, a second word line and a bit line structure. The first word line and the second word line are embedded in the substrate. The bit line structure extends from the substrate between the first word line and the second word line to above the substrate. The bit line structure includes a first conductive layer, a titanium silicon nitride layer and a second conductive layer. The titanium silicon nitride layer is located on the first conductive layer. The titanium silicon nitride layer includes a lower portion and an upper portion. The silicon atomic percentage in the lower portion is greater than the silicon atomic percentage in the upper portion. The second conductive layer is located on the titanium silicon nitride layer.

Description

[Technical Field]

[0001] This invention relates to semiconductor memory structures and methods for forming them, and particularly to bit line structures of semiconductor memory structures and methods for forming them. [Previous Technology]

[0002] To increase the component density within Dynamic Random Access Memory (DRAM) devices and improve their overall performance, current integrated circuit device manufacturing technologies continue to strive towards miniaturization of component sizes. However, as manufacturing processes evolve and component sizes continue to shrink, many challenges arise. For example, how to improve the reliability of bit lines to increase component yield. [Summary of the Invention]

[0003] Embodiments of the present invention provide a semiconductor memory structure, including a substrate, a first word line, a second word line, and a bit line structure. The first word line and the second word line are embedded in the substrate. The bit line structure extends from the substrate between the first word line and the second word line to the substrate. The bit line structure includes a first conductive layer, a titanium nitride silicon layer, and a second conductive layer. The titanium nitride silicon layer is located on the first conductive layer. The titanium nitride silicon layer includes a lower portion and an upper portion. The percentage of silicon atoms in the lower portion is greater than the percentage of silicon atoms in the upper portion. The second conductive layer is located on the titanium nitride silicon layer.

[0004] This invention provides a method for forming a semiconductor memory structure, including providing a substrate; forming a first word line and a second word line embedded in the substrate; and forming a bit line structure. The bit line structure extends from the substrate between the first word line and the second word line onto the substrate. The bit line structure includes a first conductive layer, a titanium nitride silicon layer, and a second conductive layer. The titanium nitride silicon layer is located on the first conductive layer. The second conductive layer is located on the titanium nitride silicon layer. The titanium nitride silicon layer includes a lower portion and an upper portion. The percentage of silicon atoms in the lower portion is greater than the percentage of silicon atoms in the upper portion.

Implementation Method

[0005] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the present invention. However, the present disclosure may be implemented in various different ways and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements.

[0006] In the conventional bit line fabrication process of dynamic random access memory (DRAM), a siliconization process is required to reduce the contact resistance between the bit line and the substrate. However, in the siliconization process, the high-temperature (approximately 800°C to 850°C) annealing process may cause uneven siliconization reaction. Some metal atoms of the conductive layer of the bit line or metal silicon silylates that react more violently may diffuse downwards to the bit line junction, resulting in an uneven film profile of the bit line and causing failure problems such as leakage. Therefore, a bit line structure of dynamic random access memory and its formation method are needed to improve the aforementioned problems.

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor memory structure 500 according to some embodiments of the present invention. In some embodiments, the semiconductor memory structure 500 is an integrated circuit structure including a memory array and peripheral components. The memory array includes a dynamic random access memory (DRAM) array or other suitable memory array. The peripheral components include metal-oxide-semiconductor field-effect transistors (MOS FETs) or other suitable peripheral components. The semiconductor memory structure 500 includes a substrate 200, an isolation component 206, an active region A1, a word line 230, and a bit line structure 250. Reference directions are indicated for ease of explanation. Directions 100 and 110 are substantially parallel to the top surface 200T of the substrate 200, and direction 120 is substantially perpendicular to the top surface 200T of the substrate 200. Furthermore, direction 100 is the bit line extension direction, and direction 110 is the gate extension direction (or word line extension direction).

[0008] In some embodiments, the substrate 200 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 200 may be a semiconductor-on-insulator (SOI) substrate. In some embodiments, the conductivity type of the substrate 200 may be P-type or N-type as required by design.

[0009] A plurality of isolation members 206 are disposed in corresponding plurality of trenches 204 of the substrate 200. The isolation members 206 may define an active region A1. In some embodiments, the isolation members 206 may be shallow trench isolation (STI). The isolation members 206 may include at least an insulating liner 208 and an insulating filler layer 212.

[0010] The insulating liner 208 of the isolation member 206 covers the bottom surface and opposite sidewalls of the trench 204. In some embodiments, the insulating liner 208 may be made of silicon oxide, which may be formed using in-situ steam generation (ISSG), chemical vapor deposition (CVD), and / or atomic layer deposition (ALD).

[0011] An insulating filler layer 212 fills the trench 204 and covers the insulating liner 208. In some embodiments, the insulating filler layer 212 is formed of a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), other suitable materials, and / or combinations thereof, which may be formed using chemical vapor deposition and / or atomic layer deposition.

[0012] The semiconductor memory structure 500 may include one or more memory cells, which may include word lines 230 (including word lines 230-1, 230-2, 230-3, 230-4), bit line structure 250, and storage capacitors (not shown). The word lines 230 are embedded in word line trenches (not shown) of the substrate 200 within the active region A1 and extend along direction 110 across the active region A1 and the isolation member 206. In some embodiments, the word line 230 includes a gate dielectric layer, a conductive structure disposed on the gate dielectric layer, and a work function adjustment structure disposed on the conductive structure. The word line 230 also includes a liner disposed between the conductive structure and the work function adjustment structure.

[0013] The memory cell further includes an insulating cap layer 242 and an insulating cap layer 213. The insulating cap layer 242 is disposed on the word line 230 and fills the upper part of the word line trench. The insulating cap layer 213 is formed on the top surface 200T of the substrate 200 and covers the word line 230. In some embodiments, the insulating cap layer 242 may be formed of a dielectric material, such as silicon nitride or silicon oxide.

[0014] The bit line structure 250 of the memory cell is disposed in the substrate 200 between word line 230-2 and word line 230-3, extends to the substrate 200, and extends in the direction 100 across the active region A1, the isolation component 206, word lines 230-1, 230-2, 230-3, and 230-4.

[0015] In some embodiments, the bit line structure 250 includes a conductive layer 248, a first conductive layer 251, a titanium nitride silicon layer 252, a second conductive layer 254, and a masking layer 256 formed sequentially from bottom to top.

[0016] The conductive layer 248 is located on the substrate 200 and covers the insulating cap layer 213, the insulating cap layer 242 and the character line 230.

[0017] The first conductive layer 251 passes through the insulating cap layer 213 and the conductive layer 248, and extends into the portion of the substrate 200 between the word lines 230-2 and 230-3 to serve as a contact portion of the bit line structure 250. In some embodiments, the conductive layer 248 and the first conductive layer 251 may comprise the same or similar materials, such as doped or undoped polysilicon.

[0018] A titanium nitride silicon layer 252 is located on the first conductive layer 251. The titanium nitride silicon layer 252 includes a lower portion 252L and an upper portion 252U. The lower portion 252L of the titanium nitride silicon layer 252 is connected to the first conductive layer 251, and the upper portion 252U is located on the lower portion 252L and connected to the lower portion 252L. The titanium nitride silicon layer 252 is a single-layer structure. For example, the lower portion 252L and the upper portion 252U of the titanium nitride silicon layer 252 are formed continuously, so there may be no interface between them.

[0019] In some embodiments, the lower portion 252L and the upper portion 252U of the titanium nitride silicon layer 252 may have different atomic percentages (at.%) of titanium (Ti), silicon (Si), and nitrogen (N) to function as both a metal silicate and a barrier material. For example, the lower portion 252L and the upper portion 252U of the titanium nitride silicon layer 252 may have different silicon atomic percentages. In some embodiments, the silicon atomic percentage of the lower portion 252L of the titanium nitride silicon layer 252 is greater than that of the upper portion 252U; for example, the silicon atomic percentage of the lower portion and the upper portion of the titanium nitride silicon monolayer gradually decreases. Therefore, the lower portion 252L of the titanium nitride silicon layer 252 has properties similar to those of metal silicide (titanium silicon), which can reduce the junction resistance between the lower portion 252L and the first conductive layer 251, further reducing the resistance of the bit line structure 250, thereby improving the electrical properties of the semiconductor memory structure 500. Furthermore, the upper portion 252U of the titanium nitride silicon layer 252 has properties similar to those of a diffusion barrier layer (titanium nitride). In other words, it can prevent cross-diffusion between the upper and lower layers (titanium nitride silicon layer 252 and the upper second conductive layer 254), thereby enhancing the thermal stability and reliability of the semiconductor memory structure 500.

[0020] In some embodiments, the percentage of silicon atoms in the lower portion 252L of the titanium nitride silicon layer 252 may be between 35% and 45%. If the percentage of silicon atoms in the lower portion 252L is too low, the atomic percentage of titanium and silicon will become high, which will increase the resistance of the bit line structure 250 and affect the electrical properties of the semiconductor memory structure 500.

[0021] In some embodiments, the percentage of silicon atoms in the upper portion 252U of the titanium nitride silicon layer 252 may be less than 5%, for example, between 3% and 5%. If the percentage of silicon atoms in the upper portion 252U is too high, the atomic percentages of titanium and silicon will be low, which will worsen the barrier properties of the upper portion 252U and prevent the conductive atoms (e.g., metal atoms) of the second conductive layer 254 from penetrating the titanium nitride silicon layer 252 and diffusing into the first conductive layer 251, causing electrical failure of the semiconductor memory structure 500.

[0022] In some embodiments, the ratio of titanium atomic percentage to silicon atomic percentage in the lower portion 252L of the titanium nitride silicon layer 252 is less than 1.2, for example, between 0.8 and 1.2, or for example, it may be 1 (meaning that titanium and silicon in the lower portion 252L have the same atomic percentage). If the atomic percentage of titanium and silicon is too high, the properties of the metal silicate will deteriorate, affecting the resistance of the bit line structure 250. In some embodiments, the titanium atomic percentage in the lower portion 252L of the titanium nitride silicon layer 252 is between 35% and 45%. In some embodiments, the nitrogen atomic percentage in the lower portion 252L of the titanium nitride silicon layer 252 is between 10% and 30%.

[0023] The ratio of titanium atoms to nitrogen atoms in the upper portion 252U of the titanium nitride silicon layer 252 is between 1.8 and 5.3. If the atomic percentages of titanium and nitrogen are too low, the barrier properties will deteriorate, affecting the reliability of the semiconductor memory structure 500. In some embodiments, the titanium atom percentage in the upper portion 252U of the titanium nitride silicon layer 252 is between 60% and 80%. In some embodiments, the nitrogen atom percentage in the upper portion 252U of the titanium nitride silicon layer 252 is between 15% and 35%.

[0024] In some embodiments, the thickness T252 of the titanium nitride silicon layer 252 can be between 13.5 Å and 65 Å. The upper portion 252U of the titanium nitride silicon layer 252 has a first thickness T1, and the lower portion 252L has a second thickness T2, wherein the first thickness T1 is greater than the second thickness T2. For example, the ratio of the first thickness T1 to the second thickness T2 can be between 3:2 and 4:1.

[0025] The second conductive layer 254 is located on the upper portion 252U of the titanium nitride silicon layer 252. In some embodiments, the second conductive layer 254 comprises a metallic material, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), a metal alloy, or a combination thereof. In some embodiments, a barrier layer 253, such as tungsten silicon (WSi), may be provided between the second conductive layer 254 and the titanium nitride silicon layer 252.

[0026] The method for forming the semiconductor structure 500 is described below using Figures 1 and 2. Referring to Figure 1, a substrate 200 is provided. Next, a pad layer (not shown) can be formed on the top surface 200T of the substrate 200. The pad layer can be an isolation layer and can also serve as a stop layer for subsequent etching. The pad layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide nitride (SiCN), silicon oxynitride (SiON), silicon oxynitride (SiOCN), other available materials, or combinations thereof.

[0027] Subsequently, a patterning process is performed to form a plurality of trenches 204 in the substrate 200 to define the formation locations of the plurality of isolation members 206 and the active region A1. In some embodiments, the trenches 204 surround the active region A1.

[0028] Next, an insulating liner 208 is compliantly formed on the sidewalls and bottom surface of the trench 204. In some embodiments, the liner 208 may include silicon oxide.

[0029] Next, a deposition process and a subsequent planarization process are performed to form an insulating filler layer 212 in the trench 204 of the substrate 200 to form an isolation member 206 and define the active region A1 of the substrate 200.

[0030] Next, a patterning process (e.g., lithography and etching) is performed to form character line trenches (not shown) in the active region A1 and the isolation member 206. Because the etching rates in the active region A1 and the isolation member 206 are different, the trench depths formed in the active region A1 and the isolation member 206 are different. In some embodiments, the character line trench depth in the isolation member 206 is greater than the character line trench depth in the active region A1.

[0031] Next, a multi-stage deposition and etching process is performed to form character lines 230-1, 230-2, 230-3, 230-4, and an insulating capping layer 242 embedded in the substrate 200 within the character line trenches of the active region A1. The insulating capping layer 242 fills the character line trenches above the character lines 230-1, 230-2, 230-3, and 230-4.

[0032] Next, a deposition process such as atomic layer deposition (ALD) is performed to form an insulating capping layer 213, such as silicon nitride (Si3N4), silicon carbide (SiCN), silicon oxynitride (SiON), or silicon oxycarbon (SiOCN), overly on the substrate 200 and the isolation component 206.

[0033] Next, a conductive layer 248 is deposited over the insulating capping layer 213, and a hard masking layer (not shown) is deposited over the conductive layer 248. The hard masking layer may include an oxide (e.g., silicon oxide). Next, an opening (not shown) is formed in the active region A1 between the character lines 230 using a patterning process (e.g., lithography and etching). In some embodiments, the opening passes through the hard masking layer, the conductive layer 248, the insulating capping layer 213, and the active region A1, and is located between character lines 230-2 and 230-3. Afterward, the hard masking layer is removed.

[0034] Next, a deposition process and a subsequent planarization process, such as chemical mechanical polishing (CMP), are performed to form a first conductive layer 251 in the opening.

[0035] Next, the method for forming the titanium nitride silicon layer 252 (Figure 1) will be described. Figure 2 is a flowchart of the method for forming the titanium nitride silicon layer 252 of the bit line structure 250 of the semiconductor memory structure 500 according to some embodiments of the present invention. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H are schematic diagrams of the steps of the titanium nitride process cycle and the silicon nitride process cycle for forming the lower portion 252L or the upper portion 252U (Figure 1) of the titanium nitride silicon layer 252 according to some embodiments of the present invention. In some embodiments, the lower portion 252L and the upper portion 252U of the titanium nitride silicon layer 252 can be formed using an atomic layer deposition (ALD) process.

[0036] The following describes a method for forming the lower portion 252L of the titanium silicon nitride layer 252. First, as shown in Figures 2 and 3A, step 2002 is performed, in which the intermediate structure 300 placed on the platform 352 of the deposition chamber 350 is cycled through a titanium nitride process. In the embodiment where the lower portion 252L of the titanium silicon nitride layer 252 is formed, the intermediate structure 300 is a substrate 200 (Figure 1) having an isolation component 206, a character line 230, and a first conductive layer 251, and the first conductive layer 251 is cycled through a titanium nitride process. As shown in Figure 3A, the first step of the titanium nitride process cycle is to provide a pulse of the first precursor 310 to the deposition chamber 350 and guide it to the intermediate structure 300, so that the exposed surface of the first conductive layer 251 adsorbs the first precursor 310 and forms a first precursor layer 310L (Figure 3B) for subsequent reactions. In some embodiments, the first precursor 310 includes a titanium-containing precursor, such as titanium tetrachloride (TiCl4). In embodiments where the first precursor 310 is titanium tetrachloride, the titanium atoms of titanium tetrachloride are chemically bonded to the surface of the first conductive layer 251, and the chlorine atoms are exposed to the ambient gas in the deposition chamber 350.

[0037] As shown in Figure 3B, the second step of the titanium nitride process cycle is then performed: purging the deposition chamber 350. A purging gas (e.g., an inert gas including argon, xenon, helium, or similar gases) (not shown) can be delivered to the deposition chamber 350, and a evacuation device (not shown) connected to the deposition chamber 350 can be used to remove the first precursor 310 (Figure 3A) from the deposition chamber 350.

[0038] As shown in Figure 3C, the third step of the titanium nitride process cycle is then performed: a pulse of the second precursor 312 is provided to the deposition chamber 350 and directed to the intermediate structure 300, causing the first precursor layer 310L to react with the second precursor 312. After performing the third step, a titanium nitride monolayer 314 is formed (as shown in Figure 3D). In some embodiments, the titanium nitride monolayer 314 may be substantially silicon-free. In some embodiments, the second precursor 312 includes ammonia (NH3). In embodiments where the first precursor 310 is titanium tetrachloride and the second precursor 312 is ammonia, the titanium tetrachloride layer reacts with ammonia to form a titanium nitride (TiN) monolayer (Figure 3D) and hydrogen chloride (HCl) gas, and the hydrogen chloride gas can be extracted from the deposition chamber 350 by a pumping device.

[0039] As shown in Figure 3D, the fourth step of the titanium nitride process cycle is then performed: purifying the deposition chamber 350. A purifying gas (e.g., an inert gas) can be supplied to the deposition chamber 350, and a vacuum device (not shown) connected to the deposition chamber 350 can be used to remove the second precursor 312 and hydrogen chloride (HCl) gas (Figure 3C) from the deposition chamber 350, leaving the titanium nitride monolayer 314 on the intermediate structure 300. After purifying the deposition chamber 350, one titanium nitride process cycle is completed.

[0040] Next, step 2004 is performed, repeating the titanium nitride process cycle for the first time to form a titanium nitride molecular layer 316 comprising multiple titanium nitride monolayers 314 (Figure 3E shows the surface portion of the titanium nitride molecular layer 316). For example, the first, second, third, and fourth steps of the above-described titanium nitride process cycle are repeated.

[0041] Next, step 2006 is performed to cycle the silicon nitride process on the titanium nitride molecular layer. As shown in Figure 3E, the first step of the silicon nitride process cycle is to pulse a third precursor 318 into the deposition chamber 350 and direct it to the intermediate structure 300, so that the exposed surface of the titanium nitride molecular layer 316 adsorbs the third precursor 318 and forms a third precursor layer 318L (Figure 3F) for subsequent reactions. In some embodiments, the third precursor 318 includes a silicon-containing precursor, such as dichlorosilane (SiH2Cl2, DCS). In embodiments where the third precursor 318 is dichlorosilane, the silicon atoms of the dichlorosilane are chemically bonded to the surface of the titanium nitride molecular layer 316, and the chlorine atoms are exposed to the ambient gas in the deposition chamber 350.

[0042] As shown in Figure 3F, the second step of the silicon nitride process cycle is then performed: purifying the deposition chamber 350. A purifying gas (e.g., an inert gas including argon, xenon, helium, or similar gases) may be delivered to the deposition chamber 350, and a vacuum device (not shown) connected to the deposition chamber 350 may be used to remove the third precursor 318 from the deposition chamber 350.

[0043] As shown in Figure 3G, the third step of the silicon nitride process cycle is then performed: a pulse of the second precursor 312 is provided to the deposition chamber 350 and directed to the intermediate structure 300, causing the third precursor layer 318L to react with the second precursor 312. After performing the third step, a silicon nitride monolayer 320 is formed (as shown in Figure 3H). In some embodiments, the second precursor 312 includes ammonia (NH3). In embodiments where the third precursor 318 is dichlorosilane and the second precursor 312 is ammonia, the dichlorosilane layer reacts with ammonia to form a silicon nitride (SiN) monolayer and hydrogen chloride (HCl) gas, and the hydrogen chloride gas can be extracted from the deposition chamber 350 by a pumping device.

[0044] As shown in Figure 3H, the fourth step of the silicon nitride process cycle is then performed: purifying the deposition chamber 350. A purifying gas (e.g., an inert gas) can be supplied to the deposition chamber 350, and an extraction device (not shown) connected to the deposition chamber 350 can be used to remove the second precursor 312 and hydrogen chloride (HCl) gas from the deposition chamber 350, while retaining the silicon nitride monolayer 320 on the titanium nitride molecular layer 316. After purifying the deposition chamber 350, one silicon nitride process cycle is completed.

[0045] Next, step 2008 is performed to repeat the titanium nitride process cycle for the second time to form a silicon nitride molecular layer 322 comprising multiple silicon nitride monolayers 320 (the silicon nitride molecular layer 322 in Figure 3H comprises one silicon nitride monolayer 320). For example, the first, second, third, and fourth steps of the silicon nitride process cycle can be repeated in the order of the first, second, third, and fourth steps of the above-described silicon nitride process cycle.

[0046] During step 2008, the silicon nitride molecular layer 322 reacts with the underlying titanium nitride molecular layer 316 to form a titanium silicon nitride molecular layer 324. After the titanium silicon nitride molecular layer is formed, one titanium silicon nitride process cycle is completed.

[0047] Next, step 2010 is performed, and the titanium silicon nitride process cycle is repeated for the third time. After step 2010, the lower portion 252L of the titanium silicon nitride layer 252 is formed. In the embodiment of forming the lower portion 252L of the titanium silicon nitride layer 252, the ratio of the first number to the second number can be between 2:1 and 3:1, the third number can be between 5 and 10, and the thickness of the titanium silicon nitride molecular layer 324 can be between 1.5 Å and 2.5 Å.

[0048] After forming the lower portion 252L of the titanium nitride silicon layer 252, steps 2002, 2004, 2006, 2008, and 2010 can be performed on the intermediate structure 300 placed in the deposition chamber 350 in the order of steps 2002, 2004, 2006, 2008, and 2010 to continuously form the upper portion 252U of the titanium nitride silicon layer 252 in the same deposition chamber 350. The ratio of the first to the second number of times in the upper portion 252U is higher than that in the lower portion 252L. In the embodiment of forming the upper portion 252U of the titanium nitride silicon layer 252, the ratio of the first to the second number can be between 25:1 and 40:1, the third number can be between 1 and 2, and the thickness of the titanium nitride silicon molecular layer 324 is between 6 Å and 20 Å. The third number of the upper 252U is lower than that of the lower 252L, and the third number can be controlled to adjust the ratio of the upper and lower thicknesses of the titanium nitride silicon layer. After the upper 252U of the titanium nitride silicon layer 252 is formed, the titanium nitride silicon layer 252 is formed.

[0049] Next, as shown in Figure 1, a deposition process is performed to sequentially form a barrier layer 253, a second conductive layer 254, and a masking layer 256 on the titanium nitride silicon layer 252. Subsequently, a patterning process is performed on the first conductive layer 251, the titanium nitride silicon layer 252, the second conductive layer 254, and the masking layer 256 to form a bit line structure 250.

[0050] In addition, additional components can be formed on the semiconductor memory structure 500 of Figure 1. For example, a patterning process, a deposition process, and a subsequent removal process can be performed to form a storage capacitor (not shown) on the active region A1 between different bit line structures 250. After the above process, the semiconductor memory structure 500 is formed.

[0051] In some embodiments, the titanium nitride silicon layer 252 formed by atomic layer deposition at a relatively low process temperature (approximately 500 °C to 600 °C) serves as both a metal silicate and a barrier material. Therefore, conventional metal silicate processes, particularly the high-temperature annealing process, are not required to form the metal silicate layer. This further prevents uneven silanization reactions that could cause metal atoms from the conductive layer above the metal silicate or from the metal silicate to diffuse into the first conductive layer 251, resulting in uneven contours of the bit line film layer of the semiconductor memory structure 500 and subsequent bit line leakage failure.

[0052] In the method for forming a semiconductor memory structure according to an embodiment of the present invention, a titanium nitride silicon layer is formed using low-temperature atomic layer deposition. The titanium nitride silicon layer includes a lower part and an upper part, wherein the percentage of silicon atoms in the lower part is greater than the percentage of silicon atoms in the upper part, thereby replacing the titanium silicon formed by the high-temperature metal silicide process in the conventional art. This avoids the electromigration problem of the upper bit line conductive layer caused by high temperature, thereby improving the electrical properties and reliability of the semiconductor memory structure.

[0053] Although the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0054] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings: Figure 1 is a cross-sectional schematic diagram of a semiconductor memory structure according to some embodiments of the present invention. Figure 2 is a flowchart of a method for forming a titanium nitride silicon layer of a bit line in a semiconductor memory structure according to some embodiments of the present invention. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H are cross-sectional schematic diagrams of intermediate stages in forming the semiconductor memory structure shown in Figure 1 according to some embodiments of the present invention.

Claims

1. A semiconductor memory structure, comprising: One base; A first character line and a second character line are embedded in the substrate; And a bit line structure extending from the substrate between the first bit line and the second bit line to the substrate, wherein the bit line structure includes: a first conductive layer; a titanium nitride silicon layer located on the first conductive layer, wherein the titanium nitride silicon layer includes: a lower portion and an upper portion, wherein the silicon atom percentage of the lower portion is greater than the silicon atom percentage of the upper portion; and a second conductive layer located on the titanium nitride silicon layer.

2. The semiconductor memory structure as described in claim 1, wherein the percentage of silicon atoms in the lower portion is between 35% and 45%, and the percentage of silicon atoms in the upper portion is less than 5%.

3. The semiconductor memory structure as described in claim 1, wherein the percentage of titanium atoms in the lower portion is between 35% and 45%.

4. The semiconductor memory structure as claimed in claim 1, wherein the ratio of the percentage of titanium atoms to the percentage of silicon atoms in the lower portion is between 0.8 and 1.

2.

5. The semiconductor memory structure as claimed in claim 1, wherein the percentage of titanium atoms in the upper portion is between 60% and 80%, and the percentage of nitrogen atoms in the upper portion is between 15% and 35%.

6. The semiconductor memory structure as claimed in claim 1, wherein the ratio of the percentage of titanium atoms to the percentage of nitrogen atoms in the upper portion is between 1.8 and 5.

3.

7. The semiconductor memory structure as claimed in claim 1, wherein the upper portion has a first thickness, the lower portion has a second thickness, and the first thickness is greater than the second thickness.

8. The semiconductor memory structure as described in claim 7, wherein the ratio of the first thickness to the second thickness is between 3:2 and 4:

1.

9. The semiconductor memory structure as claimed in claim 1, wherein the first conductive layer comprises polysilicon and the second conductive layer comprises tungsten, aluminum, and / or copper.

10. A method for forming a semiconductor memory structure, comprising: Provide a base; A first character line and a second character line are formed and embedded in the substrate; and forming a bit line structure extending from the substrate between the first word line and the second word line to the substrate, wherein the bit line structure includes: a first conductive layer; a titanium nitride silicon layer located on the first conductive layer, wherein the titanium nitride silicon layer includes: a lower portion and an upper portion, wherein the silicon atom percentage of the lower portion is greater than the silicon atom percentage of the upper portion; and a second conductive layer located on the titanium nitride silicon layer.

11. A method for forming a semiconductor memory structure as described in claim 10, wherein forming the lower or upper portion of the titanium nitride silicon layer comprises: A titanium nitride process cycle is performed on an intermediate structure placed in a deposition chamber; The titanium nitride process cycle is repeated for a first number of times to form a titanium nitride molecular layer; a silicon nitride process cycle is performed on the titanium nitride molecular layer; the silicon nitride process cycle is repeated for a second number of times to form a silicon nitride molecular layer, and the silicon nitride molecular layer reacts with the titanium nitride molecular layer to complete a titanium silicon nitride process cycle, which is used to form a titanium silicon nitride molecular layer; and the titanium silicon nitride process cycle is repeated for a third number of times.

12. A method for forming a semiconductor memory structure as described in claim 11, wherein: During the formation of the lower portion of the titanium nitride silicon layer, the intermediate structure is a substrate having the first character line, the second character line, and the first conductive layer, and during the formation of the upper portion of the titanium nitride silicon layer, the intermediate structure is a substrate having the first character line, the second character line, the first conductive layer, and the lower portion.

13. The method for forming a semiconductor memory structure as described in claim 11, wherein performing the titanium nitride process cycle includes: (a) providing a pulse of a first precursor to the deposition chamber; (b) purging the deposition chamber after step (a); (c) providing a pulse of a second precursor to the deposition chamber after step (b) to form a titanium nitride monolayer; and (d) purging the deposition chamber after step (c).

14. The method for forming a semiconductor memory structure as described in claim 13, wherein performing the silicon nitride process cycle includes: (e) After step (d), a pulse of a third precursor is provided to the deposition chamber; (f) After step (e), the deposition chamber is cleaned; (g) After step (f), a pulse of the second precursor is provided to the deposition chamber to form a silicon nitride monolayer; and (h) After step (g), the deposition chamber is cleaned.

15. The method for forming a semiconductor memory structure as claimed in claim 11, wherein the ratio of the first number of times the upper portion of the titanium nitride silicon layer is formed to the second number of times is higher than that of the lower portion of the titanium nitride silicon layer.

16. The method of forming a semiconductor memory structure as claimed in claim 11, wherein the third number of the upper portion of the titanium nitride silicon layer is lower than that of the lower portion of the titanium nitride silicon layer.

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