Semiconductor devices and semiconductor memory devices

Abstract

The present invention provides a semiconductor device and a semiconductor memory device that can reduce parasitic capacitance between electrodes. The semiconductor device includes: a plurality of oxide semiconductors, each having a first end and a second end, extending in a first direction from the second end toward the first end; a plurality of first electrodes, each connected to the first end of the plurality of oxide semiconductors; a plurality of second electrodes, each connected to the second end of the plurality of oxide semiconductors; a gate electrode extending along a second direction intersecting the first direction, and a first insulating film surrounding each of the plurality of oxide semiconductors disposed along the second direction, separating the first end and the second end of each of the plurality of oxide semiconductors; and a cavity portion, at least a portion of which is disposed between two adjacent second electrodes.

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