Semiconductor memory devices

Abstract

A semiconductor memory device includes a channel pattern, a gate electrode layer configured to surround at least part of each of an upper surface and a lower surface of the channel pattern and extend in a first horizontal direction, a bit line structure connected to one end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction and configured to extend in a vertical direction, a capacitor structure connected to another end of the channel pattern in the second horizontal direction, a gate dielectric layer between the channel pattern and the gate electrode layer and configured to cover the upper surface, the lower surface, and both side surfaces, in the first horizontal direction, of the channel pattern, and a bit line shield structure on both sides of the bit line structure in the first horizontal direction and configured to extend in the vertical direction.

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