Patterning process and manufacturing method of gate structure of memory device

Abstract

Providing are a patterning process and a manufacturing method of gate structures of a memory device. The patterning process includes the following steps. A target layer is formed on a substrate. A patterned mask layer is formed on the target layer, wherein the patterned mask layer includes a first pattern and a second pattern, and the width of the first pattern is greater than the width of the second pattern. A sacrificial layer is conformally formed on the target layer. An ashing process is performed to remove the second pattern and at least a part of the first pattern from the sidewall of the first pattern through the sacrificial layer such that the first pattern has a reduced width. An anisotropic etching process is performed to remove a part of the sacrificial layer and a part of the target layer. The remaining sacrificial layer and the first pattern are removed.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing process, and more particularly to a patterning process and a method for manufacturing the gate structure of a memory element. Prior Technology

[0002] In current memory manufacturing, multiple patterning processes are typically used to form the gate structure within the memory cell. For example, self-aligned double patterning (SADP) can be used to form the gate structure. Furthermore, by combining the SADP process with additional lithography, a larger select gate structure can be formed around the gate structure of the memory cell. However, as device dimensions continue to shrink, the difficulty and cost of forming the select gate structure in this manner have increased significantly due to limitations in lithography equipment resolution. Summary of the Invention

[0003] The present invention provides a patterning process in which, after forming a patterned mask layer including a first pattern and a second pattern using a photolithography and etching processes, an ashing process is used to reduce the width of the first pattern and remove the second pattern.

[0004] The present invention provides a method for manufacturing a gate structure of a memory element, which uses the above-described patterning process to form the gate structure.

[0005] The patterning process of the present invention includes the following steps: A target layer is formed on a substrate. A patterned mask layer is formed on the target layer, wherein the patterned mask layer includes a first pattern and a second pattern, and the width of the first pattern is greater than the width of the second pattern. A sacrificial layer is conformally formed on the target layer. An ashing process is performed to remove the second pattern and at least a portion of the first pattern removed from the sidewalls of the first pattern through the sacrificial layer, such that the first pattern has a reduced width. An anisotropic etching process is performed to remove a portion of the sacrificial layer and a portion of the target layer. The remaining sacrificial layer and the first pattern are removed.

[0006] The method for manufacturing the gate structure of the memory element of the present invention includes the following steps: forming a tunneling dielectric layer on a substrate; forming a first gate material layer on the tunneling dielectric layer; forming an inter-gate dielectric material layer on the first gate material layer, wherein the inter-gate dielectric material layer has discontinuous regions; forming a second gate material layer on the inter-gate dielectric material layer; forming a hard mask material layer on the second gate material layer; forming a patterned mask layer on the hard mask material layer, wherein the patterned mask layer includes a first pattern and a plurality of second patterns, the first pattern being located above the discontinuous regions, and the width of the first pattern being greater than the width of the second patterns; conformally forming a sacrificial layer on the patterned mask layer; performing an ashing process to remove the second patterns and at least a portion of the first pattern removed from the sidewalls of the first pattern through the sacrificial layer, thereby reducing the width of the first pattern. An anisotropic etching process is performed to remove portions of the sacrificial layer, the hard mask material layer, the second gate material layer, the inter-gate dielectric material layer, and the first gate material layer. The remaining sacrificial layer and the first pattern are then removed.

[0007] Based on the above, in the patterning process and the method for manufacturing the gate structure of the memory element of the present invention, after forming a patterned mask layer including a first pattern and a second pattern with different widths, an ashing process is used to reduce the width of the first pattern and remove the second pattern to form a first pattern with the desired width. In this way, by using the first pattern as an etching mask, a target pattern with the desired width can be formed without being limited by the resolution of the lithography machine. Simple Explanation of the Diagram

[0008] Figures 1A to 1F are schematic cross-sectional views of the patterning process according to an embodiment of the present invention. Figures 2A to 2F are schematic cross-sectional flow diagrams of the manufacturing method of the gate structure according to an embodiment of the present invention. Implementation

[0009] Figures 1A to 1F are schematic cross-sectional views of the patterning process according to an embodiment of the present invention. The patterning process of this embodiment can pattern the target layer into a first pattern with a larger width and a second pattern with a smaller width, without requiring additional lithography processes to complement the multiple patterning processes. This reduces process costs and is not limited by the resolution of the lithography machine. This will be explained in detail below.

[0010] Referring to FIG1A, a target layer 102 is formed on a substrate 100. In this embodiment, no limitations are imposed on the substrate 100 and the target layer 102. For example, the substrate 100 may be a dielectric substrate, and the target layer 102 may be a conductive layer to be patterned.

[0011] Referring to FIG1B, a patterned mask layer 104 is formed on the target layer 102, and a cover layer 106 is formed on the patterned mask layer 104. The patterned mask layer 104 includes a first pattern 104A with a larger width and a plurality of second patterns 104B with smaller widths. In FIG1B, only two second patterns 104B are shown; however, a plurality of second patterns 104B may be present on each side of the first pattern 104A. In this step, since the width of the second patterns 104B does not exceed the resolution limit of the lithography machine, the patterned mask layer 104 can be formed using general lithography and etching processes. In this embodiment, the material of the patterned mask layer 104 is, for example, carbon or a carbon-containing material, and the material of the cover layer 106 is, for example, silicon oxynitride, but the invention is not limited thereto. Depending on the actual situation, the cover layer 106 may be omitted in other embodiments.

[0012] Subsequently, a sacrificial layer 108 is conformally formed on the target layer 102. The sacrificial layer 108 covers the sidewalls of the patterned mask layer 104, the cover layer 106 located on the patterned mask layer 104, and the exposed surface of the target layer 102. The material of the sacrificial layer 108 is, for example, silicon oxide, but the invention is not limited thereto. In this embodiment, the thickness of the sacrificial layer 108 is the same as the width of the second pattern 104B, but the invention is not limited thereto, as long as the sacrificial layer 108 does not fill the space between the first pattern 104A and the second pattern 104B, or the space between two adjacent second patterns 104B.

[0013] Referring to FIG1C, an ashing process 110 is performed to remove the second pattern 104B through the sacrificial layer 108, and to remove a portion of the first pattern 104A from the sidewall of the first pattern 104A, such that the first pattern 104A has a reduced width. A space S1 is formed after the removal of the portion of the first pattern 104A, and a space S2 is formed after the removal of the second pattern 104B. In this embodiment, the material of the patterned mask layer 104 is, for example, carbon, therefore the ashing process 110 is performed, for example, using oxygen plasma.

[0014] In detail, in this step, the ashing plasma used in the ashing process 110 can penetrate the sacrificial layer 108 to remove the patterned mask layer 104. Therefore, by controlling the process parameters of the ashing process 110 (e.g., ashing time), the second pattern 104B can be completely removed, and the first pattern 104A can be partially removed, thereby reducing the width of the first pattern 104A. In other words, even if the resolution of the lithography machine limits the direct use of conventional lithography and etching processes to form the first pattern 104A with the required width, the width of the first pattern 104A can be further reduced to the required level via the ashing process 110.

[0015] Furthermore, in this embodiment, since the cover layer 106 is located on the patterned mask layer 104, it can block the ashing plasma, preventing the upper portion of the first pattern 104A from being removed. In embodiments where the cover layer 106 is not formed, the ashing plasma used in the ashing process 110 removes a portion of the first pattern 104A from the sidewalls of the first pattern 104A, and also removes a portion of the first pattern 104A from the top surface of the first pattern 104A. In this case, the first pattern 104A has both a reduced width and a reduced thickness.

[0016] Referring to FIG1D, an anisotropic etching process is performed on the sacrificial layer 108 to remove a portion of the sacrificial layer 108, thereby forming a spacer composed of the sacrificial layer 108. In this step, the capping layer 106 is also removed, exposing spaces S1 and S2.

[0017] Referring to FIG1E, an anisotropic etching process is performed using a spacer composed of a sacrificial layer 108 and a first pattern 104A as an etching mask to remove a portion of the target layer 102, thereby forming a first target pattern 102A and a plurality of second target patterns 102B in the target layer 102. The width of the first target pattern 102A corresponds to the width of the first pattern 104A, and the pitch between adjacent second target patterns 102B corresponds to the width of space S2.

[0018] In detail, in this step, the etchant of the anisotropic etching process removes a portion of the target layer 102 towards the substrate 100, and the spacers formed by the sacrificial layer 108 and the first pattern 104A are also partially removed. Furthermore, since an etchant with a lower etching rate (higher selectivity) for the first pattern 104A and the sacrificial layer 108 can be selected, the target layer 102 below the first pattern 104A and the sacrificial layer 108 is not etched. Therefore, after the anisotropic etching process, a small amount of the first pattern 104A remains on the first target pattern 102A, and a small amount of the sacrificial layer 108 remains on the second target pattern 102B.

[0019] In another embodiment, it is not necessary to form additional spacers composed of sacrificial layer 108. Instead, an anisotropic etching process is performed after the steps described in FIG1C to remove a portion of sacrificial layer 108, cover layer 106, a portion of first pattern 104A and a portion of target layer 102 to form first target pattern 102A and second target pattern 102B.

[0020] In this embodiment, the spacing between the first target pattern 102A and the second target pattern 102B corresponds to the width of space S1. Since space S1 is formed by removing a portion of the first pattern 104A, the degree of removal of the first pattern 104A can be controlled by adjusting the time of the ashing process 110, thereby controlling the width of space S1 and thus controlling the spacing between the first target pattern 102A and the second target pattern 102B. Furthermore, since space S2 is formed by removing the second pattern 104B, the spacing between adjacent second target patterns 102B also corresponds to the width of the second pattern 104B, and therefore the spacing between adjacent second target patterns 102B can be controlled by adjusting the width of the second pattern 104B. In addition, since the second target pattern 102B is formed by performing an anisotropic etching process using a spacer composed of a sacrificial layer 108 as an etching mask, the width of the second target pattern 102B can be controlled by adjusting the thickness of the sacrificial layer 108.

[0021] Referring to Figure 1F, the first pattern 104A on the first target pattern 102A and the sacrificial layer 108 on the second target pattern 102B are removed. In this way, the target layer 102 is patterned to include the first target pattern 102A with a larger width and a plurality of second target patterns 102B with smaller widths, and the widths of the first target pattern 102A and the second target patterns 102B are not limited by the resolution of the lithography machine.

[0022] In this embodiment, after forming a patterned mask layer 104 using lithography and etching processes, an ashing process is used to reduce the width of the first pattern 104A and remove the second pattern 104B to form a first pattern 104A with the desired width. In this way, by using the first pattern 104A as an etching mask, a first target pattern 102A with the desired width can be formed, without being limited by the resolution of the lithography machine. Furthermore, the width of the subsequently formed first target pattern 102A and the spacing between the first target pattern 102A and the second target pattern 102B can be further controlled by controlling the process parameters (e.g., ashing time) of the ashing process 110.

[0023] In this embodiment, the first pattern 104A and the sacrificial layer 108 are formed on and in contact with the target layer 102. Therefore, the first pattern 104A and the sacrificial layer 108 can serve as a mask pattern to define the first target pattern 102A and the second target pattern 102B. However, the present invention is not limited to this. In other embodiments, depending on the actual situation, there may be at least one additional layer between the first pattern 104A and the sacrificial layer 108 and the target layer 102. The same technical means as in this embodiment can be used to first use the first pattern 104A and the sacrificial layer 108 as mask patterns to pattern the at least one additional layer, and then use the patterned at least one additional layer as a mask pattern to define the first target pattern 102A and the second target pattern 102B.

[0024] The patterning process of this embodiment can be used to form various semiconductor patterns, such as gate structures and select gate structures of memory cells with different widths in memory elements. This will be described in detail below.

[0025] Figures 2A to 2E are schematic cross-sectional flow diagrams illustrating the manufacturing method of the gate structure according to an embodiment of the present invention. In this embodiment, the same elements as in the above embodiments will be indicated by the same reference numerals and will not be described further.

[0026] Referring to FIG2A, a tunneling dielectric layer 201, a gate material layer 202, an inter-gate dielectric layer 204, a gate material layer 206, and a hard mask material layer 208 are sequentially formed on a substrate 200. The substrate 200 is, for example, a silicon substrate. The tunneling dielectric layer 201 is, for example, a silicon oxide layer. The gate material layers 202 and 206 are, for example, polycrystalline silicon layers. The hard mask material layer 208 is, for example, a silicon nitride layer. Furthermore, the inter-gate dielectric layer has a discontinuity region R. Therefore, in the discontinuity region R, the gate material layer 206 can penetrate the tunneling dielectric layer 201 and contact the gate material layer 202.

[0027] Referring to Figure 2B, the steps described in Figure 1B are performed to form a first pattern 104A with a larger width, a plurality of second patterns 104B with smaller widths, and a cover layer 106 on the rigid masking material layer 208. Depending on the actual situation, the cover layer 106 may be omitted in other embodiments. In this embodiment, the first pattern 104A is located above the discontinuous region R, and the first pattern 104A overlaps with the discontinuous region R. Subsequently, a sacrificial layer 108 is conformally formed on the rigid masking material layer 208. In this embodiment, since the width of the gate structure of the subsequently formed memory cell and the spacing between adjacent gate structures are the same, the thickness of the sacrificial layer 108 will be the same as the width of the second patterns 104B.

[0028] Referring to FIG2C, the steps described in FIG1C are performed, including an ashing process 110, to remove the second pattern 104B through the sacrificial layer 108, and to remove a portion of the first pattern 104A from the sidewall of the first pattern 104A, so that the first pattern 104A has a reduced width and forms spaces S1 and S2. In this step, after removing a portion of the first pattern 104A from the sidewall of the first pattern 104A, the first pattern 104A can still overlap with the discontinuous region R.

[0029] Referring to Figure 2D, following the steps described in Figure 1D, an anisotropic etching process is performed on the sacrificial layer 108 to remove a portion of the sacrificial layer 108, thereby forming a spacer composed of the sacrificial layer 108. In this step, the cover layer 106 is also removed, exposing spaces S1 and S2.

[0030] Referring to Figure 2E, following the steps described in Figure 1E, an anisotropic etching process is performed to remove portions of the hard mask material layer 208, the second gate material layer 206, the inter-gate dielectric material layer 204, and the gate material layer 202, thereby forming a gate structure GS1 and multiple gate structures GS2 on the tunneling dielectric layer 201. Then, following the steps described in Figure 1F, the first pattern 104A on the gate structure GS1 and the sacrificial layer 108 on the gate structure GS2 are removed.

[0031] Thus, the gate structure GS1 with a larger width includes a gate material layer 202, an inter-gate dielectric material layer 204 with a discontinuous region R, a second gate material layer 206, and a hard mask material layer 208, while the gate structure GS2 with a smaller width includes a first gate material layer 202, a continuous inter-gate dielectric material layer 204, a second gate material layer 206, and a hard mask material layer 208.

[0032] In this embodiment, the spacing between gate structure GS1 and gate structure GS2 corresponds to the width of space S1. Therefore, the width of space S1 can be controlled by adjusting the time of the ashing process 110, thereby controlling the spacing between gate structure GS1 and gate structure GS2. Furthermore, the spacing between adjacent gate structures GS2 also corresponds to the width of the second pattern 104B, so the spacing between adjacent gate structures GS2 can be controlled by adjusting the width of the second pattern 104B. Additionally, the width of the second target pattern 102B corresponds to the width (thickness) of the spacer formed by the sacrificial layer 108, so the width of the gate structure GS2 can be controlled by adjusting the thickness of the sacrificial layer 108.

[0033] Referring to Figure 2F, the gate structure GS1 is patterned to form a pair of gate structures GS3, each gate structure GS3 including a discontinuous inter-gate dielectric material layer 204. Furthermore, the width of the gate structure GS3 is greater than the width of the gate structure GS2. In this way, the gate structure of the memory element of this embodiment is formed.

[0034] The gate structure of the memory element in this embodiment includes a gate structure GS3 with a larger width and a gate structure GS2 with a smaller width. The gate structure GS2, located on the tunneling dielectric layer 201, can serve as the gate structure of the memory cell. Therefore, the gate structure GS2 includes a floating gate formed by a gate material layer 202, an inter-gate dielectric layer formed by an inter-gate dielectric material layer 204, a control gate formed by a gate material layer 206, and a hard mask layer 208. Furthermore, the gate structure GS3 on the tunneling dielectric layer 201 can serve as a selection gate structure. Therefore, the gate structure GS3 includes a selection gate formed by a first gate material layer 202 and a second gate material layer 206 connected to each other, and a hard mask layer formed by the hard mask material layer 208. Additionally, the tunneling dielectric layer 201 below the gate structure GS3 can serve as a gate dielectric layer.

[0035] In this embodiment, after forming the patterned mask layer 104 using lithography and etching processes, an ashing process is used to reduce the width of the first pattern 104A and remove the second pattern 104B to form a first pattern 104A with the desired width. In this way, by using the first pattern 104A as an etching mask and subsequent patterning processes, a gate structure GS3 with the desired width can be formed, without being limited by the resolution of the lithography machine. Furthermore, the width of the subsequently formed gate structure GS3 and the spacing between the gate structure GS3 and the gate structure GS2 can be further controlled by controlling the process parameters (e.g., ashing time) of the ashing process 110.

[0036] Furthermore, in this embodiment, the required number of gate structures GS2 can be formed by adjusting the number of the second pattern 104B. Therefore, as the size of the component continues to decrease, a greater number of gate structures GS2 can be formed without being limited by the resolution of the lithography machine, allowing a greater number of gate structures GS2 adjacent to the gate structure GS3 to serve as dummy memory units.

[0037] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0038] 100, 200: Base 102: Target Layer 102A: First target pattern 102B: Second target pattern 104: Patterned dome layer 104A: First Pattern 104B: Second Pattern 106: Overlay 108: Sacrifice Layer 110: Ashing process 201: Tunneling Dielectric Layer 202: Gate material layer 204: Inter-gate dielectric material layer 206: Gate material layer 208: Rigid curtain material layer GS1: Gate structure GS2: Gate structure GS3: Gate structure R: Discontinuous region S1, S2: Space

Claims

1. A patterning process, comprising: The target layer is formed on the substrate; A patterned mask layer is formed on the target layer, wherein the patterned mask layer includes a first pattern and a second pattern, and the width of the first pattern is greater than the width of the second pattern; a sacrificial layer is conformally formed on the target layer; an ashing process is performed to remove the second pattern and at least a portion of the first pattern removed from the sidewalls of the first pattern through the sacrificial layer, such that the first pattern has a reduced width; an anisotropic etching process is performed to remove a portion of the sacrificial layer and a portion of the target layer; And remove the remaining sacrificial layer and the first pattern.

2. The patterning process as described in claim 1, wherein the material of the patterned mask layer includes carbon or a carbon-containing material.

3. The patterning process as described in claim 2, wherein the ashing process is performed using oxygen plasma.

4. The patterning process as described in claim 1, wherein the thickness of the sacrificial layer is the same as the width of the second pattern.

5. The patterning process as claimed in claim 1, wherein after the anisotropic etching process, the target layer includes a first target pattern and a second target pattern, and the width of the first target pattern is greater than the width of the second target pattern.

6. The patterning process as described in claim 1, wherein the anisotropic etching process includes: The sacrificial layer is subjected to a first anisotropic etching process to form a spacer; And using the spacer and the first pattern as an etching mask, a second anisotropic etching process is performed.

7. A method for manufacturing the gate structure of a memory element, comprising: A tunneling dielectric layer is formed on the substrate; A first gate material layer is formed on the tunneling dielectric layer; An inter-gate dielectric material layer is formed on the first gate material layer, wherein the inter-gate dielectric material layer has discontinuous regions; a second gate material layer is formed on the inter-gate dielectric material layer; a hard mask material layer is formed on the second gate material layer; a patterned mask layer is formed on the hard mask material layer, wherein the patterned mask layer includes a first pattern and a plurality of second patterns, the first pattern being located above the discontinuous regions, and the width of the first pattern being greater than the width of the second patterns; a sacrificial layer is conformally formed on the patterned mask layer; an ashing process is performed to remove the second patterns and at least a portion of the first pattern removed from the sidewalls of the first pattern through the sacrificial layer, such that the first pattern has a reduced width; an anisotropic etching process is performed to remove portions of the sacrificial layer, portions of the hard mask material layer, portions of the second gate material layer, portions of the inter-gate dielectric material layer, and portions of the first gate material layer; And remove the remaining sacrificial layer and the first pattern.

8. A method for manufacturing the gate structure of a memory element as claimed in claim 7, wherein the material of the patterned mask layer includes carbon or a carbon-containing material.

9. A method for manufacturing the gate structure of a memory element as claimed in claim 8, wherein the ashing process is performed using oxygen plasma.

10. A method for manufacturing the gate structure of a memory element as claimed in claim 7, wherein the thickness of the sacrificial layer is the same as the width of the second pattern.

11. A method for manufacturing a gate structure of a memory element as claimed in claim 7, wherein after the anisotropic etching process is performed, a first gate structure and a plurality of second gate structures are formed on the substrate, and the width of the first gate structure is greater than the width of the second gate structures.

12. A method of manufacturing a gate structure for a memory element as claimed in claim 11, wherein the second gate structure comprises, sequentially formed on the tunneling dielectric layer, a floating gate formed of the first gate material layer, an inter-gate dielectric layer formed of the inter-gate dielectric material layer, a control gate formed of the second gate material layer, and a hard mask layer formed of the hard mask material layer.

13. The method of manufacturing the gate structure of the memory element as claimed in claim 11, further comprising patterning the first gate structure to form a pair of third gate structures, wherein the inter-gate dielectric material layer in the third gate structure does not completely separate the first gate material layer from the second gate material layer.

14. A method for manufacturing the gate structure of a memory element as claimed in claim 7, wherein the anisotropic etching process includes: The sacrificial layer is subjected to a first anisotropic etching process to form a spacer; And using the spacer and the first pattern as an etching mask, a second anisotropic etching process is performed.

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