Semiconductor memory devices

Abstract

A highly integrated semiconductor memory device is provided. The semiconductor memory device includes a first chip, a second chip, and a third chip. The first chip includes: a plurality of first structures arranged side-by-side in a first direction and comprising first memory cells; and a first bit line connected to the plurality of first structures. The second chip includes: a plurality of second structures arranged side-by-side in a first direction and comprising a plurality of second memory cells; and a second bit line connected to the plurality of second structures; and a first via contact electrode electrically connected to the first bit line and the second bit line. The third chip includes: a first transistor electrically connected to the first bit line and the second bit line. One of the plurality of first structures is positioned at a location that overlaps with the first via contact electrode when viewed from a second direction, and is capable of storing data.

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