RRAM memory cell structure

Abstract

A resistive random access memory (RRAM) memory cell structure includes a transistor formed on a semiconductor substrate and includes a source region, a drain region and a gate, a lower electrode disposed over the semiconductor substrate and electrically connected to the drain region, a source line electrically connected to the source region, a word line electrically connected to the gate, first and second blocks of resistive switching dielectric material electrically connected to the lower electrode, a first upper electrode electrically connected to the first block of resistive switching dielectric material, a second upper electrode electrically connected to the second block of resistive switching dielectric material, and first and second bit lines electrically connected to the first and second upper electrodes respectively. The first bit line and the second bit line are electrically isolated from each other except for the first and second blocks of resistive switching dielectric material.

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