Transistor structure with metal gate and fabricating method of the same

Abstract

A transistor structure with a metal gate includes a semiconductor substrate. A dielectric layer covers the semiconductor substrate, and a recess is formed in the dielectric layer. A metal gate is disposed in the recess, and a U-shaped composite layer is disposed at two sides and a bottom of the metal gate. The top surface of the metal gate protrudes from two ends of the U-shaped composite layer. A cap layer is placed in the recess and disposed on the metal gate and U-shaped composite layer. The cap layer includes a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, and a silicon oxide block. The silicon oxide block is disposed at the center of the cap layer. The silicon oxynitride layer, the second silicon nitride layer, and the first silicon nitride layer surround the silicon oxide block sequentially in a listed order from closer to the silicon oxide block to farther from the silicon oxide block. The nitrogen-to-silicon atomic ratio in the second silicon nitride layer is between

Claims

1. A transistor structure having a metal gate, comprising: a semiconductor substrate; a dielectric layer covering the semiconductor substrate; a groove disposed in the dielectric layer; a metal gate disposed in the groove; a U-shaped composite layer located on both sides and bottom of the metal gate, the top surface of the metal gate protruding from the two ends of the U-shaped composite layer; and a capping layer disposed in the groove and on the metal gate and the U-shaped composite layer, wherein the capping layer comprises a first silicon nitride layer, a second silicon nitride layer, a silicon oxynitride layer, and a silicon oxide block, the silicon oxide block being located at the center of the capping layer, the silicon oxynitride layer, the second silicon nitride layer, and the first silicon nitride layer sequentially surrounding the silicon oxide block in order from closest to furthest from the silicon oxide block; wherein the atomic ratio of nitrogen to silicon in the second silicon nitride layer is between 0.6 and 1.

2.

2. The transistor structure with a metal gate as described in claim 1, wherein the atomic ratio of nitrogen to silicon in the first silicon nitride layer is between 1.2 and 1.

4.

3. The transistor structure with a metal gate as described in claim 1, wherein the nitrogen-to-silicon atomic ratio of the first silicon nitride layer is greater than the nitrogen-to-silicon atomic ratio of the second silicon nitride layer.

4. The transistor structure with a metal gate as described in claim 3, wherein the atomic ratio of nitrogen to silicon in the second silicon nitride layer is greater than the atomic ratio of nitrogen to silicon in the silicon oxynitride layer.

5. The transistor structure with a metal gate as described in claim 1, wherein the first silicon nitride layer has compressive stress, the second silicon nitride layer has neutral stress, and the silicon oxide block has tensile stress.

6. The transistor structure with a metal gate as described in claim 1, wherein the thickness of the second silicon nitride layer is greater than the thickness of the silicon oxynitride layer.

7. The transistor structure with a metal gate as described in claim 1, wherein the bottom of the top cover layer includes a notch, and the top surface of the metal gate is embedded in the notch.

8. The transistor structure with a metal gate as described in claim 7, wherein the first silicon nitride layer, the second silicon nitride layer, and the silicon oxynitride layer together form a trench profile, and the bottom of the trench profile includes the notch.

9. The transistor structure with a metal gate as described in claim 1, wherein the U-shaped composite layer comprises a high-dielectric material layer, at least one work function layer and at least one buffer layer.

10. The transistor structure with a metal gate as described in claim 1, wherein diluted hydrofluoric acid is used as an etchant, and the etching rate of the diluted hydrofluoric acid on the second silicon nitride layer is less than the etching rate on the first silicon nitride layer.

11. A method for fabricating a transistor structure with a metal gate, comprising: providing a semiconductor substrate, a dielectric layer covering the semiconductor substrate, a groove disposed in the dielectric layer, a metal gate disposed in the groove, a U-shaped composite layer located on both sides and bottom of the metal gate, the top surface of the metal gate protruding from the two ends of the U-shaped composite layer; forming a capping layer disposed in the groove and located on the metal gate and the U-shaped composite layer, the capping layer being formed comprising: performing a first deposition process to form a first silicon nitride layer covering and contacting the metal gate and the U-shaped composite layer, wherein the first deposition process includes using a first operating power and inputting a first silicon-containing gas; performing a second deposition process to form a second silicon nitride layer covering and contacting the first silicon nitride layer, wherein the second deposition process includes using 0.3 to 0.7 times the first operating power and inputting 0.3 to 0.7 times the first silicon-containing gas; A silicon oxide block is formed to cover and contact the second silicon nitride layer; and after the silicon oxide block is formed, a silicon oxynitride layer is formed between the silicon oxide block and the second silicon nitride layer.

12. A method for fabricating a transistor structure having a metal gate as described in claim 11, wherein the silicon oxynitride layer is formed by directly contacting the second silicon nitride layer with the silicon oxide block.

13. A method for fabricating a transistor structure with a metal gate as described in claim 11, wherein the first operating power is between 160 and 350 watts, and the flow rate of the first silicon-containing gas is between 50 and 150 standard cubic centimeters per minute (sccm).

14. A method for fabricating a transistor structure with a metal gate as described in claim 11, wherein the formation of the top cover layer further comprises: when forming the first silicon nitride layer, the first silicon nitride layer covers and contacts the dielectric layer on the upper surface outside the groove; when forming the second silicon nitride layer, the second silicon nitride layer covers the dielectric layer on the upper surface outside the groove; forming a silicon oxide layer to fill the groove and the second silicon nitride layer covering the groove; forming the silicon oxynitride layer; and performing a removal process, using the first silicon nitride layer as a removal stop layer, removing the silicon oxide layer, the silicon oxynitride layer and the second silicon nitride layer outside the groove, wherein the silicon oxide layer remaining in the groove becomes the silicon oxide block.

15. A method for fabricating a transistor structure with a metal gate as described in claim 14, wherein the removal process is dry etching or chemical mechanical polishing.

16. A method for fabricating a transistor structure having a metal gate as described in claim 11, wherein the atomic ratio of nitrogen to silicon in the second silicon nitride layer is between 0.6 and 1.

2.

17. A method for fabricating a transistor structure having a metal gate as described in claim 11, wherein the nitrogen-to-silicon atomic ratio of the first silicon nitride layer is between 1.2 and 1.

4.

18. A method for fabricating a transistor structure with a metal gate as described in claim 11, wherein the first silicon nitride layer has compressive stress, the second silicon nitride layer has neutral stress, and the silicon oxide block has tensile stress.

19. A method for fabricating a transistor structure having a metal gate as described in claim 11, wherein diluted hydrofluoric acid is used as an etchant, and the etching rate of the diluted hydrofluoric acid on the second silicon nitride layer is less than the etching rate on the first silicon nitride layer.

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